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@ -1764,7 +1764,7 @@ static DisasASI resolve_asi(DisasContext *dc, int asi, MemOp memop) |
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case ASI_FL16_SL: |
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case ASI_FL16_P: |
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case ASI_FL16_PL: |
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memop = MO_TEUW; |
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memop = MO_BEUW; |
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type = GET_ASI_SHORT; |
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break; |
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} |
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@ -2215,7 +2215,7 @@ static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) |
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* byte swapped. We perform one 128-bit LE load, so must swap |
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* the order of the writebacks. |
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*/ |
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if ((mop & MO_BSWAP) == MO_TE) { |
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if ((mop & MO_BSWAP) == MO_BE) { |
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tcg_gen_extr_i128_i64(lo, hi, t); |
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} else { |
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tcg_gen_extr_i128_i64(hi, lo, t); |
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@ -2235,7 +2235,7 @@ static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) |
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/* Note that LE ldda acts as if each 32-bit register
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result is byte swapped. Having just performed one |
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64-bit bswap, we need now to swap the writebacks. */ |
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if ((da->memop & MO_BSWAP) == MO_TE) { |
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if ((da->memop & MO_BSWAP) == MO_BE) { |
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tcg_gen_extr_i64_tl(lo, hi, tmp); |
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} else { |
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tcg_gen_extr_i64_tl(hi, lo, tmp); |
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@ -2252,7 +2252,7 @@ static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) |
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gen_helper_ld_code(tmp, tcg_env, addr, tcg_constant_i32(oi)); |
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/* See above. */ |
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if ((da->memop & MO_BSWAP) == MO_TE) { |
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if ((da->memop & MO_BSWAP) == MO_BE) { |
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tcg_gen_extr_i64_tl(lo, hi, tmp); |
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} else { |
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tcg_gen_extr_i64_tl(hi, lo, tmp); |
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@ -2277,7 +2277,7 @@ static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) |
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gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop); |
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/* See above. */ |
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if ((da->memop & MO_BSWAP) == MO_TE) { |
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if ((da->memop & MO_BSWAP) == MO_BE) { |
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tcg_gen_extr_i64_tl(lo, hi, tmp); |
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} else { |
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tcg_gen_extr_i64_tl(hi, lo, tmp); |
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@ -2310,7 +2310,7 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) |
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* byte swapped. We perform one 128-bit LE store, so must swap |
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* the order of the construction. |
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*/ |
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if ((mop & MO_BSWAP) == MO_TE) { |
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if ((mop & MO_BSWAP) == MO_BE) { |
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tcg_gen_concat_i64_i128(t, lo, hi); |
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} else { |
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tcg_gen_concat_i64_i128(t, hi, lo); |
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@ -2329,7 +2329,7 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) |
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/* Note that LE stda acts as if each 32-bit register result is
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byte swapped. We will perform one 64-bit LE store, so now |
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we must swap the order of the construction. */ |
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if ((da->memop & MO_BSWAP) == MO_TE) { |
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if ((da->memop & MO_BSWAP) == MO_BE) { |
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tcg_gen_concat_tl_i64(t64, lo, hi); |
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} else { |
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tcg_gen_concat_tl_i64(t64, hi, lo); |
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@ -2345,7 +2345,7 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) |
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* See comments for GET_ASI_COPY above. |
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*/ |
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{ |
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MemOp mop = MO_TE | MO_128 | MO_ATOM_IFALIGN_PAIR; |
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MemOp mop = MO_BE | MO_128 | MO_ATOM_IFALIGN_PAIR; |
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TCGv_i64 t8 = tcg_temp_new_i64(); |
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TCGv_i128 t16 = tcg_temp_new_i128(); |
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TCGv daddr = tcg_temp_new(); |
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@ -2368,7 +2368,7 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) |
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TCGv_i64 t64 = tcg_temp_new_i64(); |
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/* See above. */ |
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if ((da->memop & MO_BSWAP) == MO_TE) { |
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if ((da->memop & MO_BSWAP) == MO_BE) { |
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tcg_gen_concat_tl_i64(t64, lo, hi); |
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} else { |
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tcg_gen_concat_tl_i64(t64, hi, lo); |
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@ -4428,13 +4428,13 @@ static bool do_ld_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) |
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return advance_pc(dc); |
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} |
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TRANS(LDUW, ALL, do_ld_gpr, a, MO_TEUL) |
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TRANS(LDUW, ALL, do_ld_gpr, a, MO_BEUL) |
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TRANS(LDUB, ALL, do_ld_gpr, a, MO_UB) |
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TRANS(LDUH, ALL, do_ld_gpr, a, MO_TEUW) |
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TRANS(LDUH, ALL, do_ld_gpr, a, MO_BEUW) |
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TRANS(LDSB, ALL, do_ld_gpr, a, MO_SB) |
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TRANS(LDSH, ALL, do_ld_gpr, a, MO_TESW) |
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TRANS(LDSW, 64, do_ld_gpr, a, MO_TESL) |
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TRANS(LDX, 64, do_ld_gpr, a, MO_TEUQ) |
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TRANS(LDSH, ALL, do_ld_gpr, a, MO_BESW) |
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TRANS(LDSW, 64, do_ld_gpr, a, MO_BESL) |
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TRANS(LDX, 64, do_ld_gpr, a, MO_BEUQ) |
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static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) |
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{ |
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@ -4451,10 +4451,10 @@ static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) |
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return advance_pc(dc); |
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} |
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TRANS(STW, ALL, do_st_gpr, a, MO_TEUL) |
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TRANS(STW, ALL, do_st_gpr, a, MO_BEUL) |
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TRANS(STB, ALL, do_st_gpr, a, MO_UB) |
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TRANS(STH, ALL, do_st_gpr, a, MO_TEUW) |
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TRANS(STX, 64, do_st_gpr, a, MO_TEUQ) |
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TRANS(STH, ALL, do_st_gpr, a, MO_BEUW) |
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TRANS(STX, 64, do_st_gpr, a, MO_BEUQ) |
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static bool trans_LDD(DisasContext *dc, arg_r_r_ri_asi *a) |
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{ |
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@ -4468,7 +4468,7 @@ static bool trans_LDD(DisasContext *dc, arg_r_r_ri_asi *a) |
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if (addr == NULL) { |
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return false; |
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} |
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da = resolve_asi(dc, a->asi, MO_TEUQ); |
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da = resolve_asi(dc, a->asi, MO_BEUQ); |
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gen_ldda_asi(dc, &da, addr, a->rd); |
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return advance_pc(dc); |
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} |
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@ -4485,7 +4485,7 @@ static bool trans_STD(DisasContext *dc, arg_r_r_ri_asi *a) |
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if (addr == NULL) { |
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return false; |
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} |
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da = resolve_asi(dc, a->asi, MO_TEUQ); |
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da = resolve_asi(dc, a->asi, MO_BEUQ); |
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gen_stda_asi(dc, &da, addr, a->rd); |
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return advance_pc(dc); |
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} |
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@ -4516,7 +4516,7 @@ static bool trans_SWAP(DisasContext *dc, arg_r_r_ri_asi *a) |
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if (addr == NULL) { |
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return false; |
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} |
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da = resolve_asi(dc, a->asi, MO_TEUL); |
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da = resolve_asi(dc, a->asi, MO_BEUL); |
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dst = gen_dest_gpr(dc, a->rd); |
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src = gen_load_gpr(dc, a->rd); |
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@ -4544,8 +4544,8 @@ static bool do_casa(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) |
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return advance_pc(dc); |
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} |
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TRANS(CASA, CASA, do_casa, a, MO_TEUL) |
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TRANS(CASXA, 64, do_casa, a, MO_TEUQ) |
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TRANS(CASA, CASA, do_casa, a, MO_BEUL) |
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TRANS(CASXA, 64, do_casa, a, MO_BEUQ) |
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static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz) |
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{ |
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@ -4561,7 +4561,7 @@ static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz) |
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if (sz == MO_128 && gen_trap_float128(dc)) { |
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return true; |
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} |
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da = resolve_asi(dc, a->asi, MO_TE | sz); |
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da = resolve_asi(dc, a->asi, MO_BE | sz); |
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gen_ldf_asi(dc, &da, sz, addr, a->rd); |
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gen_update_fprs_dirty(dc, a->rd); |
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return advance_pc(dc); |
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@ -4590,7 +4590,7 @@ static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz) |
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if (sz == MO_128 && gen_trap_float128(dc)) { |
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return true; |
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} |
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da = resolve_asi(dc, a->asi, MO_TE | sz); |
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da = resolve_asi(dc, a->asi, MO_BE | sz); |
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gen_stf_asi(dc, &da, sz, addr, a->rd); |
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return advance_pc(dc); |
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} |
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@ -4629,7 +4629,7 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a) |
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/* Store the single element from the queue. */ |
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TCGv_i64 fq = tcg_temp_new_i64(); |
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tcg_gen_ld_i64(fq, tcg_env, offsetof(CPUSPARCState, fq.d)); |
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tcg_gen_qemu_st_i64(fq, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN_4); |
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tcg_gen_qemu_st_i64(fq, addr, dc->mem_idx, MO_BEUQ | MO_ALIGN_4); |
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/* Mark the queue empty, transitioning to fp_execute state. */ |
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tcg_gen_st_i32(tcg_constant_i32(0), tcg_env, |
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@ -4655,7 +4655,7 @@ static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a) |
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} |
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tmp = tcg_temp_new_i32(); |
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tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_TEUL | MO_ALIGN); |
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tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_BEUL | MO_ALIGN); |
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tcg_gen_extract_i32(cpu_fcc[0], tmp, FSR_FCC0_SHIFT, 2); |
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/* LDFSR does not change FCC[1-3]. */ |
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@ -4679,7 +4679,7 @@ static bool do_ldxfsr(DisasContext *dc, arg_r_r_ri *a, bool entire) |
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} |
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t64 = tcg_temp_new_i64(); |
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tcg_gen_qemu_ld_i64(t64, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN); |
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tcg_gen_qemu_ld_i64(t64, addr, dc->mem_idx, MO_BEUQ | MO_ALIGN); |
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lo = tcg_temp_new_i32(); |
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hi = cpu_fcc[3]; |
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@ -4722,8 +4722,8 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) |
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return advance_pc(dc); |
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} |
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TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL) |
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TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ) |
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TRANS(STFSR, ALL, do_stfsr, a, MO_BEUL) |
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TRANS(STXFSR, 64, do_stfsr, a, MO_BEUQ) |
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static bool do_fc(DisasContext *dc, int rd, int32_t c) |
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{ |
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Peter Maydell
2 months ago