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target-ppc: Add VSX Vector Compare Instructions 

This patch adds the VSX floating point compare vector instructions:

  - xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.]
  - xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.]

Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
pull/7/head
Tom Musta 13 years ago
committed by Alexander Graf
parent
959e9c9d1e
commit
354a6decf1
3 changed files with 86 additions and 0 deletions
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  1. 57
      target-ppc/fpu_helper.c
  2. 6
      target-ppc/helper.h
  3. 23
      target-ppc/translate.c

57
target-ppc/fpu_helper.c
View File

@ -2327,3 +2327,60 @@ VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, f32)
VSX_MAX_MIN(xsmindp, minnum, 1, float64, f64)
VSX_MAX_MIN(xvmindp, minnum, 2, float64, f64)
VSX_MAX_MIN(xvminsp, minnum, 4, float32, f32)
/* VSX_CMP - VSX floating point compare
* op - instruction mnemonic
* nels - number of elements (1, 2 or 4)
* tp - type (float32 or float64)
* fld - vsr_t field (f32 or f64)
* cmp - comparison operation
* svxvc - set VXVC bit
*/
#define VSX_CMP(op, nels, tp, fld, cmp, svxvc) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
{ \
ppc_vsr_t xt, xa, xb; \
int i; \
int all_true = 1; \
int all_false = 1; \
\
getVSR(xA(opcode), &xa, env); \
getVSR(xB(opcode), &xb, env); \
getVSR(xT(opcode), &xt, env); \
\
for (i = 0; i < nels; i++) { \
if (unlikely(tp##_is_any_nan(xa.fld[i]) || \
tp##_is_any_nan(xb.fld[i]))) { \
if (tp##_is_signaling_nan(xa.fld[i]) || \
tp##_is_signaling_nan(xb.fld[i])) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
} \
if (svxvc) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
} \
xt.fld[i] = 0; \
all_true = 0; \
} else { \
if (tp##_##cmp(xb.fld[i], xa.fld[i], &env->fp_status) == 1) { \
xt.fld[i] = -1; \
all_false = 0; \
} else { \
xt.fld[i] = 0; \
all_true = 0; \
} \
} \
} \
\
putVSR(xT(opcode), &xt, env); \
if ((opcode >> (31-21)) & 1) { \
env->crf[6] = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
} \
helper_float_check_status(env); \
}
VSX_CMP(xvcmpeqdp, 2, float64, f64, eq, 0)
VSX_CMP(xvcmpgedp, 2, float64, f64, le, 1)
VSX_CMP(xvcmpgtdp, 2, float64, f64, lt, 1)
VSX_CMP(xvcmpeqsp, 4, float32, f32, eq, 0)
VSX_CMP(xvcmpgesp, 4, float32, f32, le, 1)
VSX_CMP(xvcmpgtsp, 4, float32, f32, lt, 1)

6
target-ppc/helper.h
View File

@ -292,6 +292,9 @@ DEF_HELPER_2(xvnmsubadp, void, env, i32)
DEF_HELPER_2(xvnmsubmdp, void, env, i32)
DEF_HELPER_2(xvmaxdp, void, env, i32)
DEF_HELPER_2(xvmindp, void, env, i32)
DEF_HELPER_2(xvcmpeqdp, void, env, i32)
DEF_HELPER_2(xvcmpgedp, void, env, i32)
DEF_HELPER_2(xvcmpgtdp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
@ -312,6 +315,9 @@ DEF_HELPER_2(xvnmsubasp, void, env, i32)
DEF_HELPER_2(xvnmsubmsp, void, env, i32)
DEF_HELPER_2(xvmaxsp, void, env, i32)
DEF_HELPER_2(xvminsp, void, env, i32)
DEF_HELPER_2(xvcmpeqsp, void, env, i32)
DEF_HELPER_2(xvcmpgesp, void, env, i32)
DEF_HELPER_2(xvcmpgtsp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)

23
target-ppc/translate.c
View File

@ -7345,6 +7345,9 @@ GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
@ -7365,6 +7368,9 @@ GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
#define VSX_LOGICAL(name, tcg_op) \
static void glue(gen_, name)(DisasContext * ctx) \
@ -10014,6 +10020,17 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
#undef GEN_XX3_RC_FORM
#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
#undef GEN_XX3FORM_DM
#define GEN_XX3FORM_DM(name, opc2, opc3) \
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
@ -10088,6 +10105,9 @@ GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
@ -10108,6 +10128,9 @@ GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
#undef VSX_LOGICAL
#define VSX_LOGICAL(name, opc2, opc3, fl2) \

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