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This is OpenCores Ethernet MAC + subset of National Semiconductors DP83838C PHY. OpenCores Ethernet MAC project: http://opencores.org/project,ethmac Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>stable-1.0
Max Filippov
15 years ago
committed by
Blue Swirl
Blue Swirl
3 changed files with 743 additions and 0 deletions
@ -0,0 +1,728 @@ |
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/*
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* OpenCores Ethernet MAC 10/100 + subset of |
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* National Semiconductors DP83848C 10/100 PHY |
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* |
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* http://opencores.org/svnget,ethmac?file=%2Ftrunk%2F%2Fdoc%2Feth_speci.pdf
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* http://cache.national.com/ds/DP/DP83848C.pdf
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* |
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* * Neither the name of the Open Source and Linux Lab nor the |
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* names of its contributors may be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#include "hw.h" |
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#include "sysbus.h" |
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#include "net.h" |
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#include "sysemu.h" |
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#include "trace.h" |
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/* RECSMALL is not used because it breaks tap networking in linux:
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* incoming ARP responses are too short |
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*/ |
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#undef USE_RECSMALL |
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#define GET_FIELD(v, field) (((v) & (field)) >> (field ## _LBN)) |
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#define GET_REGBIT(s, reg, field) ((s)->regs[reg] & (reg ## _ ## field)) |
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#define GET_REGFIELD(s, reg, field) \ |
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GET_FIELD((s)->regs[reg], reg ## _ ## field) |
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#define SET_FIELD(v, field, data) \ |
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((v) = (((v) & ~(field)) | (((data) << (field ## _LBN)) & (field)))) |
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#define SET_REGFIELD(s, reg, field, data) \ |
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SET_FIELD((s)->regs[reg], reg ## _ ## field, data) |
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/* PHY MII registers */ |
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enum { |
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MII_BMCR, |
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MII_BMSR, |
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MII_PHYIDR1, |
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MII_PHYIDR2, |
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MII_ANAR, |
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MII_ANLPAR, |
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MII_REG_MAX = 16, |
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}; |
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typedef struct Mii { |
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uint16_t regs[MII_REG_MAX]; |
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bool link_ok; |
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} Mii; |
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static void mii_set_link(Mii *s, bool link_ok) |
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{ |
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if (link_ok) { |
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s->regs[MII_BMSR] |= 0x4; |
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s->regs[MII_ANLPAR] |= 0x01e1; |
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} else { |
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s->regs[MII_BMSR] &= ~0x4; |
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s->regs[MII_ANLPAR] &= 0x01ff; |
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} |
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s->link_ok = link_ok; |
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} |
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static void mii_reset(Mii *s) |
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{ |
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memset(s->regs, 0, sizeof(s->regs)); |
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s->regs[MII_BMCR] = 0x1000; |
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s->regs[MII_BMSR] = 0x7848; /* no ext regs */ |
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s->regs[MII_PHYIDR1] = 0x2000; |
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s->regs[MII_PHYIDR2] = 0x5c90; |
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s->regs[MII_ANAR] = 0x01e1; |
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mii_set_link(s, s->link_ok); |
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} |
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static void mii_ro(Mii *s, uint16_t v) |
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{ |
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} |
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static void mii_write_bmcr(Mii *s, uint16_t v) |
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{ |
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if (v & 0x8000) { |
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mii_reset(s); |
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} else { |
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s->regs[MII_BMCR] = v; |
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} |
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} |
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static void mii_write_host(Mii *s, unsigned idx, uint16_t v) |
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{ |
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static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = { |
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[MII_BMCR] = mii_write_bmcr, |
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[MII_BMSR] = mii_ro, |
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[MII_PHYIDR1] = mii_ro, |
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[MII_PHYIDR2] = mii_ro, |
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}; |
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if (idx < MII_REG_MAX) { |
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trace_open_eth_mii_write(idx, v); |
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if (reg_write[idx]) { |
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reg_write[idx](s, v); |
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} else { |
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s->regs[idx] = v; |
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} |
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} |
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} |
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static uint16_t mii_read_host(Mii *s, unsigned idx) |
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{ |
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trace_open_eth_mii_read(idx, s->regs[idx]); |
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return s->regs[idx]; |
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} |
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/* OpenCores Ethernet registers */ |
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enum { |
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MODER, |
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INT_SOURCE, |
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INT_MASK, |
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IPGT, |
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IPGR1, |
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IPGR2, |
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PACKETLEN, |
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COLLCONF, |
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TX_BD_NUM, |
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CTRLMODER, |
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MIIMODER, |
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MIICOMMAND, |
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MIIADDRESS, |
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MIITX_DATA, |
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MIIRX_DATA, |
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MIISTATUS, |
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MAC_ADDR0, |
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MAC_ADDR1, |
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HASH0, |
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HASH1, |
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TXCTRL, |
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REG_MAX, |
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}; |
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enum { |
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MODER_RECSMALL = 0x10000, |
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MODER_PAD = 0x8000, |
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MODER_HUGEN = 0x4000, |
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MODER_RST = 0x800, |
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MODER_LOOPBCK = 0x80, |
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MODER_PRO = 0x20, |
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MODER_IAM = 0x10, |
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MODER_BRO = 0x8, |
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MODER_TXEN = 0x2, |
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MODER_RXEN = 0x1, |
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}; |
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enum { |
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INT_SOURCE_RXB = 0x4, |
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INT_SOURCE_TXB = 0x1, |
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}; |
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enum { |
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PACKETLEN_MINFL = 0xffff0000, |
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PACKETLEN_MINFL_LBN = 16, |
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PACKETLEN_MAXFL = 0xffff, |
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PACKETLEN_MAXFL_LBN = 0, |
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}; |
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enum { |
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MIICOMMAND_WCTRLDATA = 0x4, |
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MIICOMMAND_RSTAT = 0x2, |
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MIICOMMAND_SCANSTAT = 0x1, |
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}; |
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enum { |
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MIIADDRESS_RGAD = 0x1f00, |
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MIIADDRESS_RGAD_LBN = 8, |
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MIIADDRESS_FIAD = 0x1f, |
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MIIADDRESS_FIAD_LBN = 0, |
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}; |
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enum { |
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MIITX_DATA_CTRLDATA = 0xffff, |
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MIITX_DATA_CTRLDATA_LBN = 0, |
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}; |
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enum { |
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MIIRX_DATA_PRSD = 0xffff, |
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MIIRX_DATA_PRSD_LBN = 0, |
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}; |
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enum { |
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MIISTATUS_LINKFAIL = 0x1, |
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MIISTATUS_LINKFAIL_LBN = 0, |
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}; |
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enum { |
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MAC_ADDR0_BYTE2 = 0xff000000, |
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MAC_ADDR0_BYTE2_LBN = 24, |
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MAC_ADDR0_BYTE3 = 0xff0000, |
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MAC_ADDR0_BYTE3_LBN = 16, |
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MAC_ADDR0_BYTE4 = 0xff00, |
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MAC_ADDR0_BYTE4_LBN = 8, |
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MAC_ADDR0_BYTE5 = 0xff, |
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MAC_ADDR0_BYTE5_LBN = 0, |
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}; |
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enum { |
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MAC_ADDR1_BYTE0 = 0xff00, |
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MAC_ADDR1_BYTE0_LBN = 8, |
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MAC_ADDR1_BYTE1 = 0xff, |
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MAC_ADDR1_BYTE1_LBN = 0, |
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}; |
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enum { |
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TXD_LEN = 0xffff0000, |
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TXD_LEN_LBN = 16, |
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TXD_RD = 0x8000, |
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TXD_IRQ = 0x4000, |
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TXD_WR = 0x2000, |
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TXD_PAD = 0x1000, |
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TXD_CRC = 0x800, |
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TXD_UR = 0x100, |
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TXD_RTRY = 0xf0, |
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TXD_RTRY_LBN = 4, |
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TXD_RL = 0x8, |
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TXD_LC = 0x4, |
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TXD_DF = 0x2, |
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TXD_CS = 0x1, |
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}; |
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enum { |
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RXD_LEN = 0xffff0000, |
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RXD_LEN_LBN = 16, |
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RXD_E = 0x8000, |
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RXD_IRQ = 0x4000, |
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RXD_WRAP = 0x2000, |
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RXD_CF = 0x100, |
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RXD_M = 0x80, |
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RXD_OR = 0x40, |
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RXD_IS = 0x20, |
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RXD_DN = 0x10, |
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RXD_TL = 0x8, |
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RXD_SF = 0x4, |
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RXD_CRC = 0x2, |
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RXD_LC = 0x1, |
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}; |
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typedef struct desc { |
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uint32_t len_flags; |
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uint32_t buf_ptr; |
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} desc; |
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#define DEFAULT_PHY 1 |
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typedef struct OpenEthState { |
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SysBusDevice dev; |
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NICState *nic; |
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NICConf conf; |
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MemoryRegion reg_io; |
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MemoryRegion desc_io; |
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qemu_irq irq; |
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Mii mii; |
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uint32_t regs[REG_MAX]; |
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unsigned tx_desc; |
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unsigned rx_desc; |
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desc desc[128]; |
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} OpenEthState; |
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static desc *rx_desc(OpenEthState *s) |
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{ |
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return s->desc + s->rx_desc; |
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} |
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static desc *tx_desc(OpenEthState *s) |
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{ |
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return s->desc + s->tx_desc; |
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} |
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static void open_eth_update_irq(OpenEthState *s, |
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uint32_t old, uint32_t new) |
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{ |
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if (!old != !new) { |
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trace_open_eth_update_irq(new); |
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qemu_set_irq(s->irq, new); |
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} |
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} |
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static void open_eth_int_source_write(OpenEthState *s, |
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uint32_t val) |
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{ |
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uint32_t old_val = s->regs[INT_SOURCE]; |
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s->regs[INT_SOURCE] = val; |
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open_eth_update_irq(s, old_val & s->regs[INT_MASK], |
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s->regs[INT_SOURCE] & s->regs[INT_MASK]); |
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} |
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static void open_eth_set_link_status(VLANClientState *nc) |
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{ |
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OpenEthState *s = DO_UPCAST(NICState, nc, nc)->opaque; |
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if (GET_REGBIT(s, MIICOMMAND, SCANSTAT)) { |
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SET_REGFIELD(s, MIISTATUS, LINKFAIL, nc->link_down); |
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} |
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mii_set_link(&s->mii, !nc->link_down); |
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} |
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static void open_eth_reset(void *opaque) |
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{ |
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OpenEthState *s = opaque; |
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memset(s->regs, 0, sizeof(s->regs)); |
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s->regs[MODER] = 0xa000; |
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s->regs[IPGT] = 0x12; |
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s->regs[IPGR1] = 0xc; |
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s->regs[IPGR2] = 0x12; |
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s->regs[PACKETLEN] = 0x400600; |
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s->regs[COLLCONF] = 0xf003f; |
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s->regs[TX_BD_NUM] = 0x40; |
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s->regs[MIIMODER] = 0x64; |
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s->tx_desc = 0; |
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s->rx_desc = 0x40; |
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mii_reset(&s->mii); |
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open_eth_set_link_status(&s->nic->nc); |
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} |
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static int open_eth_can_receive(VLANClientState *nc) |
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{ |
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OpenEthState *s = DO_UPCAST(NICState, nc, nc)->opaque; |
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return GET_REGBIT(s, MODER, RXEN) && |
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(s->regs[TX_BD_NUM] < 0x80) && |
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(rx_desc(s)->len_flags & RXD_E); |
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} |
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#define POLYNOMIAL 0x04c11db6 |
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/* From FreeBSD */ |
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/* XXX: optimize */ |
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static unsigned compute_mcast_idx(const uint8_t *ep) |
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{ |
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uint32_t crc; |
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int carry, i, j; |
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uint8_t b; |
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crc = 0xffffffff; |
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for (i = 0; i < 6; i++) { |
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b = *ep++; |
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for (j = 0; j < 8; j++) { |
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carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
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crc <<= 1; |
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b >>= 1; |
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if (carry) { |
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crc = ((crc ^ POLYNOMIAL) | carry); |
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} |
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} |
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} |
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return crc >> 26; |
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} |
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static ssize_t open_eth_receive(VLANClientState *nc, |
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const uint8_t *buf, size_t size) |
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{ |
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OpenEthState *s = DO_UPCAST(NICState, nc, nc)->opaque; |
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size_t maxfl = GET_REGFIELD(s, PACKETLEN, MAXFL); |
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size_t minfl = GET_REGFIELD(s, PACKETLEN, MINFL); |
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bool miss = true; |
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trace_open_eth_receive((unsigned)size); |
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if (size >= 6) { |
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static const uint8_t bcast_addr[] = { |
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff |
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}; |
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if (memcmp(buf, bcast_addr, sizeof(bcast_addr)) == 0) { |
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miss = GET_REGBIT(s, MODER, BRO); |
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} else if ((buf[0] & 0x1) || GET_REGBIT(s, MODER, IAM)) { |
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unsigned mcast_idx = compute_mcast_idx(buf); |
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miss = !(s->regs[HASH0 + mcast_idx / 32] & |
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(1 << (mcast_idx % 32))); |
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trace_open_eth_receive_mcast( |
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mcast_idx, s->regs[HASH0], s->regs[HASH1]); |
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} else { |
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miss = GET_REGFIELD(s, MAC_ADDR1, BYTE0) != buf[0] || |
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GET_REGFIELD(s, MAC_ADDR1, BYTE1) != buf[1] || |
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GET_REGFIELD(s, MAC_ADDR0, BYTE2) != buf[2] || |
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GET_REGFIELD(s, MAC_ADDR0, BYTE3) != buf[3] || |
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GET_REGFIELD(s, MAC_ADDR0, BYTE4) != buf[4] || |
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GET_REGFIELD(s, MAC_ADDR0, BYTE5) != buf[5]; |
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} |
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} |
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if (miss && !GET_REGBIT(s, MODER, PRO)) { |
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trace_open_eth_receive_reject(); |
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return size; |
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} |
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#ifdef USE_RECSMALL |
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if (GET_REGBIT(s, MODER, RECSMALL) || size >= minfl) { |
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#else |
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{ |
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#endif |
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desc *desc = rx_desc(s); |
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size_t copy_size = GET_REGBIT(s, MODER, HUGEN) ? 65536 : maxfl; |
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desc->len_flags &= ~(RXD_CF | RXD_M | RXD_OR | |
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RXD_IS | RXD_DN | RXD_TL | RXD_SF | RXD_CRC | RXD_LC); |
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if (copy_size > size) { |
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copy_size = size; |
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} |
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if (miss) { |
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desc->len_flags |= RXD_M; |
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} |
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if (size > maxfl) { |
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desc->len_flags |= RXD_TL; |
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} |
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#ifdef USE_RECSMALL |
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if (size < minfl) { |
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desc->len_flags |= RXD_SF; |
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} |
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#endif |
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cpu_physical_memory_write(desc->buf_ptr, buf, copy_size); |
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if (GET_REGBIT(s, MODER, PAD) && copy_size < minfl) { |
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static const uint8_t zero[65536] = {0}; |
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cpu_physical_memory_write(desc->buf_ptr + copy_size, |
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zero, minfl - copy_size); |
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copy_size = minfl; |
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} |
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SET_FIELD(desc->len_flags, RXD_LEN, copy_size); |
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if ((desc->len_flags & RXD_WRAP) || s->rx_desc == 0x7f) { |
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s->rx_desc = s->regs[TX_BD_NUM]; |
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} else { |
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++s->rx_desc; |
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} |
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desc->len_flags &= ~RXD_E; |
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trace_open_eth_receive_desc(desc->buf_ptr, desc->len_flags); |
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if (desc->len_flags & RXD_IRQ) { |
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open_eth_int_source_write(s, |
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s->regs[INT_SOURCE] | INT_SOURCE_RXB); |
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} |
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} |
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return size; |
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} |
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static void open_eth_cleanup(VLANClientState *nc) |
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{ |
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} |
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static NetClientInfo net_open_eth_info = { |
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.type = NET_CLIENT_TYPE_NIC, |
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.size = sizeof(NICState), |
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.can_receive = open_eth_can_receive, |
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.receive = open_eth_receive, |
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.cleanup = open_eth_cleanup, |
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.link_status_changed = open_eth_set_link_status, |
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}; |
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static void open_eth_start_xmit(OpenEthState *s, desc *tx) |
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{ |
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uint8_t buf[65536]; |
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unsigned len = GET_FIELD(tx->len_flags, TXD_LEN); |
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unsigned tx_len = len; |
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if ((tx->len_flags & TXD_PAD) && |
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tx_len < GET_REGFIELD(s, PACKETLEN, MINFL)) { |
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tx_len = GET_REGFIELD(s, PACKETLEN, MINFL); |
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} |
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if (!GET_REGBIT(s, MODER, HUGEN) && |
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tx_len > GET_REGFIELD(s, PACKETLEN, MAXFL)) { |
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tx_len = GET_REGFIELD(s, PACKETLEN, MAXFL); |
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} |
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trace_open_eth_start_xmit(tx->buf_ptr, len, tx_len); |
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if (len > tx_len) { |
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len = tx_len; |
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} |
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cpu_physical_memory_read(tx->buf_ptr, buf, len); |
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if (tx_len > len) { |
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memset(buf + len, 0, tx_len - len); |
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} |
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qemu_send_packet(&s->nic->nc, buf, tx_len); |
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if (tx->len_flags & TXD_WR) { |
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s->tx_desc = 0; |
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} else { |
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++s->tx_desc; |
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if (s->tx_desc >= s->regs[TX_BD_NUM]) { |
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s->tx_desc = 0; |
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} |
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} |
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tx->len_flags &= ~(TXD_RD | TXD_UR | |
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TXD_RTRY | TXD_RL | TXD_LC | TXD_DF | TXD_CS); |
|||
if (tx->len_flags & TXD_IRQ) { |
|||
open_eth_int_source_write(s, s->regs[INT_SOURCE] | INT_SOURCE_TXB); |
|||
} |
|||
|
|||
} |
|||
|
|||
static void open_eth_check_start_xmit(OpenEthState *s) |
|||
{ |
|||
desc *tx = tx_desc(s); |
|||
if (GET_REGBIT(s, MODER, TXEN) && s->regs[TX_BD_NUM] > 0 && |
|||
(tx->len_flags & TXD_RD) && |
|||
GET_FIELD(tx->len_flags, TXD_LEN) > 4) { |
|||
open_eth_start_xmit(s, tx); |
|||
} |
|||
} |
|||
|
|||
static uint64_t open_eth_reg_read(void *opaque, |
|||
target_phys_addr_t addr, unsigned int size) |
|||
{ |
|||
static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = { |
|||
}; |
|||
OpenEthState *s = opaque; |
|||
unsigned idx = addr / 4; |
|||
uint64_t v = 0; |
|||
|
|||
if (idx < REG_MAX) { |
|||
if (reg_read[idx]) { |
|||
v = reg_read[idx](s); |
|||
} else { |
|||
v = s->regs[idx]; |
|||
} |
|||
} |
|||
trace_open_eth_reg_read((uint32_t)addr, (uint32_t)v); |
|||
return v; |
|||
} |
|||
|
|||
static void open_eth_ro(OpenEthState *s, uint32_t val) |
|||
{ |
|||
} |
|||
|
|||
static void open_eth_moder_host_write(OpenEthState *s, uint32_t val) |
|||
{ |
|||
uint32_t set = val & ~s->regs[MODER]; |
|||
|
|||
if (set & MODER_RST) { |
|||
open_eth_reset(s); |
|||
} |
|||
|
|||
s->regs[MODER] = val; |
|||
|
|||
if (set & MODER_RXEN) { |
|||
s->rx_desc = s->regs[TX_BD_NUM]; |
|||
} |
|||
if (set & MODER_TXEN) { |
|||
s->tx_desc = 0; |
|||
open_eth_check_start_xmit(s); |
|||
} |
|||
} |
|||
|
|||
static void open_eth_int_source_host_write(OpenEthState *s, uint32_t val) |
|||
{ |
|||
uint32_t old = s->regs[INT_SOURCE]; |
|||
|
|||
s->regs[INT_SOURCE] &= ~val; |
|||
open_eth_update_irq(s, old & s->regs[INT_MASK], |
|||
s->regs[INT_SOURCE] & s->regs[INT_MASK]); |
|||
} |
|||
|
|||
static void open_eth_int_mask_host_write(OpenEthState *s, uint32_t val) |
|||
{ |
|||
uint32_t old = s->regs[INT_MASK]; |
|||
|
|||
s->regs[INT_MASK] = val; |
|||
open_eth_update_irq(s, s->regs[INT_SOURCE] & old, |
|||
s->regs[INT_SOURCE] & s->regs[INT_MASK]); |
|||
} |
|||
|
|||
static void open_eth_mii_command_host_write(OpenEthState *s, uint32_t val) |
|||
{ |
|||
unsigned fiad = GET_REGFIELD(s, MIIADDRESS, FIAD); |
|||
unsigned rgad = GET_REGFIELD(s, MIIADDRESS, RGAD); |
|||
|
|||
if (val & MIICOMMAND_WCTRLDATA) { |
|||
if (fiad == DEFAULT_PHY) { |
|||
mii_write_host(&s->mii, rgad, |
|||
GET_REGFIELD(s, MIITX_DATA, CTRLDATA)); |
|||
} |
|||
} |
|||
if (val & MIICOMMAND_RSTAT) { |
|||
if (fiad == DEFAULT_PHY) { |
|||
SET_REGFIELD(s, MIIRX_DATA, PRSD, |
|||
mii_read_host(&s->mii, rgad)); |
|||
} else { |
|||
s->regs[MIIRX_DATA] = 0xffff; |
|||
} |
|||
SET_REGFIELD(s, MIISTATUS, LINKFAIL, s->nic->nc.link_down); |
|||
} |
|||
} |
|||
|
|||
static void open_eth_mii_tx_host_write(OpenEthState *s, uint32_t val) |
|||
{ |
|||
SET_REGFIELD(s, MIITX_DATA, CTRLDATA, val); |
|||
if (GET_REGFIELD(s, MIIADDRESS, FIAD) == DEFAULT_PHY) { |
|||
mii_write_host(&s->mii, GET_REGFIELD(s, MIIADDRESS, RGAD), |
|||
GET_REGFIELD(s, MIITX_DATA, CTRLDATA)); |
|||
} |
|||
} |
|||
|
|||
static void open_eth_reg_write(void *opaque, |
|||
target_phys_addr_t addr, uint64_t val, unsigned int size) |
|||
{ |
|||
static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = { |
|||
[MODER] = open_eth_moder_host_write, |
|||
[INT_SOURCE] = open_eth_int_source_host_write, |
|||
[INT_MASK] = open_eth_int_mask_host_write, |
|||
[MIICOMMAND] = open_eth_mii_command_host_write, |
|||
[MIITX_DATA] = open_eth_mii_tx_host_write, |
|||
[MIISTATUS] = open_eth_ro, |
|||
}; |
|||
OpenEthState *s = opaque; |
|||
unsigned idx = addr / 4; |
|||
|
|||
if (idx < REG_MAX) { |
|||
trace_open_eth_reg_write((uint32_t)addr, (uint32_t)val); |
|||
if (reg_write[idx]) { |
|||
reg_write[idx](s, val); |
|||
} else { |
|||
s->regs[idx] = val; |
|||
} |
|||
} |
|||
} |
|||
|
|||
static uint64_t open_eth_desc_read(void *opaque, |
|||
target_phys_addr_t addr, unsigned int size) |
|||
{ |
|||
OpenEthState *s = opaque; |
|||
uint64_t v = 0; |
|||
|
|||
addr &= 0x3ff; |
|||
memcpy(&v, (uint8_t *)s->desc + addr, size); |
|||
trace_open_eth_desc_read((uint32_t)addr, (uint32_t)v); |
|||
return v; |
|||
} |
|||
|
|||
static void open_eth_desc_write(void *opaque, |
|||
target_phys_addr_t addr, uint64_t val, unsigned int size) |
|||
{ |
|||
OpenEthState *s = opaque; |
|||
|
|||
addr &= 0x3ff; |
|||
trace_open_eth_desc_write((uint32_t)addr, (uint32_t)val); |
|||
memcpy((uint8_t *)s->desc + addr, &val, size); |
|||
open_eth_check_start_xmit(s); |
|||
} |
|||
|
|||
|
|||
static MemoryRegionOps open_eth_reg_ops = { |
|||
.read = open_eth_reg_read, |
|||
.write = open_eth_reg_write, |
|||
}; |
|||
|
|||
static MemoryRegionOps open_eth_desc_ops = { |
|||
.read = open_eth_desc_read, |
|||
.write = open_eth_desc_write, |
|||
}; |
|||
|
|||
static int sysbus_open_eth_init(SysBusDevice *dev) |
|||
{ |
|||
OpenEthState *s = DO_UPCAST(OpenEthState, dev, dev); |
|||
|
|||
memory_region_init_io(&s->reg_io, &open_eth_reg_ops, s, |
|||
"open_eth.regs", 0x54); |
|||
sysbus_init_mmio_region(dev, &s->reg_io); |
|||
|
|||
memory_region_init_io(&s->desc_io, &open_eth_desc_ops, s, |
|||
"open_eth.desc", 0x400); |
|||
sysbus_init_mmio_region(dev, &s->desc_io); |
|||
|
|||
sysbus_init_irq(dev, &s->irq); |
|||
|
|||
s->nic = qemu_new_nic(&net_open_eth_info, &s->conf, |
|||
s->dev.qdev.info->name, s->dev.qdev.id, s); |
|||
return 0; |
|||
} |
|||
|
|||
static void qdev_open_eth_reset(DeviceState *dev) |
|||
{ |
|||
OpenEthState *d = DO_UPCAST(OpenEthState, dev.qdev, dev); |
|||
open_eth_reset(d); |
|||
} |
|||
|
|||
static SysBusDeviceInfo open_eth_info = { |
|||
.qdev.name = "open_eth", |
|||
.qdev.desc = "Opencores 10/100 Mbit Ethernet", |
|||
.qdev.size = sizeof(OpenEthState), |
|||
.qdev.reset = qdev_open_eth_reset, |
|||
.init = sysbus_open_eth_init, |
|||
.qdev.props = (Property[]) { |
|||
DEFINE_NIC_PROPERTIES(OpenEthState, conf), |
|||
DEFINE_PROP_END_OF_LIST(), |
|||
} |
|||
}; |
|||
|
|||
static void open_eth_register_devices(void) |
|||
{ |
|||
sysbus_register_withprop(&open_eth_info); |
|||
} |
|||
|
|||
device_init(open_eth_register_devices) |
|||
Loading…
Reference in new issue