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@ -23,6 +23,7 @@ MSR_IA32_VMX_TRUE_PROCBASED_CTLS = 0x48E |
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MSR_IA32_VMX_TRUE_EXIT_CTLS = 0x48F |
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MSR_IA32_VMX_TRUE_ENTRY_CTLS = 0x490 |
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MSR_IA32_VMX_VMFUNC = 0x491 |
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MSR_IA32_VMX_PROCBASED_CTLS3 = 0x492 |
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class msr(object): |
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def __init__(self): |
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@ -71,6 +72,13 @@ class Control(object): |
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s = 'yes' |
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print(' %-40s %s' % (self.bits[bit], s)) |
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# All 64 bits in the tertiary controls MSR are allowed-1 |
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class Allowed1Control(Control): |
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def read2(self, nr): |
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m = msr() |
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val = m.read(nr, 0) |
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return (0, val) |
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class Misc(object): |
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def __init__(self, name, bits, msr): |
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self.name = name |
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@ -135,6 +143,7 @@ controls = [ |
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12: 'RDTSC exiting', |
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15: 'CR3-load exiting', |
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16: 'CR3-store exiting', |
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17: 'Activate tertiary controls', |
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19: 'CR8-load exiting', |
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20: 'CR8-store exiting', |
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21: 'Use TPR shadow', |
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@ -186,6 +195,14 @@ controls = [ |
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cap_msr = MSR_IA32_VMX_PROCBASED_CTLS2, |
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), |
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Allowed1Control( |
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name = 'tertiary processor-based controls', |
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bits = { |
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4: 'Enable IPI virtualization' |
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}, |
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cap_msr = MSR_IA32_VMX_PROCBASED_CTLS3, |
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), |
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Control( |
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name = 'VM-Exit controls', |
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bits = { |
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