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@ -13,6 +13,7 @@ |
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#include "qemu/log.h" |
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#include "ui/pixel_ops.h" |
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#include "ui/console.h" |
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#include "ui/rect.h" |
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/*
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* NOTE: |
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@ -24,7 +25,7 @@ |
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* possible. |
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*/ |
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static int ati_bpp_from_datatype(ATIVGAState *s) |
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static int ati_bpp_from_datatype(const ATIVGAState *s) |
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{ |
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switch (s->regs.dp_datatype & 0xf) { |
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case 2: |
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@ -43,118 +44,182 @@ static int ati_bpp_from_datatype(ATIVGAState *s) |
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} |
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} |
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static void ati_set_dirty(ATIVGAState *s, |
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const uint8_t *dst_bits, unsigned dst_y) |
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typedef struct { |
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int bpp; |
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uint32_t rop3; |
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bool host_data_active; |
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bool left_to_right; |
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bool top_to_bottom; |
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uint32_t frgd_clr; |
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const uint8_t *palette; |
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const uint8_t *vram_end; |
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QemuRect scissor; |
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QemuRect dst; |
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int dst_stride; |
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uint8_t *dst_bits; |
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uint32_t dst_offset; |
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QemuRect src; |
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int src_stride; |
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const uint8_t *src_bits; |
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} ATI2DCtx; |
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static void ati_set_dirty(VGACommonState *vga, const ATI2DCtx *ctx) |
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{ |
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VGACommonState *vga = &s->vga; |
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DisplaySurface *ds = qemu_console_surface(vga->con); |
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DPRINTF("%p %u ds: %p %d %d rop: %x\n", vga->vram_ptr, vga->vbe_start_addr, |
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surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), |
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(s->regs.dp_mix & GMC_ROP3_MASK) >> 16); |
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if (dst_bits >= vga->vram_ptr + vga->vbe_start_addr && |
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dst_bits < vga->vram_ptr + vga->vbe_start_addr + |
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vga->vbe_regs[VBE_DISPI_INDEX_YRES] * vga->vbe_line_offset) { |
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ctx->rop3 >> 16); |
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if (ctx->dst_bits >= vga->vram_ptr + vga->vbe_start_addr && |
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ctx->dst_bits < vga->vram_ptr + vga->vbe_start_addr + |
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vga->vbe_regs[VBE_DISPI_INDEX_YRES] * vga->vbe_line_offset) { |
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memory_region_set_dirty(&vga->vram, |
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vga->vbe_start_addr + s->regs.dst_offset |
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+ dst_y * surface_stride(ds), |
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s->regs.dst_height * surface_stride(ds)); |
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vga->vbe_start_addr + ctx->dst_offset + |
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ctx->dst.y * surface_stride(ds), |
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ctx->dst.height * surface_stride(ds)); |
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} |
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} |
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void ati_2d_blt(ATIVGAState *s) |
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static void setup_2d_blt_ctx(const ATIVGAState *s, ATI2DCtx *ctx) |
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{ |
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/* FIXME it is probably more complex than this and may need to be */ |
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/* rewritten but for now as a start just to get some output: */ |
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unsigned dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? |
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s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width); |
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unsigned dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? |
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s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height); |
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int bpp = ati_bpp_from_datatype(s); |
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if (!bpp) { |
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); |
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return; |
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} |
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int dst_stride = s->regs.dst_pitch; |
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if (!dst_stride) { |
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qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); |
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return; |
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} |
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uint8_t *dst_bits = s->vga.vram_ptr + s->regs.dst_offset; |
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ctx->bpp = ati_bpp_from_datatype(s); |
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ctx->rop3 = s->regs.dp_mix & GMC_ROP3_MASK; |
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ctx->host_data_active = s->host_data.active; |
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ctx->left_to_right = s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT; |
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ctx->top_to_bottom = s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM; |
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ctx->frgd_clr = s->regs.dp_brush_frgd_clr; |
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ctx->palette = s->vga.palette; |
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ctx->dst_offset = s->regs.dst_offset; |
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ctx->vram_end = s->vga.vram_ptr + s->vga.vram_size; |
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ctx->scissor.width = s->regs.sc_right - s->regs.sc_left + 1; |
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ctx->scissor.height = s->regs.sc_bottom - s->regs.sc_top + 1; |
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ctx->scissor.x = s->regs.sc_left; |
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ctx->scissor.y = s->regs.sc_top; |
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ctx->dst.width = s->regs.dst_width; |
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ctx->dst.height = s->regs.dst_height; |
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ctx->dst.x = (ctx->left_to_right ? |
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s->regs.dst_x : s->regs.dst_x + 1 - ctx->dst.width); |
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ctx->dst.y = (ctx->top_to_bottom ? |
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s->regs.dst_y : s->regs.dst_y + 1 - ctx->dst.height); |
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ctx->dst_stride = s->regs.dst_pitch; |
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ctx->dst_bits = s->vga.vram_ptr + s->regs.dst_offset; |
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if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { |
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dst_bits += s->regs.crtc_offset & 0x07ffffff; |
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dst_stride *= bpp; |
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ctx->dst_bits += s->regs.crtc_offset & 0x07ffffff; |
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ctx->dst_stride *= ctx->bpp; |
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} |
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uint8_t *end = s->vga.vram_ptr + s->vga.vram_size; |
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if (dst_x > 0x3fff || dst_y > 0x3fff || dst_bits >= end |
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|| dst_bits + dst_x |
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+ (dst_y + s->regs.dst_height) * dst_stride >= end) { |
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qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); |
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return; |
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ctx->src.x = (ctx->left_to_right ? |
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s->regs.src_x : s->regs.src_x + 1 - ctx->dst.width); |
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ctx->src.y = (ctx->top_to_bottom ? |
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s->regs.src_y : s->regs.src_y + 1 - ctx->dst.height); |
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ctx->src_stride = s->regs.src_pitch; |
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ctx->src_bits = s->vga.vram_ptr + s->regs.src_offset; |
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if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { |
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ctx->src_bits += s->regs.crtc_offset & 0x07ffffff; |
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ctx->src_stride *= ctx->bpp; |
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} |
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DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", |
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s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, |
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s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, |
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s->regs.src_x, s->regs.src_y, dst_x, dst_y, |
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s->regs.dst_width, s->regs.dst_height, |
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(s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'), |
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(s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^')); |
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switch (s->regs.dp_mix & GMC_ROP3_MASK) { |
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ctx->src_stride, ctx->dst_stride, s->regs.default_pitch, |
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ctx->src.x, ctx->src.y, ctx->dst.x, ctx->dst.y, |
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ctx->dst.width, ctx->dst.height, |
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(ctx->left_to_right ? '>' : '<'), |
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(ctx->top_to_bottom ? 'v' : '^')); |
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} |
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static bool ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_pixman) |
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{ |
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QemuRect vis_src, vis_dst; |
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if (!ctx->bpp) { |
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); |
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return false; |
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} |
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if (!ctx->dst_stride) { |
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qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); |
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return false; |
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} |
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if (ctx->dst.x > 0x3fff || ctx->dst.y > 0x3fff || |
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ctx->dst_bits >= ctx->vram_end || ctx->dst_bits + ctx->dst.x + |
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(ctx->dst.y + ctx->dst.height) * ctx->dst_stride >= ctx->vram_end) { |
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qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); |
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return false; |
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} |
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qemu_rect_intersect(&ctx->dst, &ctx->scissor, &vis_dst); |
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if (!vis_dst.height || !vis_dst.width) { |
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/* Nothing is visible, completely clipped */ |
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return false; |
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} |
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/*
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* The src must be offset if clipping is applied to the dst. |
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* This is so that when the source is blit to a dst clipped |
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* on the top or left the src image is not shifted into the |
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* clipped region but actually clipped. |
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*/ |
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vis_src.x = ctx->src.x + (vis_dst.x - ctx->dst.x); |
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vis_src.y = ctx->src.y + (vis_dst.y - ctx->dst.y); |
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vis_src.width = vis_dst.width; |
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vis_src.height = vis_dst.height; |
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DPRINTF("dst: (%d,%d) %dx%d -> vis_dst: (%d,%d) %dx%d\n", |
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ctx->dst.x, ctx->dst.y, ctx->dst.width, ctx->dst.height, |
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vis_dst.x, vis_dst.y, vis_dst.width, vis_dst.height); |
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DPRINTF("src: (%d,%d) %dx%d -> vis_src: (%d,%d) %dx%d\n", |
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ctx->src.x, ctx->src.y, ctx->dst.width, ctx->dst.height, |
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vis_src.x, vis_src.y, vis_src.width, vis_src.height); |
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switch (ctx->rop3) { |
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case ROP3_SRCCOPY: |
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{ |
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bool fallback = false; |
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unsigned src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? |
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s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width); |
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unsigned src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? |
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s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height); |
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int src_stride = s->regs.src_pitch; |
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if (!src_stride) { |
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if (!ctx->src_stride) { |
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qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); |
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return; |
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} |
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uint8_t *src_bits = s->vga.vram_ptr + s->regs.src_offset; |
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if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { |
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src_bits += s->regs.crtc_offset & 0x07ffffff; |
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src_stride *= bpp; |
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return false; |
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} |
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if (src_x > 0x3fff || src_y > 0x3fff || src_bits >= end |
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|| src_bits + src_x |
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+ (src_y + s->regs.dst_height) * src_stride >= end) { |
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if (!ctx->host_data_active && |
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(vis_src.x > 0x3fff || vis_src.y > 0x3fff || |
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ctx->src_bits >= ctx->vram_end || ctx->src_bits + vis_src.x + |
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(vis_src.y + vis_dst.height) * ctx->src_stride >= ctx->vram_end)) { |
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qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); |
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return; |
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return false; |
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} |
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src_stride /= sizeof(uint32_t); |
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dst_stride /= sizeof(uint32_t); |
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DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n", |
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src_bits, dst_bits, src_stride, dst_stride, bpp, bpp, |
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src_x, src_y, dst_x, dst_y, |
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s->regs.dst_width, s->regs.dst_height); |
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DPRINTF("pixman_blt(%p, %p, %ld, %ld, %d, %d, %d, %d, %d, %d, %d, %d)\n", |
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ctx->src_bits, ctx->dst_bits, |
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ctx->src_stride / sizeof(uint32_t), |
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ctx->dst_stride / sizeof(uint32_t), |
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ctx->bpp, ctx->bpp, vis_src.x, vis_src.y, vis_dst.x, vis_dst.y, |
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vis_dst.width, vis_dst.height); |
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#ifdef CONFIG_PIXMAN |
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if ((s->use_pixman & BIT(1)) && |
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s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT && |
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s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { |
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fallback = !pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits, |
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src_stride, dst_stride, bpp, bpp, |
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src_x, src_y, dst_x, dst_y, |
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s->regs.dst_width, s->regs.dst_height); |
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} else if (s->use_pixman & BIT(1)) { |
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int src_stride_words = ctx->src_stride / sizeof(uint32_t); |
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int dst_stride_words = ctx->dst_stride / sizeof(uint32_t); |
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if ((use_pixman & BIT(1)) && |
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ctx->left_to_right && ctx->top_to_bottom) { |
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fallback = !pixman_blt((uint32_t *)ctx->src_bits, |
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(uint32_t *)ctx->dst_bits, src_stride_words, |
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dst_stride_words, ctx->bpp, ctx->bpp, |
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vis_src.x, vis_src.y, vis_dst.x, vis_dst.y, |
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vis_dst.width, vis_dst.height); |
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} else if (use_pixman & BIT(1)) { |
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/* FIXME: We only really need a temporary if src and dst overlap */ |
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int llb = s->regs.dst_width * (bpp / 8); |
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int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t)); |
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uint32_t *tmp = g_malloc(tmp_stride * sizeof(uint32_t) * |
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s->regs.dst_height); |
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fallback = !pixman_blt((uint32_t *)src_bits, tmp, |
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src_stride, tmp_stride, bpp, bpp, |
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src_x, src_y, 0, 0, |
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s->regs.dst_width, s->regs.dst_height); |
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int llb = vis_dst.width * (ctx->bpp / 8); |
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int tmp_stride_words = DIV_ROUND_UP(llb, sizeof(uint32_t)); |
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uint32_t *tmp = g_malloc(tmp_stride_words * sizeof(uint32_t) * |
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vis_dst.height); |
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fallback = !pixman_blt((uint32_t *)ctx->src_bits, tmp, |
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src_stride_words, tmp_stride_words, ctx->bpp, |
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ctx->bpp, vis_src.x, vis_src.y, 0, 0, |
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vis_dst.width, vis_dst.height); |
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if (!fallback) { |
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fallback = !pixman_blt(tmp, (uint32_t *)dst_bits, |
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tmp_stride, dst_stride, bpp, bpp, |
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0, 0, dst_x, dst_y, |
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s->regs.dst_width, s->regs.dst_height); |
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fallback = !pixman_blt(tmp, (uint32_t *)ctx->dst_bits, |
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tmp_stride_words, dst_stride_words, |
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ctx->bpp, ctx->bpp, 0, 0, |
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vis_dst.x, vis_dst.y, |
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vis_dst.width, vis_dst.height); |
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} |
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g_free(tmp); |
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} else |
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@ -163,21 +228,21 @@ void ati_2d_blt(ATIVGAState *s) |
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fallback = true; |
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} |
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if (fallback) { |
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unsigned int y, i, j, bypp = bpp / 8; |
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unsigned int src_pitch = src_stride * sizeof(uint32_t); |
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unsigned int dst_pitch = dst_stride * sizeof(uint32_t); |
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for (y = 0; y < s->regs.dst_height; y++) { |
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i = dst_x * bypp; |
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j = src_x * bypp; |
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if (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { |
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i += (dst_y + y) * dst_pitch; |
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j += (src_y + y) * src_pitch; |
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unsigned int y, i, j, bypp = ctx->bpp / 8; |
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for (y = 0; y < vis_dst.height; y++) { |
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i = vis_dst.x * bypp; |
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j = vis_src.x * bypp; |
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if (ctx->top_to_bottom) { |
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i += (vis_dst.y + y) * ctx->dst_stride; |
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j += (vis_src.y + y) * ctx->src_stride; |
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} else { |
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i += (dst_y + s->regs.dst_height - 1 - y) * dst_pitch; |
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j += (src_y + s->regs.dst_height - 1 - y) * src_pitch; |
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i += (vis_dst.y + vis_dst.height - 1 - y) |
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* ctx->dst_stride; |
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j += (vis_src.y + vis_dst.height - 1 - y) |
|
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* ctx->src_stride; |
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|
} |
|
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|
memmove(&dst_bits[i], &src_bits[j], s->regs.dst_width * bypp); |
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|
memmove(&ctx->dst_bits[i], &ctx->src_bits[j], |
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|
vis_dst.width * bypp); |
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} |
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} |
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break; |
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|
@ -188,37 +253,39 @@ void ati_2d_blt(ATIVGAState *s) |
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{ |
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uint32_t filler = 0; |
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|
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switch (s->regs.dp_mix & GMC_ROP3_MASK) { |
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switch (ctx->rop3) { |
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case ROP3_PATCOPY: |
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filler = s->regs.dp_brush_frgd_clr; |
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filler = ctx->frgd_clr; |
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break; |
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case ROP3_BLACKNESS: |
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filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0], |
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s->vga.palette[1], s->vga.palette[2]); |
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filler = 0xffUL << 24 | rgb_to_pixel32(ctx->palette[0], |
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ctx->palette[1], |
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ctx->palette[2]); |
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break; |
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case ROP3_WHITENESS: |
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filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3], |
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s->vga.palette[4], s->vga.palette[5]); |
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filler = 0xffUL << 24 | rgb_to_pixel32(ctx->palette[3], |
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ctx->palette[4], |
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ctx->palette[5]); |
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break; |
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} |
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dst_stride /= sizeof(uint32_t); |
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DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", |
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dst_bits, dst_stride, bpp, dst_x, dst_y, |
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s->regs.dst_width, s->regs.dst_height, filler); |
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DPRINTF("pixman_fill(%p, %ld, %d, %d, %d, %d, %d, %x)\n", |
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ctx->dst_bits, ctx->dst_stride / sizeof(uint32_t), ctx->bpp, |
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vis_dst.x, vis_dst.y, vis_dst.width, vis_dst.height, filler); |
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#ifdef CONFIG_PIXMAN |
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if (!(s->use_pixman & BIT(0)) || |
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!pixman_fill((uint32_t *)dst_bits, dst_stride, bpp, dst_x, dst_y, |
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s->regs.dst_width, s->regs.dst_height, filler)) |
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if (!(use_pixman & BIT(0)) || |
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!pixman_fill((uint32_t *)ctx->dst_bits, |
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ctx->dst_stride / sizeof(uint32_t), ctx->bpp, |
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vis_dst.x, vis_dst.y, vis_dst.width, vis_dst.height, |
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filler)) |
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#endif |
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{ |
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/* fallback when pixman failed or we don't want to call it */ |
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unsigned int x, y, i, bypp = bpp / 8; |
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unsigned int dst_pitch = dst_stride * sizeof(uint32_t); |
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for (y = 0; y < s->regs.dst_height; y++) { |
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i = dst_x * bypp + (dst_y + y) * dst_pitch; |
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for (x = 0; x < s->regs.dst_width; x++, i += bypp) { |
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stn_he_p(&dst_bits[i], bypp, filler); |
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unsigned int x, y, i, bypp = ctx->bpp / 8; |
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for (y = 0; y < vis_dst.height; y++) { |
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|
i = vis_dst.x * bypp + (vis_dst.y + y) * ctx->dst_stride; |
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|
|
for (x = 0; x < vis_dst.width; x++, i += bypp) { |
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|
|
stn_he_p(&ctx->dst_bits[i], bypp, filler); |
|
|
|
} |
|
|
|
} |
|
|
|
} |
|
|
|
@ -226,9 +293,143 @@ void ati_2d_blt(ATIVGAState *s) |
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|
} |
|
|
|
default: |
|
|
|
qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n", |
|
|
|
(s->regs.dp_mix & GMC_ROP3_MASK) >> 16); |
|
|
|
ctx->rop3 >> 16); |
|
|
|
return false; |
|
|
|
} |
|
|
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|
|
|
|
return true; |
|
|
|
} |
|
|
|
|
|
|
|
void ati_2d_blt(ATIVGAState *s) |
|
|
|
{ |
|
|
|
ATI2DCtx ctx; |
|
|
|
uint32_t src_source = s->regs.dp_mix & DP_SRC_SOURCE; |
|
|
|
|
|
|
|
/* Finish any active HOST_DATA blits before starting a new blit */ |
|
|
|
ati_host_data_finish(s); |
|
|
|
|
|
|
|
if (src_source == DP_SRC_HOST || src_source == DP_SRC_HOST_BYTEALIGN) { |
|
|
|
/* Begin a HOST_DATA blit */ |
|
|
|
s->host_data.active = true; |
|
|
|
s->host_data.next = 0; |
|
|
|
s->host_data.col = 0; |
|
|
|
s->host_data.row = 0; |
|
|
|
return; |
|
|
|
} |
|
|
|
setup_2d_blt_ctx(s, &ctx); |
|
|
|
if (ati_2d_do_blt(&ctx, s->use_pixman)) { |
|
|
|
ati_set_dirty(&s->vga, &ctx); |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
bool ati_host_data_flush(ATIVGAState *s) |
|
|
|
{ |
|
|
|
ATI2DCtx ctx, chunk; |
|
|
|
uint32_t fg = s->regs.dp_src_frgd_clr; |
|
|
|
uint32_t bg = s->regs.dp_src_bkgd_clr; |
|
|
|
unsigned bypp, pix_count, row, col, idx; |
|
|
|
uint8_t pix_buf[ATI_HOST_DATA_ACC_BITS * sizeof(uint32_t)]; |
|
|
|
uint32_t byte_pix_order = s->regs.dp_datatype & DP_BYTE_PIX_ORDER; |
|
|
|
uint32_t src_source = s->regs.dp_mix & DP_SRC_SOURCE; |
|
|
|
uint32_t src_datatype = s->regs.dp_datatype & DP_SRC_DATATYPE; |
|
|
|
|
|
|
|
if (!s->host_data.active) { |
|
|
|
return false; |
|
|
|
} |
|
|
|
if (src_source != DP_SRC_HOST) { |
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, |
|
|
|
"host_data_blt: unsupported src_source %x\n", src_source); |
|
|
|
return false; |
|
|
|
} |
|
|
|
if (src_datatype != SRC_MONO_FRGD_BKGD && src_datatype != SRC_MONO_FRGD && |
|
|
|
src_datatype != SRC_COLOR) { |
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, |
|
|
|
"host_data_blt: undefined src_datatype %x\n", |
|
|
|
src_datatype); |
|
|
|
return false; |
|
|
|
} |
|
|
|
|
|
|
|
setup_2d_blt_ctx(s, &ctx); |
|
|
|
|
|
|
|
if (!ctx.left_to_right || !ctx.top_to_bottom) { |
|
|
|
qemu_log_mask(LOG_UNIMP, |
|
|
|
"host_data_blt: unsupported blit direction %c%c\n", |
|
|
|
ctx.left_to_right ? '>' : '<', |
|
|
|
ctx.top_to_bottom ? 'v' : '^'); |
|
|
|
return false; |
|
|
|
} |
|
|
|
|
|
|
|
bypp = ctx.bpp / 8; |
|
|
|
|
|
|
|
ati_set_dirty(s, dst_bits, dst_y); |
|
|
|
if (src_datatype == SRC_COLOR) { |
|
|
|
pix_count = ATI_HOST_DATA_ACC_BITS / ctx.bpp; |
|
|
|
memcpy(pix_buf, &s->host_data.acc[0], sizeof(s->host_data.acc)); |
|
|
|
} else { |
|
|
|
pix_count = ATI_HOST_DATA_ACC_BITS; |
|
|
|
/* Expand monochrome bits to color pixels */ |
|
|
|
idx = 0; |
|
|
|
for (int word = 0; word < 4; word++) { |
|
|
|
for (int byte = 0; byte < 4; byte++) { |
|
|
|
uint8_t byte_val = s->host_data.acc[word] >> (byte * 8); |
|
|
|
for (int i = 0; i < 8; i++) { |
|
|
|
bool is_fg = byte_val & BIT(byte_pix_order ? i : 7 - i); |
|
|
|
uint32_t color = is_fg ? fg : bg; |
|
|
|
stn_he_p(&pix_buf[idx], bypp, color); |
|
|
|
idx += bypp; |
|
|
|
} |
|
|
|
} |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
/* Copy and then modify blit ctx for use in a chunked blit */ |
|
|
|
chunk = ctx; |
|
|
|
chunk.src_bits = pix_buf; |
|
|
|
chunk.src.y = 0; |
|
|
|
chunk.src_stride = ATI_HOST_DATA_ACC_BITS * bypp; |
|
|
|
|
|
|
|
/* Blit one scanline chunk at a time */ |
|
|
|
row = s->host_data.row; |
|
|
|
col = s->host_data.col; |
|
|
|
idx = 0; |
|
|
|
DPRINTF("blt %dpx @ row: %d, col: %d\n", pix_count, row, col); |
|
|
|
while (idx < pix_count && row < ctx.dst.height) { |
|
|
|
unsigned pix_in_scanline = MIN(pix_count - idx, |
|
|
|
ctx.dst.width - col); |
|
|
|
chunk.src.x = idx; |
|
|
|
/* Build a rect for this scanline chunk */ |
|
|
|
chunk.dst.x = ctx.dst.x + col; |
|
|
|
chunk.dst.y = ctx.dst.y + row; |
|
|
|
chunk.dst.width = pix_in_scanline; |
|
|
|
chunk.dst.height = 1; |
|
|
|
DPRINTF("blt %dpx span @ row: %d, col: %d to dst (%d,%d)\n", |
|
|
|
pix_in_scanline, row, col, chunk.dst.x, chunk.dst.y); |
|
|
|
if (ati_2d_do_blt(&chunk, s->use_pixman)) { |
|
|
|
ati_set_dirty(&s->vga, &chunk); |
|
|
|
} |
|
|
|
idx += pix_in_scanline; |
|
|
|
col += pix_in_scanline; |
|
|
|
if (col >= ctx.dst.width) { |
|
|
|
col = 0; |
|
|
|
row += 1; |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
/* Track state of the overall blit for use by the next flush */ |
|
|
|
s->host_data.next = 0; |
|
|
|
s->host_data.row = row; |
|
|
|
s->host_data.col = col; |
|
|
|
if (s->host_data.row >= ctx.dst.height) { |
|
|
|
s->host_data.active = false; |
|
|
|
} |
|
|
|
|
|
|
|
return s->host_data.active; |
|
|
|
} |
|
|
|
|
|
|
|
void ati_host_data_finish(ATIVGAState *s) |
|
|
|
{ |
|
|
|
if (ati_host_data_flush(s)) { |
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, |
|
|
|
"HOST_DATA blit ended before all data was written\n"); |
|
|
|
} |
|
|
|
s->host_data.active = false; |
|
|
|
} |
|
|
|
|
Peter Maydell
3 weeks ago