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meson: Drop host_arch rename for riscv64

This requires renaming several directories:
tcg/riscv, linux-user/include/host/riscv, and
common-user/host/riscv.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
pull/316/head
Richard Henderson 3 months ago
parent
commit
264ae24c36
  1. 2
      MAINTAINERS
  2. 0
      common-user/host/riscv64/safe-syscall.inc.S
  3. 4
      configure
  4. 0
      host/include/riscv64/host/cpuinfo.h
  5. 0
      linux-user/include/host/riscv64/host-signal.h
  6. 2
      meson.build
  7. 0
      tcg/riscv64/tcg-target-con-set.h
  8. 0
      tcg/riscv64/tcg-target-con-str.h
  9. 0
      tcg/riscv64/tcg-target-has.h
  10. 0
      tcg/riscv64/tcg-target-mo.h
  11. 0
      tcg/riscv64/tcg-target-opc.h.inc
  12. 0
      tcg/riscv64/tcg-target-reg-bits.h
  13. 0
      tcg/riscv64/tcg-target.c.inc
  14. 0
      tcg/riscv64/tcg-target.h

2
MAINTAINERS

@ -4086,7 +4086,7 @@ M: Palmer Dabbelt <palmer@dabbelt.com>
M: Alistair Francis <Alistair.Francis@wdc.com>
L: qemu-riscv@nongnu.org
S: Maintained
F: tcg/riscv/
F: tcg/riscv64/
F: disas/riscv.[ch]
S390 TCG target

0
common-user/host/riscv/safe-syscall.inc.S → common-user/host/riscv64/safe-syscall.inc.S

4
configure

@ -469,8 +469,8 @@ case "$cpu" in
CPU_CFLAGS="-m64 -mlittle-endian"
;;
riscv32 | riscv64)
host_arch=riscv
riscv64)
host_arch=riscv64
linux_arch=riscv
;;

0
host/include/riscv/host/cpuinfo.h → host/include/riscv64/host/cpuinfo.h

0
linux-user/include/host/riscv/host-signal.h → linux-user/include/host/riscv64/host-signal.h

2
meson.build

@ -265,8 +265,6 @@ enable_modules = get_option('modules') \
if cpu not in supported_cpus
host_arch = 'unknown'
elif cpu in ['riscv32', 'riscv64']
host_arch = 'riscv'
else
host_arch = cpu
endif

0
tcg/riscv/tcg-target-con-set.h → tcg/riscv64/tcg-target-con-set.h

0
tcg/riscv/tcg-target-con-str.h → tcg/riscv64/tcg-target-con-str.h

0
tcg/riscv/tcg-target-has.h → tcg/riscv64/tcg-target-has.h

0
tcg/riscv/tcg-target-mo.h → tcg/riscv64/tcg-target-mo.h

0
tcg/riscv/tcg-target-opc.h.inc → tcg/riscv64/tcg-target-opc.h.inc

0
tcg/riscv/tcg-target-reg-bits.h → tcg/riscv64/tcg-target-reg-bits.h

0
tcg/riscv/tcg-target.c.inc → tcg/riscv64/tcg-target.c.inc

0
tcg/riscv/tcg-target.h → tcg/riscv64/tcg-target.h

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