From 2211bb484c9d11c8fc0504dd05d0fdc0b4969218 Mon Sep 17 00:00:00 2001 From: Caleb Schlossin Date: Tue, 10 Feb 2026 07:46:45 -0600 Subject: [PATCH] ppc/pnv: Support for SECURITY_SWITCH XSCOM register access Power Hypervisor code requires access to the SECURITY_SWITCH XSCOM register at MMIO address 0x80028 (scom address 0x10005). Adding basic read support for now so that is doesn't cause error messages to be posted. Reviewed-by: Chalapathi V Reviewed-by: Glenn Miles Reviewed-by: Aditya Gupta Signed-off-by: Glenn Miles Signed-off-by: Caleb Schlossin Link: https://lore.kernel.org/qemu-devel/20260210134647.2050821-2-calebs@linux.ibm.com Signed-off-by: Harsh Prateek Bora --- hw/ppc/pnv_xscom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 8557b560ae..dc1ffc6c01 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -61,6 +61,8 @@ static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) { switch (pcba) { + case 0x10005: /* SECURITY SWITCH */ + return 0; case 0xf000f: return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id; case 0x18002: /* ECID2 */