Browse Source
These machines have been marked as deprecated two releases ago, and so far nobody complained that they are still useful, so it's time to remove these now. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260226090704.27699-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
Thomas Huth
5 months ago
committed by
Peter Maydell
Peter Maydell
9 changed files with 7 additions and 458 deletions
@ -1,19 +0,0 @@ |
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Calxeda Highbank and Midway (``highbank``, ``midway``) |
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====================================================== |
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|
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``highbank`` is a model of the Calxeda Highbank (ECX-1000) system, |
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which has four Cortex-A9 cores. |
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|
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``midway`` is a model of the Calxeda Midway (ECX-2000) system, |
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which has four Cortex-A15 cores. |
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|
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Emulated devices: |
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|
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- L2x0 cache controller |
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- SP804 dual timer |
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- PL011 UART |
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- PL061 GPIOs |
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- PL031 RTC |
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- PL022 synchronous serial port controller |
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- AHCI |
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- XGMAC ethernet controllers |
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@ -1,404 +0,0 @@ |
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/*
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* Calxeda Highbank SoC emulation |
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* |
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* Copyright (c) 2010-2012 Calxeda |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms and conditions of the GNU General Public License, |
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* version 2 or later, as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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* more details. |
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* |
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* You should have received a copy of the GNU General Public License along with |
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* this program. If not, see <http://www.gnu.org/licenses/>.
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* |
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*/ |
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|
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#include "qemu/osdep.h" |
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#include "qemu/datadir.h" |
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#include "qapi/error.h" |
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#include "hw/core/sysbus.h" |
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#include "migration/vmstate.h" |
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#include "hw/arm/boot.h" |
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#include "hw/arm/machines-qom.h" |
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#include "hw/core/loader.h" |
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#include "net/net.h" |
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#include "system/runstate.h" |
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#include "system/system.h" |
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#include "hw/core/boards.h" |
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#include "qemu/error-report.h" |
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#include "hw/char/pl011.h" |
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#include "hw/ide/ahci-sysbus.h" |
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#include "hw/cpu/a9mpcore.h" |
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#include "hw/cpu/a15mpcore.h" |
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#include "qemu/log.h" |
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#include "qom/object.h" |
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#include "cpu.h" |
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#include "target/arm/cpu-qom.h" |
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|
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#define SMP_BOOT_ADDR 0x100 |
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#define SMP_BOOT_REG 0x40 |
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#define MPCORE_PERIPHBASE 0xfff10000 |
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|
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#define MVBAR_ADDR 0x200 |
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#define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t)) |
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|
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#define GIC_EXT_IRQS 128 /* EnergyCore ECX-1000 & ECX-2000 */ |
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|
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/* Board init. */ |
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#define NUM_REGS 0x200 |
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static void hb_regs_write(void *opaque, hwaddr offset, |
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uint64_t value, unsigned size) |
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{ |
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uint32_t *regs = opaque; |
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|
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if (offset == 0xf00) { |
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if (value == 1 || value == 2) { |
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
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} else if (value == 3) { |
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
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} |
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} |
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|
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if (offset / 4 >= NUM_REGS) { |
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qemu_log_mask(LOG_GUEST_ERROR, |
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"highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset); |
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return; |
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} |
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regs[offset / 4] = value; |
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} |
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|
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static uint64_t hb_regs_read(void *opaque, hwaddr offset, |
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unsigned size) |
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{ |
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uint32_t value; |
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uint32_t *regs = opaque; |
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|
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if (offset / 4 >= NUM_REGS) { |
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qemu_log_mask(LOG_GUEST_ERROR, |
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"highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset); |
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return 0; |
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} |
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value = regs[offset / 4]; |
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if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { |
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value |= 0x30000000; |
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} |
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return value; |
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} |
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|
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static const MemoryRegionOps hb_mem_ops = { |
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.read = hb_regs_read, |
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.write = hb_regs_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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|
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#define TYPE_HIGHBANK_REGISTERS "highbank-regs" |
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OBJECT_DECLARE_SIMPLE_TYPE(HighbankRegsState, HIGHBANK_REGISTERS) |
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struct HighbankRegsState { |
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/*< private >*/ |
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SysBusDevice parent_obj; |
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/*< public >*/ |
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|
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MemoryRegion iomem; |
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uint32_t regs[NUM_REGS]; |
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}; |
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static const VMStateDescription vmstate_highbank_regs = { |
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.name = "highbank-regs", |
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.version_id = 0, |
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.minimum_version_id = 0, |
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.fields = (const VMStateField[]) { |
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VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), |
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VMSTATE_END_OF_LIST(), |
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}, |
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}; |
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static void highbank_regs_reset(DeviceState *dev) |
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{ |
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HighbankRegsState *s = HIGHBANK_REGISTERS(dev); |
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s->regs[0x40] = 0x05F20121; |
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s->regs[0x41] = 0x2; |
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s->regs[0x42] = 0x05F30121; |
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s->regs[0x43] = 0x05F40121; |
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} |
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static void highbank_regs_init(Object *obj) |
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{ |
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HighbankRegsState *s = HIGHBANK_REGISTERS(obj); |
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SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
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memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs, |
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"highbank_regs", 0x1000); |
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sysbus_init_mmio(dev, &s->iomem); |
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} |
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|
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static void highbank_regs_class_init(ObjectClass *klass, const void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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dc->desc = "Calxeda Highbank registers"; |
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dc->vmsd = &vmstate_highbank_regs; |
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device_class_set_legacy_reset(dc, highbank_regs_reset); |
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} |
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static const TypeInfo highbank_regs_info = { |
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.name = TYPE_HIGHBANK_REGISTERS, |
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(HighbankRegsState), |
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.instance_init = highbank_regs_init, |
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.class_init = highbank_regs_class_init, |
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}; |
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static void highbank_regs_register_types(void) |
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{ |
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type_register_static(&highbank_regs_info); |
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} |
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type_init(highbank_regs_register_types) |
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static struct arm_boot_info highbank_binfo; |
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|
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enum cxmachines { |
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CALXEDA_HIGHBANK, |
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CALXEDA_MIDWAY, |
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}; |
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/* ram_size must be set to match the upper bound of memory in the
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* device tree (linux/arch/arm/boot/dts/highbank.dts), which is |
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* normally 0xff900000 or -m 4089. When running this board on a |
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* 32-bit host, set the reg value of memory to 0xf7ff00000 in the |
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* device tree and pass -m 2047 to QEMU. |
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*/ |
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static void calxeda_init(MachineState *machine, enum cxmachines machine_id) |
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{ |
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DeviceState *dev = NULL; |
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SysBusDevice *busdev; |
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qemu_irq pic[GIC_EXT_IRQS]; |
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int n; |
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unsigned int smp_cpus = machine->smp.cpus; |
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qemu_irq cpu_irq[4]; |
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qemu_irq cpu_fiq[4]; |
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qemu_irq cpu_virq[4]; |
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qemu_irq cpu_vfiq[4]; |
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MemoryRegion *sysram; |
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MemoryRegion *sysmem; |
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char *sysboot_filename; |
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switch (machine_id) { |
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case CALXEDA_HIGHBANK: |
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machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); |
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break; |
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case CALXEDA_MIDWAY: |
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machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); |
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break; |
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default: |
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g_assert_not_reached(); |
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} |
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for (n = 0; n < smp_cpus; n++) { |
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Object *cpuobj; |
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ARMCPU *cpu; |
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cpuobj = object_new(machine->cpu_type); |
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cpu = ARM_CPU(cpuobj); |
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object_property_add_child(OBJECT(machine), "cpu[*]", cpuobj); |
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object_property_set_int(cpuobj, "psci-conduit", QEMU_PSCI_CONDUIT_SMC, |
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&error_abort); |
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if (object_property_find(cpuobj, "reset-cbar")) { |
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object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE, |
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&error_abort); |
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} |
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qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); |
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cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); |
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cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ); |
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cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ); |
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cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ); |
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} |
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sysmem = get_system_memory(); |
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/* SDRAM at address zero. */ |
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memory_region_add_subregion(sysmem, 0, machine->ram); |
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sysram = g_new(MemoryRegion, 1); |
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memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000, |
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&error_fatal); |
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memory_region_add_subregion(sysmem, 0xfff88000, sysram); |
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if (machine->firmware != NULL) { |
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sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); |
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if (sysboot_filename != NULL) { |
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if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000, |
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NULL) < 0) { |
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error_report("Unable to load %s", machine->firmware); |
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exit(1); |
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} |
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g_free(sysboot_filename); |
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} else { |
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error_report("Unable to find %s", machine->firmware); |
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exit(1); |
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} |
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} |
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switch (machine_id) { |
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case CALXEDA_HIGHBANK: |
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dev = qdev_new("l2x0"); |
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busdev = SYS_BUS_DEVICE(dev); |
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sysbus_realize_and_unref(busdev, &error_fatal); |
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sysbus_mmio_map(busdev, 0, 0xfff12000); |
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dev = qdev_new(TYPE_A9MPCORE_PRIV); |
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break; |
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case CALXEDA_MIDWAY: |
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dev = qdev_new(TYPE_A15MPCORE_PRIV); |
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break; |
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} |
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qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); |
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qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); |
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busdev = SYS_BUS_DEVICE(dev); |
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sysbus_realize_and_unref(busdev, &error_fatal); |
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sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); |
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for (n = 0; n < smp_cpus; n++) { |
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sysbus_connect_irq(busdev, n, cpu_irq[n]); |
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sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]); |
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sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]); |
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sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]); |
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} |
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for (n = 0; n < GIC_EXT_IRQS; n++) { |
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pic[n] = qdev_get_gpio_in(dev, n); |
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} |
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dev = qdev_new("sp804"); |
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qdev_prop_set_uint32(dev, "freq0", 150000000); |
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qdev_prop_set_uint32(dev, "freq1", 150000000); |
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busdev = SYS_BUS_DEVICE(dev); |
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sysbus_realize_and_unref(busdev, &error_fatal); |
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sysbus_mmio_map(busdev, 0, 0xfff34000); |
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sysbus_connect_irq(busdev, 0, pic[18]); |
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pl011_create(0xfff36000, pic[20], serial_hd(0)); |
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dev = qdev_new(TYPE_HIGHBANK_REGISTERS); |
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busdev = SYS_BUS_DEVICE(dev); |
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sysbus_realize_and_unref(busdev, &error_fatal); |
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sysbus_mmio_map(busdev, 0, 0xfff3c000); |
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sysbus_create_simple("pl061", 0xfff30000, pic[14]); |
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sysbus_create_simple("pl061", 0xfff31000, pic[15]); |
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sysbus_create_simple("pl061", 0xfff32000, pic[16]); |
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sysbus_create_simple("pl061", 0xfff33000, pic[17]); |
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sysbus_create_simple("pl031", 0xfff35000, pic[19]); |
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sysbus_create_simple("pl022", 0xfff39000, pic[23]); |
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sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]); |
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dev = qemu_create_nic_device("xgmac", true, NULL); |
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if (dev) { |
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]); |
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} |
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dev = qemu_create_nic_device("xgmac", true, NULL); |
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if (dev) { |
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]); |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]); |
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} |
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|
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/* TODO create and connect IDE devices for ide_drive_get() */ |
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highbank_binfo.ram_size = machine->ram_size; |
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/* highbank requires a dtb in order to boot, and the dtb will override
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* the board ID. The following value is ignored, so set it to -1 to be |
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* clear that the value is meaningless. |
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*/ |
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highbank_binfo.board_id = -1; |
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highbank_binfo.loader_start = 0; |
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highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; |
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highbank_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC; |
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arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo); |
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} |
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static void highbank_init(MachineState *machine) |
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{ |
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calxeda_init(machine, CALXEDA_HIGHBANK); |
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} |
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static void midway_init(MachineState *machine) |
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{ |
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calxeda_init(machine, CALXEDA_MIDWAY); |
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} |
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|
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static void highbank_class_init(ObjectClass *oc, const void *data) |
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{ |
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static const char * const valid_cpu_types[] = { |
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ARM_CPU_TYPE_NAME("cortex-a9"), |
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NULL |
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}; |
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MachineClass *mc = MACHINE_CLASS(oc); |
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mc->desc = "Calxeda Highbank (ECX-1000)"; |
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mc->init = highbank_init; |
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mc->valid_cpu_types = valid_cpu_types; |
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mc->block_default_type = IF_IDE; |
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mc->units_per_default_bus = 1; |
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mc->max_cpus = 4; |
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mc->ignore_memory_transaction_failures = true; |
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mc->default_ram_id = "highbank.dram"; |
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mc->deprecation_reason = "no known users left for this machine"; |
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} |
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static const TypeInfo highbank_type = { |
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.name = MACHINE_TYPE_NAME("highbank"), |
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.parent = TYPE_MACHINE, |
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.class_init = highbank_class_init, |
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.interfaces = arm_machine_interfaces, |
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}; |
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static void midway_class_init(ObjectClass *oc, const void *data) |
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{ |
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static const char * const valid_cpu_types[] = { |
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ARM_CPU_TYPE_NAME("cortex-a15"), |
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NULL |
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}; |
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MachineClass *mc = MACHINE_CLASS(oc); |
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mc->desc = "Calxeda Midway (ECX-2000)"; |
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mc->init = midway_init; |
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mc->valid_cpu_types = valid_cpu_types; |
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mc->block_default_type = IF_IDE; |
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mc->units_per_default_bus = 1; |
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mc->max_cpus = 4; |
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mc->ignore_memory_transaction_failures = true; |
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mc->default_ram_id = "highbank.dram"; |
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mc->deprecation_reason = "no known users left for this machine"; |
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} |
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static const TypeInfo midway_type = { |
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.name = MACHINE_TYPE_NAME("midway"), |
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.parent = TYPE_MACHINE, |
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.class_init = midway_class_init, |
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.interfaces = arm_machine_interfaces, |
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}; |
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|
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static void calxeda_machines_init(void) |
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{ |
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type_register_static(&highbank_type); |
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type_register_static(&midway_type); |
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} |
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|
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type_init(calxeda_machines_init) |
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Reference in new issue