Browse Source
* Removed the ast2700-a0 SoC and ast2700a0-evb machine. * Added SGPIO support to the ast2700 SoC, including unit tests. * Added several FRU EEPROMs to the Catalina board. * Added support for the new AST1060 SoC and ast1060-evb machine, including functional tests. * Fixed the silicon revision ID register for AST2600 and AST1030 SoCs. * Added an SFDP table for a Winbond flash chip. * Updated documentation for Aspeed boards. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmlbtGMACgkQUaNDx8/7 7KGtVBAAgiCDME1oXrc+ZVmYn8RtRsx/lakp4prbqRbs6A8qoITk3ao6WjNd2k3P kOkvB/xQCqRDSSJIpp8BQhUzDet80b8KUz16iTw1m7KubMIqapmOxVkGJqSc9kGT PfLVjB60rHqiCkInNaaMXxMQuY0iAFKS+SDM8mCGaay0MXdvsEIi+XIcxv2TX0Jo tnHMaJxtSKfzY3QiM7yeB+WryzOlzQ7IMqRkai9tCN1y3XyDy8PodelZFCIGXw/N tw04Z3q/LhmxT6kjvYLmeTETne+1k69gfME+7JhB1hPSrIgdIqM9qyXCROb0U8/W 5mJDkm84blHc4QWITdewiyhIGps9ITxqlIelCExPL1GpEubSg5BVkqFbIjMv+6HJ 2XcBbP+rG6IdEpxeT+PcHw5HvOfLjMY6kGrawpK4s2id5jI9GSSyNY5k576tqRzg P10GfeKUDNDj1nYhUfOmzL6qXb9TqIyQtOVJVGcHkaASnXIqFvL6rYQHcttFej08 YepKqvYBBSwsb2TdSb1t6VKTgCublFUD4jdhph3iqVmfQRl3ei8WJHFKCt8aQ235 HqXzcmBDoTFYqJ97SAg1bvydhVL+rDpd//gcPqVw2cwMnTa2S3zvgI6xj1oBTEf8 YiRPtFYJ03Y9baNZRdGdYAErxIdiliZh+OYfaEFNNn5Zuqp6tYQ= =64bG -----END PGP SIGNATURE----- Merge tag 'pull-aspeed-20260105' of https://github.com/legoater/qemu into staging aspeed queue: * Removed the ast2700-a0 SoC and ast2700a0-evb machine. * Added SGPIO support to the ast2700 SoC, including unit tests. * Added several FRU EEPROMs to the Catalina board. * Added support for the new AST1060 SoC and ast1060-evb machine, including functional tests. * Fixed the silicon revision ID register for AST2600 and AST1030 SoCs. * Added an SFDP table for a Winbond flash chip. * Updated documentation for Aspeed boards. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmlbtGMACgkQUaNDx8/7 # 7KGtVBAAgiCDME1oXrc+ZVmYn8RtRsx/lakp4prbqRbs6A8qoITk3ao6WjNd2k3P # kOkvB/xQCqRDSSJIpp8BQhUzDet80b8KUz16iTw1m7KubMIqapmOxVkGJqSc9kGT # PfLVjB60rHqiCkInNaaMXxMQuY0iAFKS+SDM8mCGaay0MXdvsEIi+XIcxv2TX0Jo # tnHMaJxtSKfzY3QiM7yeB+WryzOlzQ7IMqRkai9tCN1y3XyDy8PodelZFCIGXw/N # tw04Z3q/LhmxT6kjvYLmeTETne+1k69gfME+7JhB1hPSrIgdIqM9qyXCROb0U8/W # 5mJDkm84blHc4QWITdewiyhIGps9ITxqlIelCExPL1GpEubSg5BVkqFbIjMv+6HJ # 2XcBbP+rG6IdEpxeT+PcHw5HvOfLjMY6kGrawpK4s2id5jI9GSSyNY5k576tqRzg # P10GfeKUDNDj1nYhUfOmzL6qXb9TqIyQtOVJVGcHkaASnXIqFvL6rYQHcttFej08 # YepKqvYBBSwsb2TdSb1t6VKTgCublFUD4jdhph3iqVmfQRl3ei8WJHFKCt8aQ235 # HqXzcmBDoTFYqJ97SAg1bvydhVL+rDpd//gcPqVw2cwMnTa2S3zvgI6xj1oBTEf8 # YiRPtFYJ03Y9baNZRdGdYAErxIdiliZh+OYfaEFNNn5Zuqp6tYQ= # =64bG # -----END PGP SIGNATURE----- # gpg: Signature made Mon 05 Jan 2026 11:53:55 PM AEDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] * tag 'pull-aspeed-20260105' of https://github.com/legoater/qemu: (36 commits) hw/i2c/aspeed: Fix wrong I2CC_DMA_LEN when I2CM_DMA_TX/RX_ADDR set first hw/intc/aspeed: Remove TSP 128 - 138 hw/intc/aspeed: Remove SSP 128 - 138 docs/specs/aspeed-intc: Remove GIC 128 - 136 hw/intc/aspeed: Remove GIC 128 - 136 hw/arm/aspeed_ast27x0: Remove ast2700-a0 SOC hw/arm: Remove ast2700a0-evb machine tests/functional: Fix URL of gb200nvl-bmc image test/qtest: Add Unit test for Aspeed SGPIO hw/arm/aspeed_ast27x0: Wire SGPIO controller to AST2700 SoC hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers hw/gpio/aspeed_sgpio: Implement SGPIO interrupt handling hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO hw/arm/aspeed: catalina: add Cable Cartridge FRU EEPROM hw/arm/aspeed: catalina: add NIC FRU EEPROM hw/arm/aspeed: catalina: add HMC FRU EEPROM hw/arm/aspeed: catalina: add GB200-IO FRU EEPROM hw/arm/aspeed: catalina: add GB200 FRU EEPROM hw/arm/aspeed: catalina: add HDD FRU EEPROM ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>pull/316/head
Richard Henderson
3 months ago
27 changed files with 1403 additions and 504 deletions
@ -0,0 +1,346 @@ |
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/*
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* ASPEED Serial GPIO Controller |
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* |
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* Copyright 2025 Google LLC. |
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* |
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* SPDX-License-Identifier: GPL-2.0-or-later |
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*/ |
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|
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#include "qemu/osdep.h" |
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#include "qemu/host-utils.h" |
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#include "qemu/log.h" |
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#include "qemu/error-report.h" |
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#include "qapi/error.h" |
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#include "qapi/visitor.h" |
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#include "hw/core/irq.h" |
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#include "hw/core/qdev-properties.h" |
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#include "hw/gpio/aspeed_sgpio.h" |
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|
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/*
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* For each set of gpios there are three sensitivity registers that control |
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* the interrupt trigger mode. |
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* |
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* | 2 | 1 | 0 | trigger mode |
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* ----------------------------- |
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* | 0 | 0 | 0 | falling-edge |
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* | 0 | 0 | 1 | rising-edge |
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* | 0 | 1 | 0 | level-low |
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* | 0 | 1 | 1 | level-high |
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* | 1 | X | X | dual-edge |
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*/ |
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|
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/* GPIO Interrupt Triggers */ |
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#define ASPEED_FALLING_EDGE 0 |
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#define ASPEED_RISING_EDGE 1 |
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#define ASPEED_LEVEL_LOW 2 |
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#define ASPEED_LEVEL_HIGH 3 |
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#define ASPEED_DUAL_EDGE 4 |
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|
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static void aspeed_clear_irq(AspeedSGPIOState *s, int idx) |
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{ |
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uint32_t reg_index = idx / 32; |
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uint32_t bit_index = idx % 32; |
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uint32_t pending = extract32(s->int_regs[reg_index], bit_index, 1); |
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assert(s->pending >= pending); |
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|
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/* No change to s->pending if pending is 0 */ |
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s->pending -= pending; |
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|
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/*
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* The write acknowledged the interrupt regardless of whether it |
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* was pending or not. The post-condition is that it mustn't be |
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* pending. Unconditionally clear the status bit. |
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*/ |
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s->int_regs[reg_index] = deposit32(s->int_regs[reg_index], bit_index, 1, 0); |
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} |
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|
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static void aspeed_evaluate_irq(AspeedSGPIOState *s, int sgpio_prev_high, |
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int sgpio_curr_high, int idx) |
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{ |
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uint32_t ctrl = s->ctrl_regs[idx]; |
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uint32_t falling_edge = 0, rising_edge = 0; |
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uint32_t int_trigger = SHARED_FIELD_EX32(ctrl, SGPIO_INT_TYPE); |
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uint32_t int_enabled = SHARED_FIELD_EX32(ctrl, SGPIO_INT_EN); |
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uint32_t reg_index = idx / 32; |
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uint32_t bit_index = idx % 32; |
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|
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if (!int_enabled) { |
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return; |
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} |
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|
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/* Detect edges */ |
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if (sgpio_curr_high && !sgpio_prev_high) { |
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rising_edge = 1; |
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} else if (!sgpio_curr_high && sgpio_prev_high) { |
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falling_edge = 1; |
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} |
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if (((int_trigger == ASPEED_FALLING_EDGE) && falling_edge) || |
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((int_trigger == ASPEED_RISING_EDGE) && rising_edge) || |
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((int_trigger == ASPEED_LEVEL_LOW) && !sgpio_curr_high) || |
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((int_trigger == ASPEED_LEVEL_HIGH) && sgpio_curr_high) || |
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((int_trigger >= ASPEED_DUAL_EDGE) && (rising_edge || falling_edge))) |
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{ |
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s->int_regs[reg_index] = deposit32(s->int_regs[reg_index], |
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bit_index, 1, 1); |
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/* Trigger the VIC IRQ */ |
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s->pending++; |
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} |
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} |
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|
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static void aspeed_sgpio_update(AspeedSGPIOState *s, uint32_t idx, |
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uint32_t value) |
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{ |
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uint32_t old = s->ctrl_regs[idx]; |
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uint32_t new = value; |
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uint32_t diff = (old ^ new); |
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if (diff) { |
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/* If the interrupt clear bit is set */ |
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if (SHARED_FIELD_EX32(new, SGPIO_INT_STATUS)) { |
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aspeed_clear_irq(s, idx); |
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/* Clear the interrupt clear bit */ |
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new &= ~SGPIO_INT_STATUS_MASK; |
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} |
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|
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/* Update the control register. */ |
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s->ctrl_regs[idx] = new; |
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|
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/* If the output value is changed */ |
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if (SHARED_FIELD_EX32(diff, SGPIO_SERIAL_OUT_VAL)) { |
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/* ...trigger the line-state IRQ */ |
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qemu_set_irq(s->sgpios[idx], 1); |
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} |
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|
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/* If the input value is changed */ |
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if (SHARED_FIELD_EX32(diff, SGPIO_SERIAL_IN_VAL)) { |
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aspeed_evaluate_irq(s, |
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SHARED_FIELD_EX32(old, SGPIO_SERIAL_IN_VAL), |
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SHARED_FIELD_EX32(new, SGPIO_SERIAL_IN_VAL), |
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idx); |
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} |
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} |
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qemu_set_irq(s->irq, !!(s->pending)); |
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} |
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|
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static uint64_t aspeed_sgpio_2700_read_int_status_reg(AspeedSGPIOState *s, |
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uint32_t reg) |
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{ |
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uint32_t idx = reg - R_SGPIO_INT_STATUS_0; |
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if (idx >= ASPEED_SGPIO_MAX_INT) { |
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qemu_log_mask(LOG_GUEST_ERROR, |
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"%s: interrupt status index: %d, out of bounds\n", |
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__func__, idx); |
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return 0; |
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} |
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return s->int_regs[idx]; |
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} |
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static uint64_t aspeed_sgpio_2700_read_control_reg(AspeedSGPIOState *s, |
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uint32_t reg) |
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{ |
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AspeedSGPIOClass *agc = ASPEED_SGPIO_GET_CLASS(s); |
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uint32_t idx = reg - R_SGPIO_0_CONTROL; |
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if (idx >= agc->nr_sgpio_pin_pairs) { |
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qemu_log_mask(LOG_GUEST_ERROR, "%s: pin index: %d, out of bounds\n", |
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__func__, idx); |
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return 0; |
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} |
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return s->ctrl_regs[idx]; |
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} |
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static void aspeed_sgpio_2700_write_control_reg(AspeedSGPIOState *s, |
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uint32_t reg, uint64_t data) |
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{ |
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AspeedSGPIOClass *agc = ASPEED_SGPIO_GET_CLASS(s); |
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uint32_t idx = reg - R_SGPIO_0_CONTROL; |
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if (idx >= agc->nr_sgpio_pin_pairs) { |
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qemu_log_mask(LOG_GUEST_ERROR, "%s: pin index: %d, out of bounds\n", |
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__func__, idx); |
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return; |
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} |
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aspeed_sgpio_update(s, idx, data); |
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} |
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static uint64_t aspeed_sgpio_2700_read(void *opaque, hwaddr offset, |
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uint32_t size) |
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{ |
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AspeedSGPIOState *s = ASPEED_SGPIO(opaque); |
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uint64_t value = 0; |
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uint64_t reg; |
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reg = offset >> 2; |
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switch (reg) { |
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case R_SGPIO_INT_STATUS_0 ... R_SGPIO_INT_STATUS_7: |
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value = aspeed_sgpio_2700_read_int_status_reg(s, reg); |
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break; |
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case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: |
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value = aspeed_sgpio_2700_read_control_reg(s, reg); |
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break; |
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default: |
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qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" |
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HWADDR_PRIx"\n", __func__, offset); |
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return 0; |
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} |
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return value; |
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} |
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static void aspeed_sgpio_2700_write(void *opaque, hwaddr offset, uint64_t data, |
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uint32_t size) |
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{ |
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AspeedSGPIOState *s = ASPEED_SGPIO(opaque); |
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uint64_t reg; |
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reg = offset >> 2; |
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switch (reg) { |
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case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: |
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aspeed_sgpio_2700_write_control_reg(s, reg, data); |
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break; |
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default: |
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qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" |
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HWADDR_PRIx"\n", __func__, offset); |
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return; |
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} |
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} |
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|
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static bool aspeed_sgpio_get_pin_level(AspeedSGPIOState *s, int pin) |
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{ |
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uint32_t value = s->ctrl_regs[pin >> 1]; |
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bool is_input = !(pin % 2); |
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uint32_t bit_mask = 0; |
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if (is_input) { |
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bit_mask = SGPIO_SERIAL_IN_VAL_MASK; |
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} else { |
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bit_mask = SGPIO_SERIAL_OUT_VAL_MASK; |
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} |
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return value & bit_mask; |
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} |
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static void aspeed_sgpio_set_pin_level(AspeedSGPIOState *s, int pin, bool level) |
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{ |
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uint32_t value = s->ctrl_regs[pin >> 1]; |
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bool is_input = !(pin % 2); |
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uint32_t bit_mask = 0; |
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if (is_input) { |
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bit_mask = SGPIO_SERIAL_IN_VAL_MASK; |
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} else { |
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bit_mask = SGPIO_SERIAL_OUT_VAL_MASK; |
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} |
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if (level) { |
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value |= bit_mask; |
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} else { |
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value &= ~bit_mask; |
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} |
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aspeed_sgpio_update(s, pin >> 1, value); |
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} |
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static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name, |
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void *opaque, Error **errp) |
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{ |
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bool level = true; |
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int pin = 0xfff; |
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AspeedSGPIOState *s = ASPEED_SGPIO(obj); |
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if (sscanf(name, "sgpio%03d", &pin) != 1) { |
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error_setg(errp, "%s: error reading %s", __func__, name); |
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return; |
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} |
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level = aspeed_sgpio_get_pin_level(s, pin); |
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visit_type_bool(v, name, &level, errp); |
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} |
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static void aspeed_sgpio_set_pin(Object *obj, Visitor *v, const char *name, |
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void *opaque, Error **errp) |
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{ |
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bool level; |
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int pin = 0xfff; |
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AspeedSGPIOState *s = ASPEED_SGPIO(obj); |
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if (!visit_type_bool(v, name, &level, errp)) { |
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return; |
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} |
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if (sscanf(name, "sgpio%03d", &pin) != 1) { |
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error_setg(errp, "%s: error reading %s", __func__, name); |
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return; |
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} |
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aspeed_sgpio_set_pin_level(s, pin, level); |
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} |
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static const MemoryRegionOps aspeed_sgpio_2700_ops = { |
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.read = aspeed_sgpio_2700_read, |
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.write = aspeed_sgpio_2700_write, |
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.endianness = DEVICE_LITTLE_ENDIAN, |
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.valid.min_access_size = 4, |
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.valid.max_access_size = 4, |
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}; |
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|
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static void aspeed_sgpio_realize(DeviceState *dev, Error **errp) |
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{ |
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AspeedSGPIOState *s = ASPEED_SGPIO(dev); |
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
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AspeedSGPIOClass *agc = ASPEED_SGPIO_GET_CLASS(s); |
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|
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/* Interrupt parent line */ |
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sysbus_init_irq(sbd, &s->irq); |
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memory_region_init_io(&s->iomem, OBJECT(s), agc->reg_ops, s, |
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TYPE_ASPEED_SGPIO, agc->mem_size); |
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sysbus_init_mmio(sbd, &s->iomem); |
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} |
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|
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static void aspeed_sgpio_init(Object *obj) |
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{ |
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for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR * 2; i++) { |
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g_autofree char *name = g_strdup_printf("sgpio%03d", i); |
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object_property_add(obj, name, "bool", aspeed_sgpio_get_pin, |
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aspeed_sgpio_set_pin, NULL, NULL); |
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} |
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} |
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static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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dc->realize = aspeed_sgpio_realize; |
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dc->desc = "Aspeed SGPIO Controller"; |
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} |
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static void aspeed_sgpio_2700_class_init(ObjectClass *klass, const void *data) |
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{ |
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AspeedSGPIOClass *agc = ASPEED_SGPIO_CLASS(klass); |
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agc->nr_sgpio_pin_pairs = ASPEED_SGPIO_MAX_PIN_PAIR; |
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agc->mem_size = 0x1000; |
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agc->reg_ops = &aspeed_sgpio_2700_ops; |
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} |
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static const TypeInfo aspeed_sgpio_info = { |
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.name = TYPE_ASPEED_SGPIO, |
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(AspeedSGPIOState), |
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.class_size = sizeof(AspeedSGPIOClass), |
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.class_init = aspeed_sgpio_class_init, |
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.abstract = true, |
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}; |
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static const TypeInfo aspeed_sgpio_ast2700_info = { |
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.name = TYPE_ASPEED_SGPIO "-ast2700", |
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.parent = TYPE_ASPEED_SGPIO, |
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.class_init = aspeed_sgpio_2700_class_init, |
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.instance_init = aspeed_sgpio_init, |
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}; |
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|
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static void aspeed_sgpio_register_types(void) |
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{ |
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type_register_static(&aspeed_sgpio_info); |
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type_register_static(&aspeed_sgpio_ast2700_info); |
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} |
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type_init(aspeed_sgpio_register_types); |
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@ -0,0 +1,68 @@ |
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/*
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* ASPEED Serial GPIO Controller |
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* |
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* Copyright 2025 Google LLC. |
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* |
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* SPDX-License-Identifier: GPL-2.0-or-later |
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*/ |
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#ifndef ASPEED_SGPIO_H |
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#define ASPEED_SGPIO_H |
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|
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#include "hw/core/sysbus.h" |
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#include "qom/object.h" |
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#include "hw/core/registerfields.h" |
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|
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#define TYPE_ASPEED_SGPIO "aspeed.sgpio" |
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OBJECT_DECLARE_TYPE(AspeedSGPIOState, AspeedSGPIOClass, ASPEED_SGPIO) |
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|
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#define ASPEED_SGPIO_MAX_PIN_PAIR 256 |
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#define ASPEED_SGPIO_MAX_INT 8 |
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|
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/* AST2700 SGPIO Register Address Offsets */ |
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REG32(SGPIO_INT_STATUS_0, 0x40) |
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REG32(SGPIO_INT_STATUS_1, 0x44) |
|||
REG32(SGPIO_INT_STATUS_2, 0x48) |
|||
REG32(SGPIO_INT_STATUS_3, 0x4C) |
|||
REG32(SGPIO_INT_STATUS_4, 0x50) |
|||
REG32(SGPIO_INT_STATUS_5, 0x54) |
|||
REG32(SGPIO_INT_STATUS_6, 0x58) |
|||
REG32(SGPIO_INT_STATUS_7, 0x5C) |
|||
/* AST2700 SGPIO_0 - SGPIO_255 Control Register */ |
|||
REG32(SGPIO_0_CONTROL, 0x80) |
|||
SHARED_FIELD(SGPIO_SERIAL_OUT_VAL, 0, 1) |
|||
SHARED_FIELD(SGPIO_PARALLEL_OUT_VAL, 1, 1) |
|||
SHARED_FIELD(SGPIO_INT_EN, 2, 1) |
|||
SHARED_FIELD(SGPIO_INT_TYPE, 3, 3) |
|||
SHARED_FIELD(SGPIO_RESET_POLARITY, 6, 1) |
|||
SHARED_FIELD(SGPIO_RESERVED_1, 7, 2) |
|||
SHARED_FIELD(SGPIO_INPUT_MASK, 9, 1) |
|||
SHARED_FIELD(SGPIO_PARALLEL_EN, 10, 1) |
|||
SHARED_FIELD(SGPIO_PARALLEL_IN_MODE, 11, 1) |
|||
SHARED_FIELD(SGPIO_INT_STATUS, 12, 1) |
|||
SHARED_FIELD(SGPIO_SERIAL_IN_VAL, 13, 1) |
|||
SHARED_FIELD(SGPIO_PARALLEL_IN_VAL, 14, 1) |
|||
SHARED_FIELD(SGPIO_RESERVED_2, 15, 12) |
|||
SHARED_FIELD(SGPIO_WRITE_PROTECT, 31, 1) |
|||
REG32(SGPIO_255_CONTROL, 0x47C) |
|||
|
|||
struct AspeedSGPIOClass { |
|||
SysBusDeviceClass parent_class; |
|||
uint32_t nr_sgpio_pin_pairs; |
|||
uint64_t mem_size; |
|||
const MemoryRegionOps *reg_ops; |
|||
}; |
|||
|
|||
struct AspeedSGPIOState { |
|||
/* <private> */ |
|||
SysBusDevice parent; |
|||
|
|||
/*< public >*/ |
|||
MemoryRegion iomem; |
|||
int pending; |
|||
qemu_irq irq; |
|||
qemu_irq sgpios[ASPEED_SGPIO_MAX_PIN_PAIR]; |
|||
uint32_t ctrl_regs[ASPEED_SGPIO_MAX_PIN_PAIR]; |
|||
uint32_t int_regs[ASPEED_SGPIO_MAX_INT]; |
|||
}; |
|||
|
|||
#endif /* ASPEED_SGPIO_H */ |
|||
@ -0,0 +1,52 @@ |
|||
#!/usr/bin/env python3 |
|||
# |
|||
# Functional test that boots the ASPEED SoCs with firmware |
|||
# |
|||
# Copyright (C) 2025 ASPEED Technology Inc |
|||
# |
|||
# SPDX-License-Identifier: GPL-2.0-or-later |
|||
|
|||
from aspeed import AspeedTest |
|||
from qemu_test import Asset, exec_command_and_wait_for_pattern |
|||
|
|||
|
|||
class AST1060Machine(AspeedTest): |
|||
ASSET_ASPEED_AST1060_PROT_3_02 = Asset( |
|||
('https://github.com/AspeedTech-BMC' |
|||
'/aspeed-zephyr-project/releases/download/v03.02' |
|||
'/ast1060_prot_v03.02.tgz'), |
|||
'dd5f1adc935316ddd1906506a02e15567bd7290657b52320f1a225564cc175bd') |
|||
|
|||
def test_arm_ast1060_prot_3_02(self): |
|||
self.set_machine('ast1060-evb') |
|||
|
|||
kernel_name = "ast1060_prot/zephyr.bin" |
|||
kernel_file = self.archive_extract( |
|||
self.ASSET_ASPEED_AST1060_PROT_3_02, member=kernel_name) |
|||
|
|||
self.vm.set_console() |
|||
self.vm.add_args('-kernel', kernel_file, '-nographic') |
|||
self.vm.launch() |
|||
self.wait_for_console_pattern("Booting Zephyr OS") |
|||
exec_command_and_wait_for_pattern(self, "help", |
|||
"Available commands") |
|||
|
|||
def test_arm_ast1060_otp_blockdev_device(self): |
|||
self.vm.set_machine("ast1060-evb") |
|||
|
|||
kernel_name = "ast1060_prot/zephyr.bin" |
|||
kernel_file = self.archive_extract(self.ASSET_ASPEED_AST1060_PROT_3_02, |
|||
member=kernel_name) |
|||
otp_img = self.generate_otpmem_image() |
|||
|
|||
self.vm.set_console() |
|||
self.vm.add_args( |
|||
"-kernel", kernel_file, |
|||
"-blockdev", f"driver=file,filename={otp_img},node-name=otp", |
|||
"-global", "aspeed-otp.drive=otp", |
|||
) |
|||
self.vm.launch() |
|||
self.wait_for_console_pattern("Booting Zephyr OS") |
|||
|
|||
if __name__ == '__main__': |
|||
AspeedTest.main() |
|||
@ -0,0 +1,165 @@ |
|||
/*
|
|||
* QTest testcase for the ASPEED AST2700 SGPIO Controller. |
|||
* |
|||
* SPDX-License-Identifier: GPL-2.0-or-later |
|||
* Copyright (C) 2025 Google LLC. |
|||
*/ |
|||
|
|||
#include "qemu/osdep.h" |
|||
#include "qemu/bitops.h" |
|||
#include "qobject/qdict.h" |
|||
#include "libqtest-single.h" |
|||
#include "hw/core/registerfields.h" |
|||
#include "hw/gpio/aspeed_sgpio.h" |
|||
|
|||
#define AST2700_SGPIO0_BASE 0x14C0C000 |
|||
#define AST2700_SGPIO1_BASE 0x14C0D000 |
|||
|
|||
static void test_output_pins(const char *machine, const uint32_t base, int idx) |
|||
{ |
|||
QTestState *s = qtest_init(machine); |
|||
char name[16]; |
|||
char qom_path[64]; |
|||
uint32_t offset = 0; |
|||
uint32_t value = 0; |
|||
for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { |
|||
/* Odd index is output port */ |
|||
sprintf(name, "sgpio%03d", i * 2 + 1); |
|||
sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); |
|||
offset = base + (R_SGPIO_0_CONTROL + i) * 4; |
|||
/* set serial output */ |
|||
qtest_writel(s, offset, 0x00000001); |
|||
value = qtest_readl(s, offset); |
|||
g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_OUT_VAL), ==, 1); |
|||
g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), ==, true); |
|||
|
|||
/* clear serial output */ |
|||
qtest_writel(s, offset, 0x00000000); |
|||
value = qtest_readl(s, offset); |
|||
g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_OUT_VAL), ==, 0); |
|||
g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), ==, false); |
|||
} |
|||
qtest_quit(s); |
|||
} |
|||
|
|||
static void test_input_pins(const char *machine, const uint32_t base, int idx) |
|||
{ |
|||
QTestState *s = qtest_init(machine); |
|||
char name[16]; |
|||
char qom_path[64]; |
|||
uint32_t offset = 0; |
|||
uint32_t value = 0; |
|||
for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { |
|||
/* Even index is input port */ |
|||
sprintf(name, "sgpio%03d", i * 2); |
|||
sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); |
|||
offset = base + (R_SGPIO_0_CONTROL + i) * 4; |
|||
/* set serial input */ |
|||
qtest_qom_set_bool(s, qom_path, name, true); |
|||
value = qtest_readl(s, offset); |
|||
g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), ==, 1); |
|||
g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), ==, true); |
|||
|
|||
/* clear serial input */ |
|||
qtest_qom_set_bool(s, qom_path, name, false); |
|||
value = qtest_readl(s, offset); |
|||
g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), ==, 0); |
|||
g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), ==, false); |
|||
} |
|||
qtest_quit(s); |
|||
} |
|||
|
|||
static void test_irq_level_high(const char *machine, |
|||
const uint32_t base, int idx) |
|||
{ |
|||
QTestState *s = qtest_init(machine); |
|||
char name[16]; |
|||
char qom_path[64]; |
|||
uint32_t ctrl_offset = 0; |
|||
uint32_t int_offset = 0; |
|||
uint32_t int_reg_idx = 0; |
|||
uint32_t int_bit_idx = 0; |
|||
uint32_t value = 0; |
|||
for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { |
|||
/* Even index is input port */ |
|||
sprintf(name, "sgpio%03d", i * 2); |
|||
sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); |
|||
int_reg_idx = i / 32; |
|||
int_bit_idx = i % 32; |
|||
int_offset = base + (R_SGPIO_INT_STATUS_0 + int_reg_idx) * 4; |
|||
ctrl_offset = base + (R_SGPIO_0_CONTROL + i) * 4; |
|||
|
|||
/* Enable the interrupt */ |
|||
value = SHARED_FIELD_DP32(value, SGPIO_INT_EN, 1); |
|||
qtest_writel(s, ctrl_offset, value); |
|||
|
|||
/* Set the interrupt type to level-high trigger */ |
|||
value = SHARED_FIELD_DP32(qtest_readl(s, ctrl_offset), |
|||
SGPIO_INT_TYPE, 3); |
|||
qtest_writel(s, ctrl_offset, value); |
|||
|
|||
/* Set serial input high */ |
|||
qtest_qom_set_bool(s, qom_path, name, true); |
|||
value = qtest_readl(s, ctrl_offset); |
|||
g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), ==, 1); |
|||
|
|||
/* Interrupt status is set */ |
|||
value = qtest_readl(s, int_offset); |
|||
g_assert_cmphex(extract32(value, int_bit_idx, 1), ==, 1); |
|||
|
|||
/* Clear Interrupt */ |
|||
value = SHARED_FIELD_DP32(qtest_readl(s, ctrl_offset), |
|||
SGPIO_INT_STATUS, 1); |
|||
qtest_writel(s, ctrl_offset, value); |
|||
value = qtest_readl(s, int_offset); |
|||
g_assert_cmphex(extract32(value, int_bit_idx, 1), ==, 0); |
|||
|
|||
/* Clear serial input */ |
|||
qtest_qom_set_bool(s, qom_path, name, false); |
|||
value = qtest_readl(s, ctrl_offset); |
|||
g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), ==, 0); |
|||
} |
|||
qtest_quit(s); |
|||
} |
|||
|
|||
static void test_ast_2700_sgpio_input(void) |
|||
{ |
|||
test_input_pins("-machine ast2700-evb", |
|||
AST2700_SGPIO0_BASE, 0); |
|||
test_input_pins("-machine ast2700-evb", |
|||
AST2700_SGPIO1_BASE, 1); |
|||
} |
|||
|
|||
static void test_ast_2700_sgpio_output(void) |
|||
{ |
|||
test_output_pins("-machine ast2700-evb", |
|||
AST2700_SGPIO0_BASE, 0); |
|||
test_output_pins("-machine ast2700-evb", |
|||
AST2700_SGPIO1_BASE, 1); |
|||
test_irq_level_high("-machine ast2700-evb", |
|||
AST2700_SGPIO0_BASE, 0); |
|||
test_irq_level_high("-machine ast2700-evb", |
|||
AST2700_SGPIO1_BASE, 1); |
|||
} |
|||
|
|||
static void test_ast_2700_sgpio_irq(void) |
|||
{ |
|||
test_irq_level_high("-machine ast2700-evb", |
|||
AST2700_SGPIO0_BASE, 0); |
|||
test_irq_level_high("-machine ast2700-evb", |
|||
AST2700_SGPIO1_BASE, 1); |
|||
} |
|||
|
|||
int main(int argc, char **argv) |
|||
{ |
|||
g_test_init(&argc, &argv, NULL); |
|||
|
|||
qtest_add_func("/ast2700/sgpio/ast_2700_sgpio_input", |
|||
test_ast_2700_sgpio_input); |
|||
qtest_add_func("/ast2700/sgpio/ast_2700_sgpio_output", |
|||
test_ast_2700_sgpio_output); |
|||
qtest_add_func("/ast2700/sgpio/ast_2700_sgpio_irq", |
|||
test_ast_2700_sgpio_irq); |
|||
|
|||
return g_test_run(); |
|||
} |
|||
Loading…
Reference in new issue