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This patch adds support for Milkymist's minimal Ethernet MAC. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>remotes/github/stable-0.15
Michael Walle
16 years ago
committed by
Edgar E. Iglesias
Edgar E. Iglesias
3 changed files with 581 additions and 0 deletions
@ -0,0 +1,568 @@ |
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/*
|
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* QEMU model of the Milkymist minimac block. |
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* |
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* Copyright (c) 2010 Michael Walle <michael@walle.cc> |
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* |
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* This library is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU Lesser General Public |
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* License as published by the Free Software Foundation; either |
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* version 2 of the License, or (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public |
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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* |
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* |
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* Specification available at: |
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* http://www.milkymist.org/socdoc/minimac.pdf
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* |
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*/ |
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#include "hw.h" |
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#include "sysbus.h" |
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#include "trace.h" |
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#include "net.h" |
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#include "qemu-error.h" |
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#include <zlib.h> |
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enum { |
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R_SETUP = 0, |
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R_MDIO, |
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R_STATE0, |
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R_ADDR0, |
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R_COUNT0, |
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R_STATE1, |
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R_ADDR1, |
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R_COUNT1, |
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R_STATE2, |
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R_ADDR2, |
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R_COUNT2, |
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R_STATE3, |
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R_ADDR3, |
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R_COUNT3, |
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R_TXADDR, |
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R_TXCOUNT, |
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R_MAX |
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}; |
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enum { |
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SETUP_RX_RST = (1<<0), |
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SETUP_TX_RST = (1<<2), |
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}; |
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enum { |
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MDIO_DO = (1<<0), |
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MDIO_DI = (1<<1), |
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MDIO_OE = (1<<2), |
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MDIO_CLK = (1<<3), |
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}; |
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enum { |
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STATE_EMPTY = 0, |
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STATE_LOADED = 1, |
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STATE_PENDING = 2, |
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}; |
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enum { |
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MDIO_OP_WRITE = 1, |
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MDIO_OP_READ = 2, |
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}; |
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enum mdio_state { |
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MDIO_STATE_IDLE, |
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MDIO_STATE_READING, |
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MDIO_STATE_WRITING, |
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}; |
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enum { |
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R_PHY_ID1 = 2, |
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R_PHY_ID2 = 3, |
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R_PHY_MAX = 32 |
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}; |
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#define MINIMAC_MTU 1530 |
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struct MilkymistMinimacMdioState { |
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int last_clk; |
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int count; |
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uint32_t data; |
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uint16_t data_out; |
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int state; |
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uint8_t phy_addr; |
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uint8_t reg_addr; |
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}; |
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typedef struct MilkymistMinimacMdioState MilkymistMinimacMdioState; |
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struct MilkymistMinimacState { |
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SysBusDevice busdev; |
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NICState *nic; |
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NICConf conf; |
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char *phy_model; |
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qemu_irq rx_irq; |
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qemu_irq tx_irq; |
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uint32_t regs[R_MAX]; |
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MilkymistMinimacMdioState mdio; |
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uint16_t phy_regs[R_PHY_MAX]; |
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}; |
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typedef struct MilkymistMinimacState MilkymistMinimacState; |
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static const uint8_t preamble_sfd[] = { |
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0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5 |
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}; |
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static void minimac_mdio_write_reg(MilkymistMinimacState *s, |
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uint8_t phy_addr, uint8_t reg_addr, uint16_t value) |
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{ |
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trace_milkymist_minimac_mdio_write(phy_addr, reg_addr, value); |
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/* nop */ |
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} |
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static uint16_t minimac_mdio_read_reg(MilkymistMinimacState *s, |
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uint8_t phy_addr, uint8_t reg_addr) |
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{ |
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uint16_t r = s->phy_regs[reg_addr]; |
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trace_milkymist_minimac_mdio_read(phy_addr, reg_addr, r); |
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return r; |
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} |
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static void minimac_update_mdio(MilkymistMinimacState *s) |
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{ |
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MilkymistMinimacMdioState *m = &s->mdio; |
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/* detect rising clk edge */ |
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if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) { |
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/* shift data in */ |
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int bit = ((s->regs[R_MDIO] & MDIO_DO) |
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&& (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0; |
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m->data = (m->data << 1) | bit; |
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/* check for sync */ |
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if (m->data == 0xffffffff) { |
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m->count = 32; |
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} |
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if (m->count == 16) { |
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uint8_t start = (m->data >> 14) & 0x3; |
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uint8_t op = (m->data >> 12) & 0x3; |
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uint8_t ta = (m->data) & 0x3; |
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if (start == 1 && op == MDIO_OP_WRITE && ta == 2) { |
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m->state = MDIO_STATE_WRITING; |
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} else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) { |
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m->state = MDIO_STATE_READING; |
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} else { |
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m->state = MDIO_STATE_IDLE; |
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} |
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if (m->state != MDIO_STATE_IDLE) { |
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m->phy_addr = (m->data >> 7) & 0x1f; |
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m->reg_addr = (m->data >> 2) & 0x1f; |
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} |
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if (m->state == MDIO_STATE_READING) { |
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m->data_out = minimac_mdio_read_reg(s, m->phy_addr, |
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m->reg_addr); |
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} |
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} |
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if (m->count < 16 && m->state == MDIO_STATE_READING) { |
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int bit = (m->data_out & 0x8000) ? 1 : 0; |
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m->data_out <<= 1; |
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if (bit) { |
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s->regs[R_MDIO] |= MDIO_DI; |
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} else { |
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s->regs[R_MDIO] &= ~MDIO_DI; |
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} |
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} |
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if (m->count == 0 && m->state) { |
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if (m->state == MDIO_STATE_WRITING) { |
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uint16_t data = m->data & 0xffff; |
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minimac_mdio_write_reg(s, m->phy_addr, m->reg_addr, data); |
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} |
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m->state = MDIO_STATE_IDLE; |
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} |
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m->count--; |
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} |
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m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0; |
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} |
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static size_t assemble_frame(uint8_t *buf, size_t size, |
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const uint8_t *payload, size_t payload_size) |
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{ |
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uint32_t crc; |
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if (size < payload_size + 12) { |
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error_report("milkymist_minimac: received too big ethernet frame"); |
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return 0; |
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} |
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/* prepend preamble and sfd */ |
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memcpy(buf, preamble_sfd, 8); |
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/* now copy the payload */ |
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memcpy(buf + 8, payload, payload_size); |
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/* pad frame if needed */ |
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if (payload_size < 60) { |
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memset(buf + payload_size + 8, 0, 60 - payload_size); |
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payload_size = 60; |
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} |
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/* append fcs */ |
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crc = cpu_to_le32(crc32(0, buf + 8, payload_size)); |
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memcpy(buf + payload_size + 8, &crc, 4); |
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return payload_size + 12; |
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} |
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static void minimac_tx(MilkymistMinimacState *s) |
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{ |
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uint8_t buf[MINIMAC_MTU]; |
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uint32_t txcount = s->regs[R_TXCOUNT]; |
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/* do nothing if transmission logic is in reset */ |
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if (s->regs[R_SETUP] & SETUP_TX_RST) { |
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return; |
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} |
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if (txcount < 64) { |
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error_report("milkymist_minimac: ethernet frame too small (%u < %u)\n", |
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txcount, 64); |
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return; |
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} |
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if (txcount > MINIMAC_MTU) { |
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error_report("milkymist_minimac: MTU exceeded (%u > %u)\n", |
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txcount, MINIMAC_MTU); |
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return; |
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} |
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/* dma */ |
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cpu_physical_memory_read(s->regs[R_TXADDR], buf, txcount); |
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if (memcmp(buf, preamble_sfd, 8) != 0) { |
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error_report("milkymist_minimac: frame doesn't contain the preamble " |
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"and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)\n", |
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buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); |
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return; |
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} |
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trace_milkymist_minimac_tx_frame(txcount - 12); |
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/* send packet, skipping preamble and sfd */ |
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qemu_send_packet_raw(&s->nic->nc, buf + 8, txcount - 12); |
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s->regs[R_TXCOUNT] = 0; |
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trace_milkymist_minimac_pulse_irq_tx(); |
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qemu_irq_pulse(s->tx_irq); |
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} |
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static ssize_t minimac_rx(VLANClientState *nc, const uint8_t *buf, size_t size) |
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{ |
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MilkymistMinimacState *s = DO_UPCAST(NICState, nc, nc)->opaque; |
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uint32_t r_addr; |
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uint32_t r_count; |
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uint32_t r_state; |
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uint8_t frame_buf[MINIMAC_MTU]; |
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size_t frame_size; |
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trace_milkymist_minimac_rx_frame(buf, size); |
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/* discard frames if nic is in reset */ |
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if (s->regs[R_SETUP] & SETUP_RX_RST) { |
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return size; |
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} |
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/* choose appropriate slot */ |
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if (s->regs[R_STATE0] == STATE_LOADED) { |
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r_addr = R_ADDR0; |
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r_count = R_COUNT0; |
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r_state = R_STATE0; |
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} else if (s->regs[R_STATE1] == STATE_LOADED) { |
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r_addr = R_ADDR1; |
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r_count = R_COUNT1; |
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r_state = R_STATE1; |
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} else if (s->regs[R_STATE2] == STATE_LOADED) { |
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r_addr = R_ADDR2; |
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r_count = R_COUNT2; |
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r_state = R_STATE2; |
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} else if (s->regs[R_STATE3] == STATE_LOADED) { |
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r_addr = R_ADDR3; |
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r_count = R_COUNT3; |
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r_state = R_STATE3; |
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} else { |
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trace_milkymist_minimac_drop_rx_frame(buf); |
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return size; |
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} |
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/* assemble frame */ |
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frame_size = assemble_frame(frame_buf, sizeof(frame_buf), buf, size); |
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if (frame_size == 0) { |
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return size; |
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} |
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trace_milkymist_minimac_rx_transfer(buf, frame_size); |
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/* do dma */ |
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cpu_physical_memory_write(s->regs[r_addr], frame_buf, frame_size); |
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/* update slot */ |
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s->regs[r_count] = frame_size; |
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s->regs[r_state] = STATE_PENDING; |
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trace_milkymist_minimac_pulse_irq_rx(); |
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qemu_irq_pulse(s->rx_irq); |
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return size; |
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} |
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static uint32_t |
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minimac_read(void *opaque, target_phys_addr_t addr) |
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{ |
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MilkymistMinimacState *s = opaque; |
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uint32_t r = 0; |
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addr >>= 2; |
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switch (addr) { |
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case R_SETUP: |
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case R_MDIO: |
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case R_STATE0: |
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case R_ADDR0: |
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case R_COUNT0: |
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case R_STATE1: |
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case R_ADDR1: |
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case R_COUNT1: |
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case R_STATE2: |
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case R_ADDR2: |
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case R_COUNT2: |
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case R_STATE3: |
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case R_ADDR3: |
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case R_COUNT3: |
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case R_TXADDR: |
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case R_TXCOUNT: |
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r = s->regs[addr]; |
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break; |
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default: |
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error_report("milkymist_minimac: read access to unknown register 0x" |
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TARGET_FMT_plx, addr << 2); |
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break; |
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} |
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trace_milkymist_minimac_memory_read(addr << 2, r); |
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return r; |
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} |
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static void |
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minimac_write(void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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MilkymistMinimacState *s = opaque; |
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trace_milkymist_minimac_memory_read(addr, value); |
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addr >>= 2; |
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switch (addr) { |
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case R_MDIO: |
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{ |
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/* MDIO_DI is read only */ |
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int mdio_di = (s->regs[R_MDIO] & MDIO_DI); |
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s->regs[R_MDIO] = value; |
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if (mdio_di) { |
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s->regs[R_MDIO] |= mdio_di; |
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} else { |
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s->regs[R_MDIO] &= ~mdio_di; |
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} |
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minimac_update_mdio(s); |
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} break; |
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case R_TXCOUNT: |
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s->regs[addr] = value; |
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if (value > 0) { |
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minimac_tx(s); |
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} |
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break; |
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case R_SETUP: |
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case R_STATE0: |
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case R_ADDR0: |
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case R_COUNT0: |
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case R_STATE1: |
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case R_ADDR1: |
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case R_COUNT1: |
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case R_STATE2: |
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case R_ADDR2: |
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case R_COUNT2: |
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case R_STATE3: |
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case R_ADDR3: |
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case R_COUNT3: |
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case R_TXADDR: |
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s->regs[addr] = value; |
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break; |
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default: |
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error_report("milkymist_minimac: write access to unknown register 0x" |
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TARGET_FMT_plx, addr << 2); |
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break; |
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} |
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} |
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static CPUReadMemoryFunc * const minimac_read_fn[] = { |
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NULL, |
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NULL, |
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&minimac_read, |
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}; |
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static CPUWriteMemoryFunc * const minimac_write_fn[] = { |
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NULL, |
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NULL, |
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&minimac_write, |
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}; |
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static int minimac_can_rx(VLANClientState *nc) |
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{ |
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MilkymistMinimacState *s = DO_UPCAST(NICState, nc, nc)->opaque; |
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/* discard frames if nic is in reset */ |
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if (s->regs[R_SETUP] & SETUP_RX_RST) { |
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return 1; |
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} |
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if (s->regs[R_STATE0] == STATE_LOADED) { |
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return 1; |
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} |
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if (s->regs[R_STATE1] == STATE_LOADED) { |
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return 1; |
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} |
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if (s->regs[R_STATE2] == STATE_LOADED) { |
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return 1; |
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} |
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if (s->regs[R_STATE3] == STATE_LOADED) { |
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return 1; |
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} |
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return 0; |
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} |
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static void minimac_cleanup(VLANClientState *nc) |
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{ |
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MilkymistMinimacState *s = DO_UPCAST(NICState, nc, nc)->opaque; |
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s->nic = NULL; |
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} |
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static void milkymist_minimac_reset(DeviceState *d) |
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{ |
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MilkymistMinimacState *s = |
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container_of(d, MilkymistMinimacState, busdev.qdev); |
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int i; |
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for (i = 0; i < R_MAX; i++) { |
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s->regs[i] = 0; |
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} |
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for (i = 0; i < R_PHY_MAX; i++) { |
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s->phy_regs[i] = 0; |
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} |
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/* defaults */ |
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s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */ |
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s->phy_regs[R_PHY_ID2] = 0x161a; |
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} |
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static NetClientInfo net_milkymist_minimac_info = { |
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.type = NET_CLIENT_TYPE_NIC, |
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.size = sizeof(NICState), |
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.can_receive = minimac_can_rx, |
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.receive = minimac_rx, |
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.cleanup = minimac_cleanup, |
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}; |
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static int milkymist_minimac_init(SysBusDevice *dev) |
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{ |
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MilkymistMinimacState *s = FROM_SYSBUS(typeof(*s), dev); |
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int regs; |
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sysbus_init_irq(dev, &s->rx_irq); |
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sysbus_init_irq(dev, &s->tx_irq); |
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regs = cpu_register_io_memory(minimac_read_fn, minimac_write_fn, s, |
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DEVICE_NATIVE_ENDIAN); |
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sysbus_init_mmio(dev, R_MAX * 4, regs); |
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qemu_macaddr_default_if_unset(&s->conf.macaddr); |
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s->nic = qemu_new_nic(&net_milkymist_minimac_info, &s->conf, |
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dev->qdev.info->name, dev->qdev.id, s); |
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qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
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return 0; |
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} |
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static const VMStateDescription vmstate_milkymist_minimac_mdio = { |
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.name = "milkymist_minimac_mdio", |
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.version_id = 1, |
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.minimum_version_id = 1, |
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.minimum_version_id_old = 1, |
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.fields = (VMStateField[]) { |
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VMSTATE_INT32(last_clk, MilkymistMinimacMdioState), |
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VMSTATE_INT32(count, MilkymistMinimacMdioState), |
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VMSTATE_UINT32(data, MilkymistMinimacMdioState), |
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VMSTATE_UINT16(data_out, MilkymistMinimacMdioState), |
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VMSTATE_INT32(state, MilkymistMinimacMdioState), |
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VMSTATE_UINT8(phy_addr, MilkymistMinimacMdioState), |
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VMSTATE_UINT8(reg_addr, MilkymistMinimacMdioState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const VMStateDescription vmstate_milkymist_minimac = { |
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.name = "milkymist-minimac", |
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.version_id = 1, |
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.minimum_version_id = 1, |
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.minimum_version_id_old = 1, |
|||
.fields = (VMStateField[]) { |
|||
VMSTATE_UINT32_ARRAY(regs, MilkymistMinimacState, R_MAX), |
|||
VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimacState, R_PHY_MAX), |
|||
VMSTATE_STRUCT(mdio, MilkymistMinimacState, 0, |
|||
vmstate_milkymist_minimac_mdio, MilkymistMinimacMdioState), |
|||
VMSTATE_END_OF_LIST() |
|||
} |
|||
}; |
|||
|
|||
static SysBusDeviceInfo milkymist_minimac_info = { |
|||
.init = milkymist_minimac_init, |
|||
.qdev.name = "milkymist-minimac", |
|||
.qdev.size = sizeof(MilkymistMinimacState), |
|||
.qdev.vmsd = &vmstate_milkymist_minimac, |
|||
.qdev.reset = milkymist_minimac_reset, |
|||
.qdev.props = (Property[]) { |
|||
DEFINE_NIC_PROPERTIES(MilkymistMinimacState, conf), |
|||
DEFINE_PROP_STRING("phy_model", MilkymistMinimacState, phy_model), |
|||
DEFINE_PROP_END_OF_LIST(), |
|||
} |
|||
}; |
|||
|
|||
static void milkymist_minimac_register(void) |
|||
{ |
|||
sysbus_register_withprop(&milkymist_minimac_info); |
|||
} |
|||
|
|||
device_init(milkymist_minimac_register) |
|||
Loading…
Reference in new issue