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hw/misc/xlnx-versal-crl: add the versal2 version 

Add the versal2 version of the CRL device. For the implemented part, it
is similar to the versal version but drives reset line of more devices.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250926070806.292065-37-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
pull/305/head
Luc Michel 6 months ago
committed by Peter Maydell
parent
4707024bc3
commit
00580a9d71
3 changed files with 722 additions and 0 deletions
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  1. 392
      hw/misc/xlnx-versal-crl.c
  2. 1
      include/hw/arm/xlnx-versal-version.h
  3. 329
      include/hw/misc/xlnx-versal-crl.h

392
hw/misc/xlnx-versal-crl.c
View File

@ -83,6 +83,51 @@ static DeviceState **versal_decode_periph_rst(XlnxVersalCRLBase *s,
case A_RST_USB0:
return xvc->cfg.usb;
default:
/* invalid or unimplemented */
g_assert_not_reached();
}
}
static DeviceState **versal2_decode_periph_rst(XlnxVersalCRLBase *s,
hwaddr addr, size_t *count)
{
size_t idx;
XlnxVersal2CRL *xvc = XLNX_VERSAL2_CRL(s);
*count = 1;
switch (addr) {
case A_VERSAL2_RST_RPU_A ... A_VERSAL2_RST_RPU_E:
idx = (addr - A_VERSAL2_RST_RPU_A) / sizeof(uint32_t);
idx *= 2; /* two RPUs per RST_RPU_x registers */
return xvc->cfg.rpu + idx;
case A_VERSAL2_RST_ADMA:
/* A single register fans out to all DMA reset inputs */
*count = ARRAY_SIZE(xvc->cfg.adma);
return xvc->cfg.adma;
case A_VERSAL2_RST_SDMA:
*count = ARRAY_SIZE(xvc->cfg.sdma);
return xvc->cfg.sdma;
case A_VERSAL2_RST_UART0 ... A_VERSAL2_RST_UART1:
idx = (addr - A_VERSAL2_RST_UART0) / sizeof(uint32_t);
return xvc->cfg.uart + idx;
case A_VERSAL2_RST_GEM0 ... A_VERSAL2_RST_GEM1:
idx = (addr - A_VERSAL2_RST_GEM0) / sizeof(uint32_t);
return xvc->cfg.gem + idx;
case A_VERSAL2_RST_USB0 ... A_VERSAL2_RST_USB1:
idx = (addr - A_VERSAL2_RST_USB0) / sizeof(uint32_t);
return xvc->cfg.usb + idx;
case A_VERSAL2_RST_CAN0 ... A_VERSAL2_RST_CAN3:
idx = (addr - A_VERSAL2_RST_CAN0) / sizeof(uint32_t);
return xvc->cfg.can + idx;
default:
/* invalid or unimplemented */
return NULL;
@ -307,6 +352,246 @@ static const RegisterAccessInfo crl_regs_info[] = {
}
};
static const RegisterAccessInfo versal2_crl_regs_info[] = {
{ .name = "ERR_CTRL", .addr = A_VERSAL2_ERR_CTRL,
.reset = 0x1,
},{ .name = "WPROT", .addr = A_VERSAL2_WPROT,
},{ .name = "RPLL_CTRL", .addr = A_VERSAL2_RPLL_CTRL,
.reset = 0x24809,
.rsvd = 0xf88c00f6,
},{ .name = "RPLL_CFG", .addr = A_VERSAL2_RPLL_CFG,
.reset = 0x7e5dcc6c,
.rsvd = 0x1801210,
},{ .name = "FLXPLL_CTRL", .addr = A_VERSAL2_FLXPLL_CTRL,
.reset = 0x24809,
.rsvd = 0xf88c00f6,
},{ .name = "FLXPLL_CFG", .addr = A_VERSAL2_FLXPLL_CFG,
.reset = 0x7e5dcc6c,
.rsvd = 0x1801210,
},{ .name = "PLL_STATUS", .addr = A_VERSAL2_PLL_STATUS,
.reset = 0xf,
.rsvd = 0xf0,
.ro = 0xf,
},{ .name = "RPLL_TO_XPD_CTRL", .addr = A_VERSAL2_RPLL_TO_XPD_CTRL,
.reset = 0x2000100,
.rsvd = 0xfdfc00ff,
},{ .name = "LPX_TOP_SWITCH_CTRL", .addr = A_VERSAL2_LPX_TOP_SWITCH_CTRL,
.reset = 0xe000300,
.rsvd = 0xf1fc00f8,
},{ .name = "LPX_LSBUS_CLK_CTRL", .addr = A_VERSAL2_LPX_LSBUS_CLK_CTRL,
.reset = 0x2000800,
.rsvd = 0xfdfc00f8,
},{ .name = "RPU_CLK_CTRL", .addr = A_VERSAL2_RPU_CLK_CTRL,
.reset = 0x3f00300,
.rsvd = 0xfc0c00f8,
},{ .name = "OCM_CLK_CTRL", .addr = A_VERSAL2_OCM_CLK_CTRL,
.reset = 0x1e00000,
.rsvd = 0xfe1fffff,
},{ .name = "IOU_SWITCH_CLK_CTRL", .addr = A_VERSAL2_IOU_SWITCH_CLK_CTRL,
.reset = 0x2000500,
.rsvd = 0xfdfc00f8,
},{ .name = "GEM0_REF_CTRL", .addr = A_VERSAL2_GEM0_REF_CTRL,
.reset = 0xe000a00,
.rsvd = 0xf1fc00f8,
},{ .name = "GEM1_REF_CTRL", .addr = A_VERSAL2_GEM1_REF_CTRL,
.reset = 0xe000a00,
.rsvd = 0xf1fc00f8,
},{ .name = "GEM_TSU_REF_CLK_CTRL", .addr = A_VERSAL2_GEM_TSU_REF_CLK_CTRL,
.reset = 0x300,
.rsvd = 0xfdfc00f8,
},{ .name = "USB0_BUS_REF_CLK_CTRL",
.addr = A_VERSAL2_USB0_BUS_REF_CLK_CTRL,
.reset = 0x2001900,
.rsvd = 0xfdfc00f8,
},{ .name = "USB1_BUS_REF_CLK_CTRL",
.addr = A_VERSAL2_USB1_BUS_REF_CLK_CTRL,
.reset = 0x2001900,
.rsvd = 0xfdfc00f8,
},{ .name = "UART0_REF_CLK_CTRL", .addr = A_VERSAL2_UART0_REF_CLK_CTRL,
.reset = 0xc00,
.rsvd = 0xfdfc00f8,
},{ .name = "UART1_REF_CLK_CTRL", .addr = A_VERSAL2_UART1_REF_CLK_CTRL,
.reset = 0xc00,
.rsvd = 0xfdfc00f8,
},{ .name = "SPI0_REF_CLK_CTRL", .addr = A_VERSAL2_SPI0_REF_CLK_CTRL,
.reset = 0x600,
.rsvd = 0xfdfc00f8,
},{ .name = "SPI1_REF_CLK_CTRL", .addr = A_VERSAL2_SPI1_REF_CLK_CTRL,
.reset = 0x600,
.rsvd = 0xfdfc00f8,
},{ .name = "CAN0_REF_2X_CTRL", .addr = A_VERSAL2_CAN0_REF_2X_CTRL,
.reset = 0xc00,
.rsvd = 0xfdfc00f8,
},{ .name = "CAN1_REF_2X_CTRL", .addr = A_VERSAL2_CAN1_REF_2X_CTRL,
.reset = 0xc00,
.rsvd = 0xfdfc00f8,
},{ .name = "CAN2_REF_2X_CTRL", .addr = A_VERSAL2_CAN2_REF_2X_CTRL,
.reset = 0xc00,
.rsvd = 0xfdfc00f8,
},{ .name = "CAN3_REF_2X_CTRL", .addr = A_VERSAL2_CAN3_REF_2X_CTRL,
.reset = 0xc00,
.rsvd = 0xfdfc00f8,
},{ .name = "I3C0_REF_CTRL", .addr = A_VERSAL2_I3C0_REF_CTRL,
.reset = 0x2000c00,
.rsvd = 0xfdfc00f8,
},{ .name = "I3C1_REF_CTRL", .addr = A_VERSAL2_I3C1_REF_CTRL,
.reset = 0x2000c00,
.rsvd = 0xfdfc00f8,
},{ .name = "I3C2_REF_CTRL", .addr = A_VERSAL2_I3C2_REF_CTRL,
.reset = 0x2000c00,
.rsvd = 0xfdfc00f8,
},{ .name = "I3C3_REF_CTRL", .addr = A_VERSAL2_I3C3_REF_CTRL,
.reset = 0x2000c00,
.rsvd = 0xfdfc00f8,
},{ .name = "I3C4_REF_CTRL", .addr = A_VERSAL2_I3C4_REF_CTRL,
.reset = 0x2000c00,
.rsvd = 0xfdfc00f8,
},{ .name = "I3C5_REF_CTRL", .addr = A_VERSAL2_I3C5_REF_CTRL,
.reset = 0x2000c00,
.rsvd = 0xfdfc00f8,
},{ .name = "I3C6_REF_CTRL", .addr = A_VERSAL2_I3C6_REF_CTRL,
.reset = 0x2000c00,
.rsvd = 0xfdfc00f8,
},{ .name = "I3C7_REF_CTRL", .addr = A_VERSAL2_I3C7_REF_CTRL,
.reset = 0x2000c00,
.rsvd = 0xfdfc00f8,
},{ .name = "DBG_LPX_CTRL", .addr = A_VERSAL2_DBG_LPX_CTRL,
.reset = 0x300,
.rsvd = 0xfdfc00f8,
},{ .name = "TIMESTAMP_REF_CTRL", .addr = A_VERSAL2_TIMESTAMP_REF_CTRL,
.reset = 0x2000c00,
.rsvd = 0xfdfc00f8,
},{ .name = "SAFETY_CHK", .addr = A_VERSAL2_SAFETY_CHK,
},{ .name = "ASU_CLK_CTRL", .addr = A_VERSAL2_ASU_CLK_CTRL,
.reset = 0x2000f04,
.rsvd = 0xfdfc00f8,
},{ .name = "DBG_TSTMP_CLK_CTRL", .addr = A_VERSAL2_DBG_TSTMP_CLK_CTRL,
.reset = 0x300,
.rsvd = 0xfdfc00f8,
},{ .name = "MMI_TOPSW_CLK_CTRL", .addr = A_VERSAL2_MMI_TOPSW_CLK_CTRL,
.reset = 0x2000300,
.rsvd = 0xfdfc00f8,
},{ .name = "WWDT_PLL_CLK_CTRL", .addr = A_VERSAL2_WWDT_PLL_CLK_CTRL,
.reset = 0xc00,
.rsvd = 0xfffc00f8,
},{ .name = "RCLK_CTRL", .addr = A_VERSAL2_RCLK_CTRL,
.rsvd = 0xc040,
},{ .name = "RST_RPU_A", .addr = A_VERSAL2_RST_RPU_A,
.reset = 0x10303,
.rsvd = 0xfffefcfc,
.pre_write = crl_rst_cpu_prew,
},{ .name = "RST_RPU_B", .addr = A_VERSAL2_RST_RPU_B,
.reset = 0x10303,
.rsvd = 0xfffefcfc,
.pre_write = crl_rst_cpu_prew,
},{ .name = "RST_RPU_C", .addr = A_VERSAL2_RST_RPU_C,
.reset = 0x10303,
.rsvd = 0xfffefcfc,
.pre_write = crl_rst_cpu_prew,
},{ .name = "RST_RPU_D", .addr = A_VERSAL2_RST_RPU_D,
.reset = 0x10303,
.rsvd = 0xfffefcfc,
.pre_write = crl_rst_cpu_prew,
},{ .name = "RST_RPU_E", .addr = A_VERSAL2_RST_RPU_E,
.reset = 0x10303,
.rsvd = 0xfffefcfc,
.pre_write = crl_rst_cpu_prew,
},{ .name = "RST_RPU_GD_0", .addr = A_VERSAL2_RST_RPU_GD_0,
.reset = 0x3,
},{ .name = "RST_RPU_GD_1", .addr = A_VERSAL2_RST_RPU_GD_1,
.reset = 0x3,
},{ .name = "RST_ASU_GD", .addr = A_VERSAL2_RST_ASU_GD,
.reset = 0x3,
},{ .name = "RST_ADMA", .addr = A_VERSAL2_RST_ADMA,
.reset = 0x1,
.pre_write = crl_rst_dev_prew,
},{ .name = "RST_SDMA", .addr = A_VERSAL2_RST_SDMA,
.pre_write = crl_rst_dev_prew,
.reset = 0x1,
},{ .name = "RST_GEM0", .addr = A_VERSAL2_RST_GEM0,
.reset = 0x1,
.pre_write = crl_rst_dev_prew,
},{ .name = "RST_GEM1", .addr = A_VERSAL2_RST_GEM1,
.reset = 0x1,
.pre_write = crl_rst_dev_prew,
},{ .name = "RST_USB0", .addr = A_VERSAL2_RST_USB0,
.reset = 0x1,
.pre_write = crl_rst_dev_prew,
},{ .name = "RST_USB1", .addr = A_VERSAL2_RST_USB1,
.reset = 0x1,
.pre_write = crl_rst_dev_prew,
},{ .name = "RST_UART0", .addr = A_VERSAL2_RST_UART0,
.reset = 0x1,
.pre_write = crl_rst_dev_prew,
},{ .name = "RST_UART1", .addr = A_VERSAL2_RST_UART1,
.reset = 0x1,
.pre_write = crl_rst_dev_prew,
},{ .name = "RST_SPI0", .addr = A_VERSAL2_RST_SPI0,
.reset = 0x1,
},{ .name = "RST_SPI1", .addr = A_VERSAL2_RST_SPI1,
.reset = 0x1,
},{ .name = "RST_CAN0", .addr = A_VERSAL2_RST_CAN0,
.reset = 0x1,
.pre_write = crl_rst_dev_prew,
},{ .name = "RST_CAN1", .addr = A_VERSAL2_RST_CAN1,
.reset = 0x1,
.pre_write = crl_rst_dev_prew,
},{ .name = "RST_CAN2", .addr = A_VERSAL2_RST_CAN2,
.reset = 0x1,
.pre_write = crl_rst_dev_prew,
},{ .name = "RST_CAN3", .addr = A_VERSAL2_RST_CAN3,
.reset = 0x1,
.pre_write = crl_rst_dev_prew,
},{ .name = "RST_I3C0", .addr = A_VERSAL2_RST_I3C0,
.reset = 0x1,
},{ .name = "RST_I3C1", .addr = A_VERSAL2_RST_I3C1,
.reset = 0x1,
},{ .name = "RST_I3C2", .addr = A_VERSAL2_RST_I3C2,
.reset = 0x1,
},{ .name = "RST_I3C3", .addr = A_VERSAL2_RST_I3C3,
.reset = 0x1,
},{ .name = "RST_I3C4", .addr = A_VERSAL2_RST_I3C4,
.reset = 0x1,
},{ .name = "RST_I3C5", .addr = A_VERSAL2_RST_I3C5,
.reset = 0x1,
},{ .name = "RST_I3C6", .addr = A_VERSAL2_RST_I3C6,
.reset = 0x1,
},{ .name = "RST_I3C7", .addr = A_VERSAL2_RST_I3C7,
.reset = 0x1,
},{ .name = "RST_DBG_LPX", .addr = A_VERSAL2_RST_DBG_LPX,
.reset = 0x3,
.rsvd = 0xfc,
},{ .name = "RST_GPIO", .addr = A_VERSAL2_RST_GPIO,
.reset = 0x1,
},{ .name = "RST_TTC", .addr = A_VERSAL2_RST_TTC,
.reset = 0xff,
},{ .name = "RST_TIMESTAMP", .addr = A_VERSAL2_RST_TIMESTAMP,
.reset = 0x1,
},{ .name = "RST_SWDT0", .addr = A_VERSAL2_RST_SWDT0,
.reset = 0x1,
},{ .name = "RST_SWDT1", .addr = A_VERSAL2_RST_SWDT1,
.reset = 0x1,
},{ .name = "RST_SWDT2", .addr = A_VERSAL2_RST_SWDT2,
.reset = 0x1,
},{ .name = "RST_SWDT3", .addr = A_VERSAL2_RST_SWDT3,
.reset = 0x1,
},{ .name = "RST_SWDT4", .addr = A_VERSAL2_RST_SWDT4,
.reset = 0x1,
},{ .name = "RST_IPI", .addr = A_VERSAL2_RST_IPI,
},{ .name = "RST_SYSMON", .addr = A_VERSAL2_RST_SYSMON,
},{ .name = "ASU_MB_RST_MODE", .addr = A_VERSAL2_ASU_MB_RST_MODE,
.reset = 0x1,
.rsvd = 0xf8,
},{ .name = "FPX_TOPSW_MUX_CTRL", .addr = A_VERSAL2_FPX_TOPSW_MUX_CTRL,
.reset = 0x1,
},{ .name = "RST_FPX", .addr = A_VERSAL2_RST_FPX,
.reset = 0x3,
},{ .name = "RST_MMI", .addr = A_VERSAL2_RST_MMI,
.reset = 0x1,
},{ .name = "RST_OCM", .addr = A_VERSAL2_RST_OCM,
}
};
static void versal_crl_reset_enter(Object *obj, ResetType type)
{
XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
@ -317,6 +602,16 @@ static void versal_crl_reset_enter(Object *obj, ResetType type)
}
}
static void versal2_crl_reset_enter(Object *obj, ResetType type)
{
XlnxVersal2CRL *s = XLNX_VERSAL2_CRL(obj);
size_t i;
for (i = 0; i < VERSAL2_CRL_R_MAX; ++i) {
register_reset(&s->regs_info[i]);
}
}
static void versal_crl_reset_hold(Object *obj, ResetType type)
{
XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
@ -388,6 +683,73 @@ static void versal_crl_init(Object *obj)
}
}
static void versal2_crl_init(Object *obj)
{
XlnxVersal2CRL *s = XLNX_VERSAL2_CRL(obj);
XlnxVersalCRLBase *xvcb = XLNX_VERSAL_CRL_BASE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
size_t i;
xvcb->reg_array = register_init_block32(DEVICE(obj), versal2_crl_regs_info,
ARRAY_SIZE(versal2_crl_regs_info),
s->regs_info, s->regs,
&crl_ops,
XLNX_VERSAL_CRL_ERR_DEBUG,
VERSAL2_CRL_R_MAX * 4);
xvcb->regs = s->regs;
sysbus_init_mmio(sbd, &xvcb->reg_array->mem);
for (i = 0; i < ARRAY_SIZE(s->cfg.rpu); ++i) {
object_property_add_link(obj, "rpu[*]", TYPE_ARM_CPU,
(Object **)&s->cfg.rpu[i],
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
}
for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) {
object_property_add_link(obj, "adma[*]", TYPE_DEVICE,
(Object **)&s->cfg.adma[i],
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
}
for (i = 0; i < ARRAY_SIZE(s->cfg.sdma); ++i) {
object_property_add_link(obj, "sdma[*]", TYPE_DEVICE,
(Object **)&s->cfg.sdma[i],
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
}
for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) {
object_property_add_link(obj, "uart[*]", TYPE_DEVICE,
(Object **)&s->cfg.uart[i],
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
}
for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) {
object_property_add_link(obj, "gem[*]", TYPE_DEVICE,
(Object **)&s->cfg.gem[i],
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
}
for (i = 0; i < ARRAY_SIZE(s->cfg.usb); ++i) {
object_property_add_link(obj, "usb[*]", TYPE_DEVICE,
(Object **)&s->cfg.usb[i],
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
}
for (i = 0; i < ARRAY_SIZE(s->cfg.can); ++i) {
object_property_add_link(obj, "can[*]", TYPE_DEVICE,
(Object **)&s->cfg.can[i],
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
}
}
static void crl_finalize(Object *obj)
{
XlnxVersalCRLBase *s = XLNX_VERSAL_CRL_BASE(obj);
@ -404,6 +766,16 @@ static const VMStateDescription vmstate_versal_crl = {
}
};
static const VMStateDescription vmstate_versal2_crl = {
.name = TYPE_XLNX_VERSAL2_CRL,
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, XlnxVersal2CRL, VERSAL2_CRL_R_MAX),
VMSTATE_END_OF_LIST(),
}
};
static void versal_crl_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -416,6 +788,17 @@ static void versal_crl_class_init(ObjectClass *klass, const void *data)
xvcc->decode_periph_rst = versal_decode_periph_rst;
}
static void versal2_crl_class_init(ObjectClass *klass, const void *data)
{
XlnxVersalCRLBaseClass *xvcc = XLNX_VERSAL_CRL_BASE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->vmsd = &vmstate_versal2_crl;
rc->phases.enter = versal2_crl_reset_enter;
xvcc->decode_periph_rst = versal2_decode_periph_rst;
}
static const TypeInfo crl_base_info = {
.name = TYPE_XLNX_VERSAL_CRL_BASE,
.parent = TYPE_SYS_BUS_DEVICE,
@ -433,10 +816,19 @@ static const TypeInfo versal_crl_info = {
.class_init = versal_crl_class_init,
};
static const TypeInfo versal2_crl_info = {
.name = TYPE_XLNX_VERSAL2_CRL,
.parent = TYPE_XLNX_VERSAL_CRL_BASE,
.instance_size = sizeof(XlnxVersal2CRL),
.instance_init = versal2_crl_init,
.class_init = versal2_crl_class_init,
};
static void crl_register_types(void)
{
type_register_static(&crl_base_info);
type_register_static(&versal_crl_info);
type_register_static(&versal2_crl_info);
}
type_init(crl_register_types)

1
include/hw/arm/xlnx-versal-version.h
View File

@ -10,6 +10,7 @@
typedef enum VersalVersion {
VERSAL_VER_VERSAL,
VERSAL_VER_VERSAL2,
} VersalVersion;
#endif

329
include/hw/misc/xlnx-versal-crl.h
View File

@ -17,10 +17,12 @@
#define TYPE_XLNX_VERSAL_CRL_BASE "xlnx-versal-crl-base"
#define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl"
#define TYPE_XLNX_VERSAL2_CRL "xlnx-versal2-crl"
OBJECT_DECLARE_TYPE(XlnxVersalCRLBase, XlnxVersalCRLBaseClass,
XLNX_VERSAL_CRL_BASE)
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersal2CRL, XLNX_VERSAL2_CRL)
REG32(ERR_CTRL, 0x0)
FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
@ -220,6 +222,314 @@ REG32(PSM_RST_MODE, 0x370)
#define CRL_R_MAX (R_PSM_RST_MODE + 1)
REG32(VERSAL2_ERR_CTRL, 0x0)
REG32(VERSAL2_WPROT, 0x1c)
FIELD(VERSAL2_WPROT, ACTIVE, 0, 1)
REG32(VERSAL2_RPLL_CTRL, 0x40)
FIELD(VERSAL2_RPLL_CTRL, POST_SRC, 24, 3)
FIELD(VERSAL2_RPLL_CTRL, PRE_SRC, 20, 3)
FIELD(VERSAL2_RPLL_CTRL, CLKOUTDIV, 16, 2)
FIELD(VERSAL2_RPLL_CTRL, FBDIV, 8, 8)
FIELD(VERSAL2_RPLL_CTRL, BYPASS, 3, 1)
FIELD(VERSAL2_RPLL_CTRL, RESET, 0, 1)
REG32(VERSAL2_RPLL_CFG, 0x44)
FIELD(VERSAL2_RPLL_CFG, LOCK_DLY, 25, 7)
FIELD(VERSAL2_RPLL_CFG, LOCK_CNT, 13, 10)
FIELD(VERSAL2_RPLL_CFG, LFHF, 10, 2)
FIELD(VERSAL2_RPLL_CFG, CP, 5, 4)
FIELD(VERSAL2_RPLL_CFG, RES, 0, 4)
REG32(VERSAL2_FLXPLL_CTRL, 0x50)
FIELD(VERSAL2_FLXPLL_CTRL, POST_SRC, 24, 3)
FIELD(VERSAL2_FLXPLL_CTRL, PRE_SRC, 20, 3)
FIELD(VERSAL2_FLXPLL_CTRL, CLKOUTDIV, 16, 2)
FIELD(VERSAL2_FLXPLL_CTRL, FBDIV, 8, 8)
FIELD(VERSAL2_FLXPLL_CTRL, BYPASS, 3, 1)
FIELD(VERSAL2_FLXPLL_CTRL, RESET, 0, 1)
REG32(VERSAL2_FLXPLL_CFG, 0x54)
FIELD(VERSAL2_FLXPLL_CFG, LOCK_DLY, 25, 7)
FIELD(VERSAL2_FLXPLL_CFG, LOCK_CNT, 13, 10)
FIELD(VERSAL2_FLXPLL_CFG, LFHF, 10, 2)
FIELD(VERSAL2_FLXPLL_CFG, CP, 5, 4)
FIELD(VERSAL2_FLXPLL_CFG, RES, 0, 4)
REG32(VERSAL2_PLL_STATUS, 0x60)
FIELD(VERSAL2_PLL_STATUS, FLXPLL_STABLE, 3, 1)
FIELD(VERSAL2_PLL_STATUS, RPLL_STABLE, 2, 1)
FIELD(VERSAL2_PLL_STATUS, FLXPLL_LOCK, 1, 1)
FIELD(VERSAL2_PLL_STATUS, RPLL_LOCK, 0, 1)
REG32(VERSAL2_RPLL_TO_XPD_CTRL, 0x100)
FIELD(VERSAL2_RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
REG32(VERSAL2_LPX_TOP_SWITCH_CTRL, 0x104)
FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1)
FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_LPX_LSBUS_CLK_CTRL, 0x108)
FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_RPU_CLK_CTRL, 0x10c)
FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERE, 24, 1)
FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERD, 23, 1)
FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERC, 22, 1)
FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERB, 21, 1)
FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERA, 20, 1)
FIELD(VERSAL2_RPU_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_RPU_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_OCM_CLK_CTRL, 0x120)
FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM3, 24, 1)
FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM2, 23, 1)
FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM1, 22, 1)
FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM0, 21, 1)
REG32(VERSAL2_IOU_SWITCH_CLK_CTRL, 0x124)
FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_GEM0_REF_CTRL, 0x128)
FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT_RX, 27, 1)
FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT_TX, 26, 1)
FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_GEM0_REF_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_GEM0_REF_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_GEM1_REF_CTRL, 0x12c)
FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT_RX, 27, 1)
FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT_TX, 26, 1)
FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_GEM1_REF_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_GEM1_REF_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_GEM_TSU_REF_CLK_CTRL, 0x130)
FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_USB0_BUS_REF_CLK_CTRL, 0x134)
FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_USB1_BUS_REF_CLK_CTRL, 0x138)
FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_UART0_REF_CLK_CTRL, 0x13c)
FIELD(VERSAL2_UART0_REF_CLK_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_UART0_REF_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_UART0_REF_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_UART1_REF_CLK_CTRL, 0x140)
FIELD(VERSAL2_UART1_REF_CLK_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_UART1_REF_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_UART1_REF_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_SPI0_REF_CLK_CTRL, 0x144)
FIELD(VERSAL2_SPI0_REF_CLK_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_SPI0_REF_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_SPI0_REF_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_SPI1_REF_CLK_CTRL, 0x148)
FIELD(VERSAL2_SPI1_REF_CLK_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_SPI1_REF_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_SPI1_REF_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_CAN0_REF_2X_CTRL, 0x14c)
FIELD(VERSAL2_CAN0_REF_2X_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_CAN0_REF_2X_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_CAN0_REF_2X_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_CAN1_REF_2X_CTRL, 0x150)
FIELD(VERSAL2_CAN1_REF_2X_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_CAN1_REF_2X_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_CAN1_REF_2X_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_CAN2_REF_2X_CTRL, 0x154)
FIELD(VERSAL2_CAN2_REF_2X_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_CAN2_REF_2X_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_CAN2_REF_2X_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_CAN3_REF_2X_CTRL, 0x158)
FIELD(VERSAL2_CAN3_REF_2X_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_CAN3_REF_2X_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_CAN3_REF_2X_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_I3C0_REF_CTRL, 0x15c)
FIELD(VERSAL2_I3C0_REF_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_I3C0_REF_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_I3C0_REF_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_I3C1_REF_CTRL, 0x160)
FIELD(VERSAL2_I3C1_REF_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_I3C1_REF_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_I3C1_REF_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_I3C2_REF_CTRL, 0x164)
FIELD(VERSAL2_I3C2_REF_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_I3C2_REF_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_I3C2_REF_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_I3C3_REF_CTRL, 0x168)
FIELD(VERSAL2_I3C3_REF_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_I3C3_REF_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_I3C3_REF_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_I3C4_REF_CTRL, 0x16c)
FIELD(VERSAL2_I3C4_REF_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_I3C4_REF_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_I3C4_REF_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_I3C5_REF_CTRL, 0x170)
FIELD(VERSAL2_I3C5_REF_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_I3C5_REF_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_I3C5_REF_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_I3C6_REF_CTRL, 0x174)
FIELD(VERSAL2_I3C6_REF_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_I3C6_REF_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_I3C6_REF_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_I3C7_REF_CTRL, 0x178)
FIELD(VERSAL2_I3C7_REF_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_I3C7_REF_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_I3C7_REF_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_DBG_LPX_CTRL, 0x17c)
FIELD(VERSAL2_DBG_LPX_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_DBG_LPX_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_DBG_LPX_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_TIMESTAMP_REF_CTRL, 0x180)
FIELD(VERSAL2_TIMESTAMP_REF_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_TIMESTAMP_REF_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_SAFETY_CHK, 0x184)
REG32(VERSAL2_ASU_CLK_CTRL, 0x188)
FIELD(VERSAL2_ASU_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_ASU_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_DBG_TSTMP_CLK_CTRL, 0x18c)
FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_MMI_TOPSW_CLK_CTRL, 0x190)
FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, CLKACT, 25, 1)
FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_WWDT_PLL_CLK_CTRL, 0x194)
FIELD(VERSAL2_WWDT_PLL_CLK_CTRL, DIVISOR0, 8, 10)
FIELD(VERSAL2_WWDT_PLL_CLK_CTRL, SRCSEL, 0, 3)
REG32(VERSAL2_RCLK_CTRL, 0x1a0)
FIELD(VERSAL2_RCLK_CTRL, CLKACT, 8, 6)
FIELD(VERSAL2_RCLK_CTRL, SELECT, 0, 6)
REG32(VERSAL2_RST_RPU_A, 0x310)
FIELD(VERSAL2_RST_RPU_A, TOPRESET, 16, 1)
FIELD(VERSAL2_RST_RPU_A, CORE1_POR, 9, 1)
FIELD(VERSAL2_RST_RPU_A, CORE0_POR, 8, 1)
FIELD(VERSAL2_RST_RPU_A, CORE1_RESET, 1, 1)
FIELD(VERSAL2_RST_RPU_A, CORE0_RESET, 0, 1)
REG32(VERSAL2_RST_RPU_B, 0x314)
FIELD(VERSAL2_RST_RPU_B, TOPRESET, 16, 1)
FIELD(VERSAL2_RST_RPU_B, CORE1_POR, 9, 1)
FIELD(VERSAL2_RST_RPU_B, CORE0_POR, 8, 1)
FIELD(VERSAL2_RST_RPU_B, CORE1_RESET, 1, 1)
FIELD(VERSAL2_RST_RPU_B, CORE0_RESET, 0, 1)
REG32(VERSAL2_RST_RPU_C, 0x318)
FIELD(VERSAL2_RST_RPU_C, TOPRESET, 16, 1)
FIELD(VERSAL2_RST_RPU_C, CORE1_POR, 9, 1)
FIELD(VERSAL2_RST_RPU_C, CORE0_POR, 8, 1)
FIELD(VERSAL2_RST_RPU_C, CORE1_RESET, 1, 1)
FIELD(VERSAL2_RST_RPU_C, CORE0_RESET, 0, 1)
REG32(VERSAL2_RST_RPU_D, 0x31c)
FIELD(VERSAL2_RST_RPU_D, TOPRESET, 16, 1)
FIELD(VERSAL2_RST_RPU_D, CORE1_POR, 9, 1)
FIELD(VERSAL2_RST_RPU_D, CORE0_POR, 8, 1)
FIELD(VERSAL2_RST_RPU_D, CORE1_RESET, 1, 1)
FIELD(VERSAL2_RST_RPU_D, CORE0_RESET, 0, 1)
REG32(VERSAL2_RST_RPU_E, 0x320)
FIELD(VERSAL2_RST_RPU_E, TOPRESET, 16, 1)
FIELD(VERSAL2_RST_RPU_E, CORE1_POR, 9, 1)
FIELD(VERSAL2_RST_RPU_E, CORE0_POR, 8, 1)
FIELD(VERSAL2_RST_RPU_E, CORE1_RESET, 1, 1)
FIELD(VERSAL2_RST_RPU_E, CORE0_RESET, 0, 1)
REG32(VERSAL2_RST_RPU_GD_0, 0x324)
FIELD(VERSAL2_RST_RPU_GD_0, RESET, 1, 1)
FIELD(VERSAL2_RST_RPU_GD_0, TOP_RESET, 0, 1)
REG32(VERSAL2_RST_RPU_GD_1, 0x328)
FIELD(VERSAL2_RST_RPU_GD_1, RESET, 1, 1)
FIELD(VERSAL2_RST_RPU_GD_1, TOP_RESET, 0, 1)
REG32(VERSAL2_RST_ASU_GD, 0x32c)
FIELD(VERSAL2_RST_ASU_GD, RESET, 1, 1)
FIELD(VERSAL2_RST_ASU_GD, TOP_RESET, 0, 1)
REG32(VERSAL2_RST_ADMA, 0x334)
FIELD(VERSAL2_RST_ADMA, RESET, 0, 1)
REG32(VERSAL2_RST_SDMA, 0x338)
FIELD(VERSAL2_RST_SDMA, RESET, 0, 1)
REG32(VERSAL2_RST_GEM0, 0x33c)
FIELD(VERSAL2_RST_GEM0, RESET, 0, 1)
REG32(VERSAL2_RST_GEM1, 0x340)
FIELD(VERSAL2_RST_GEM1, RESET, 0, 1)
REG32(VERSAL2_RST_USB0, 0x348)
FIELD(VERSAL2_RST_USB0, RESET, 0, 1)
REG32(VERSAL2_RST_USB1, 0x34c)
FIELD(VERSAL2_RST_USB1, RESET, 0, 1)
REG32(VERSAL2_RST_UART0, 0x350)
FIELD(VERSAL2_RST_UART0, RESET, 0, 1)
REG32(VERSAL2_RST_UART1, 0x354)
FIELD(VERSAL2_RST_UART1, RESET, 0, 1)
REG32(VERSAL2_RST_SPI0, 0x358)
FIELD(VERSAL2_RST_SPI0, RESET, 0, 1)
REG32(VERSAL2_RST_SPI1, 0x35c)
FIELD(VERSAL2_RST_SPI1, RESET, 0, 1)
REG32(VERSAL2_RST_CAN0, 0x360)
FIELD(VERSAL2_RST_CAN0, RESET, 0, 1)
REG32(VERSAL2_RST_CAN1, 0x364)
FIELD(VERSAL2_RST_CAN1, RESET, 0, 1)
REG32(VERSAL2_RST_CAN2, 0x368)
FIELD(VERSAL2_RST_CAN2, RESET, 0, 1)
REG32(VERSAL2_RST_CAN3, 0x36c)
FIELD(VERSAL2_RST_CAN3, RESET, 0, 1)
REG32(VERSAL2_RST_I3C0, 0x374)
FIELD(VERSAL2_RST_I3C0, RESET, 0, 1)
REG32(VERSAL2_RST_I3C1, 0x378)
FIELD(VERSAL2_RST_I3C1, RESET, 0, 1)
REG32(VERSAL2_RST_I3C2, 0x37c)
FIELD(VERSAL2_RST_I3C2, RESET, 0, 1)
REG32(VERSAL2_RST_I3C3, 0x380)
FIELD(VERSAL2_RST_I3C3, RESET, 0, 1)
REG32(VERSAL2_RST_I3C4, 0x384)
FIELD(VERSAL2_RST_I3C4, RESET, 0, 1)
REG32(VERSAL2_RST_I3C5, 0x388)
FIELD(VERSAL2_RST_I3C5, RESET, 0, 1)
REG32(VERSAL2_RST_I3C6, 0x38c)
FIELD(VERSAL2_RST_I3C6, RESET, 0, 1)
REG32(VERSAL2_RST_I3C7, 0x390)
FIELD(VERSAL2_RST_I3C7, RESET, 0, 1)
REG32(VERSAL2_RST_DBG_LPX, 0x398)
FIELD(VERSAL2_RST_DBG_LPX, RESET_HSDP, 1, 1)
FIELD(VERSAL2_RST_DBG_LPX, RESET, 0, 1)
REG32(VERSAL2_RST_GPIO, 0x39c)
FIELD(VERSAL2_RST_GPIO, RESET, 0, 1)
REG32(VERSAL2_RST_TTC, 0x3a0)
FIELD(VERSAL2_RST_TTC, TTC7_RESET, 7, 1)
FIELD(VERSAL2_RST_TTC, TTC6_RESET, 6, 1)
FIELD(VERSAL2_RST_TTC, TTC5_RESET, 5, 1)
FIELD(VERSAL2_RST_TTC, TTC4_RESET, 4, 1)
FIELD(VERSAL2_RST_TTC, TTC3_RESET, 3, 1)
FIELD(VERSAL2_RST_TTC, TTC2_RESET, 2, 1)
FIELD(VERSAL2_RST_TTC, TTC1_RESET, 1, 1)
FIELD(VERSAL2_RST_TTC, TTC0_RESET, 0, 1)
REG32(VERSAL2_RST_TIMESTAMP, 0x3a4)
FIELD(VERSAL2_RST_TIMESTAMP, RESET, 0, 1)
REG32(VERSAL2_RST_SWDT0, 0x3a8)
FIELD(VERSAL2_RST_SWDT0, RESET, 0, 1)
REG32(VERSAL2_RST_SWDT1, 0x3ac)
FIELD(VERSAL2_RST_SWDT1, RESET, 0, 1)
REG32(VERSAL2_RST_SWDT2, 0x3b0)
FIELD(VERSAL2_RST_SWDT2, RESET, 0, 1)
REG32(VERSAL2_RST_SWDT3, 0x3b4)
FIELD(VERSAL2_RST_SWDT3, RESET, 0, 1)
REG32(VERSAL2_RST_SWDT4, 0x3b8)
FIELD(VERSAL2_RST_SWDT4, RESET, 0, 1)
REG32(VERSAL2_RST_IPI, 0x3bc)
FIELD(VERSAL2_RST_IPI, RESET, 0, 1)
REG32(VERSAL2_RST_SYSMON, 0x3c0)
FIELD(VERSAL2_RST_SYSMON, CFG_RST, 0, 1)
REG32(VERSAL2_ASU_MB_RST_MODE, 0x3c4)
FIELD(VERSAL2_ASU_MB_RST_MODE, WAKEUP, 2, 1)
FIELD(VERSAL2_ASU_MB_RST_MODE, RST_MODE, 0, 2)
REG32(VERSAL2_FPX_TOPSW_MUX_CTRL, 0x3c8)
FIELD(VERSAL2_FPX_TOPSW_MUX_CTRL, SELECT, 0, 1)
REG32(VERSAL2_RST_FPX, 0x3d0)
FIELD(VERSAL2_RST_FPX, SRST, 1, 1)
FIELD(VERSAL2_RST_FPX, POR, 0, 1)
REG32(VERSAL2_RST_MMI, 0x3d4)
FIELD(VERSAL2_RST_MMI, POR, 0, 1)
REG32(VERSAL2_RST_OCM, 0x3d8)
FIELD(VERSAL2_RST_OCM, RESET_OCM3, 3, 1)
FIELD(VERSAL2_RST_OCM, RESET_OCM2, 2, 1)
FIELD(VERSAL2_RST_OCM, RESET_OCM1, 1, 1)
FIELD(VERSAL2_RST_OCM, RESET_OCM0, 0, 1)
#define VERSAL2_CRL_R_MAX (R_VERSAL2_RST_OCM + 1)
struct XlnxVersalCRLBase {
SysBusDevice parent_obj;
@ -249,11 +559,30 @@ struct XlnxVersalCRL {
RegisterInfo regs_info[CRL_R_MAX];
};
struct XlnxVersal2CRL {
XlnxVersalCRLBase parent_obj;
struct {
DeviceState *rpu[10];
DeviceState *adma[8];
DeviceState *sdma[8];
DeviceState *uart[2];
DeviceState *gem[2];
DeviceState *usb[2];
DeviceState *can[4];
} cfg;
RegisterInfo regs_info[VERSAL2_CRL_R_MAX];
uint32_t regs[VERSAL2_CRL_R_MAX];
};
static inline const char *xlnx_versal_crl_class_name(VersalVersion ver)
{
switch (ver) {
case VERSAL_VER_VERSAL:
return TYPE_XLNX_VERSAL_CRL;
case VERSAL_VER_VERSAL2:
return TYPE_XLNX_VERSAL2_CRL;
default:
g_assert_not_reached();
}

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