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We have 115 direct inclusions of "system/memory.h", and 91 headers in include/ use it: hundreds of files have to process it. However only one single header really uses the MemoryRegionCache API: "hw/virtio/virtio-access.h". Split it out to a new header, avoiding processing unused inlined functions hundreds of times. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260109165058.59144-6-philmd@linaro.org>pull/316/head
Philippe Mathieu-Daudé
7 months ago
5 changed files with 213 additions and 185 deletions
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/*
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* Physical memory management API |
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* |
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* Copyright 2011 Red Hat, Inc. and/or its affiliates |
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* |
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* Authors: |
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* Avi Kivity <avi@redhat.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0-or-later |
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*/ |
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#ifndef SYSTEM_MEMORY_CACHED_H |
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#define SYSTEM_MEMORY_CACHED_H |
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#include "exec/hwaddr.h" |
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#include "system/memory.h" |
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struct MemoryRegionCache { |
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uint8_t *ptr; |
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hwaddr xlat; |
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hwaddr len; |
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FlatView *fv; |
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MemoryRegionSection mrs; |
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bool is_write; |
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}; |
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/**
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* address_space_ld*_cached: load from a cached #MemoryRegion |
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* address_space_st*_cached: store into a cached #MemoryRegion |
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* |
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* These functions perform a load or store of the byte, word, |
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* longword or quad to the specified address. The address is |
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* a physical address in the AddressSpace, but it must lie within |
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* a #MemoryRegion that was mapped with address_space_cache_init. |
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* |
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* The _le suffixed functions treat the data as little endian; |
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* _be indicates big endian; no suffix indicates "same endianness |
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* as guest CPU". |
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* |
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* The "guest CPU endianness" accessors are deprecated for use outside |
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* target-* code; devices should be CPU-agnostic and use either the LE |
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* or the BE accessors. |
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* |
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* @cache: previously initialized #MemoryRegionCache to be accessed |
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* @addr: address within the address space |
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* @val: data value, for stores |
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* @attrs: memory transaction attributes |
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* @result: location to write the success/failure of the transaction; |
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* if NULL, this information is discarded |
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*/ |
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#define SUFFIX _cached_slow |
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#define ARG1 cache |
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#define ARG1_DECL MemoryRegionCache *cache |
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#include "system/memory_ldst.h.inc" |
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/* Inline fast path for direct RAM access. */ |
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static inline |
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uint8_t address_space_ldub_cached(MemoryRegionCache *cache, hwaddr addr, |
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MemTxAttrs attrs, MemTxResult *result) |
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{ |
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assert(addr < cache->len); |
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if (likely(cache->ptr)) { |
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return ldub_p(cache->ptr + addr); |
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} else { |
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return address_space_ldub_cached_slow(cache, addr, attrs, result); |
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} |
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} |
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static inline |
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void address_space_stb_cached(MemoryRegionCache *cache, |
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hwaddr addr, uint8_t val, |
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MemTxAttrs attrs, MemTxResult *result) |
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{ |
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assert(addr < cache->len); |
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if (likely(cache->ptr)) { |
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stb_p(cache->ptr + addr, val); |
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} else { |
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address_space_stb_cached_slow(cache, addr, val, attrs, result); |
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} |
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} |
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#define ENDIANNESS |
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#include "system/memory_ldst_cached.h.inc" |
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#define ENDIANNESS _le |
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#include "system/memory_ldst_cached.h.inc" |
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#define ENDIANNESS _be |
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#include "system/memory_ldst_cached.h.inc" |
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#define SUFFIX _cached |
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#define ARG1 cache |
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#define ARG1_DECL MemoryRegionCache *cache |
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#include "system/memory_ldst_phys.h.inc" |
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/**
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* address_space_cache_init: prepare for repeated access to a physical |
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* memory region |
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* |
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* @cache: #MemoryRegionCache to be filled |
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* @as: #AddressSpace to be accessed |
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* @addr: address within that address space |
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* @len: length of buffer |
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* @is_write: indicates the transfer direction |
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* |
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* Will only work with RAM, and may map a subset of the requested range by |
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* returning a value that is less than @len. On failure, return a negative |
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* errno value. |
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* |
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* Because it only works with RAM, this function can be used for |
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* read-modify-write operations. In this case, is_write should be %true. |
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* |
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* Note that addresses passed to the address_space_*_cached functions |
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* are relative to @addr. |
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*/ |
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int64_t address_space_cache_init(MemoryRegionCache *cache, |
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AddressSpace *as, |
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hwaddr addr, |
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hwaddr len, |
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bool is_write); |
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/**
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* address_space_cache_init_empty: Initialize empty #MemoryRegionCache |
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* |
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* @cache: The #MemoryRegionCache to operate on. |
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* |
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* Initializes #MemoryRegionCache structure without memory region attached. |
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* Cache initialized this way can only be safely destroyed, but not used. |
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*/ |
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static inline void address_space_cache_init_empty(MemoryRegionCache *cache) |
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{ |
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cache->mrs.mr = NULL; |
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/* There is no real need to initialize fv, but it makes Coverity happy. */ |
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cache->fv = NULL; |
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} |
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/**
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* address_space_cache_invalidate: complete a write to a #MemoryRegionCache |
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* |
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* @cache: The #MemoryRegionCache to operate on. |
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* @addr: The first physical address that was written, relative to the |
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* address that was passed to @address_space_cache_init. |
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* @access_len: The number of bytes that were written starting at @addr. |
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*/ |
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void address_space_cache_invalidate(MemoryRegionCache *cache, |
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hwaddr addr, |
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hwaddr access_len); |
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/**
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* address_space_cache_destroy: free a #MemoryRegionCache |
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* |
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* @cache: The #MemoryRegionCache whose memory should be released. |
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*/ |
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void address_space_cache_destroy(MemoryRegionCache *cache); |
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/*
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* Internal functions, part of the implementation of address_space_read_cached |
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* and address_space_write_cached. |
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*/ |
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MemTxResult address_space_read_cached_slow(MemoryRegionCache *cache, |
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hwaddr addr, void *buf, hwaddr len); |
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MemTxResult address_space_write_cached_slow(MemoryRegionCache *cache, |
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hwaddr addr, const void *buf, |
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hwaddr len); |
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/**
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* address_space_read_cached: read from a cached RAM region |
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* |
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* @cache: Cached region to be addressed |
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* @addr: address relative to the base of the RAM region |
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* @buf: buffer with the data transferred |
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* @len: length of the data transferred |
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*/ |
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static inline MemTxResult |
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address_space_read_cached(MemoryRegionCache *cache, hwaddr addr, |
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void *buf, hwaddr len) |
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{ |
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assert(addr < cache->len && len <= cache->len - addr); |
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fuzz_dma_read_cb(cache->xlat + addr, len, cache->mrs.mr); |
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if (likely(cache->ptr)) { |
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memcpy(buf, cache->ptr + addr, len); |
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return MEMTX_OK; |
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} else { |
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return address_space_read_cached_slow(cache, addr, buf, len); |
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} |
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} |
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/**
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* address_space_write_cached: write to a cached RAM region |
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* |
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* @cache: Cached region to be addressed |
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* @addr: address relative to the base of the RAM region |
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* @buf: buffer with the data transferred |
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* @len: length of the data transferred |
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*/ |
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static inline MemTxResult |
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address_space_write_cached(MemoryRegionCache *cache, hwaddr addr, |
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const void *buf, hwaddr len) |
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{ |
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assert(addr < cache->len && len <= cache->len - addr); |
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if (likely(cache->ptr)) { |
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memcpy(cache->ptr + addr, buf, len); |
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return MEMTX_OK; |
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} else { |
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return address_space_write_cached_slow(cache, addr, buf, len); |
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} |
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} |
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#endif |
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