libgloss: bfin: add clear_cache_range support (for gcc)

libgloss/ChangeLog

@@ -1,3 +1,11 @@
+2011-12-18  Mike Frysinger  <vapier@gentoo.org>
+
+	* bfin/clear_cache_range.c: New file.
+	* bfin/Makefile.in (SIM_OBJS): Add clear_cache_range.o.
+	(BOARD_OBJS): Likewise.
+	(BOARD_BSP): Set to libbfinbsp.a.
+	(${BOARD_BSP}): New rule.
+
 2011-12-15  Konrad Eisele <konrad@gaisler.com>
 
 	* configure.in: Add SPARC LEON support.

libgloss/bfin/Makefile.in

@@ -55,7 +55,7 @@ SIM_SCRIPTS	=
 SIM_LDFLAGS	=
 SIM_BSP		= libsim.a
 SIM_CRT0	= crt0.o
-SIM_OBJS	= syscalls.o
+SIM_OBJS	= syscalls.o clear_cache_range.o
 SIM_TEST	= sim-test
 SIM_INSTALL	= install-sim
 
@@ -71,10 +71,10 @@ BOARD_SCRIPTS	= bfin-common-sc.ld  bfin-common-mc.ld \
 	bf561.ld bf561a.ld bf561b.ld bf561m.ld \
 	bf592.ld
 BOARD_LDFLAGS	=
-BOARD_BSP	= # We actually use libnosys.a
+BOARD_BSP	= libbfinbsp.a
 BOARD_CRT0S	= basiccrt.o basiccrts.o
 BOARD_CRT0S	+= basiccrt561.o basiccrt561s.o basiccrt561b.o
-BOARD_OBJS	=
+BOARD_OBJS	= clear_cache_range.o
 BOARD_TEST	=
 BOARD_INSTALL	= install-board
 
@@ -91,6 +91,10 @@ all: ${SIM_CRT0} ${SIM_BSP} ${BOARD_CRT0S} ${BOARD_BSP}
 #
 # here's where we build the board support packages for each target
 #
+${BOARD_BSP}: ${OBJS} ${BOARD_OBJS}
+	${AR} ${ARFLAGS} $@ $^
+	${RANLIB} $@
+
 ${SIM_BSP}: ${OBJS} ${SIM_OBJS}
 	${AR} ${ARFLAGS} ${SIM_BSP} ${SIM_OBJS} ${OBJS}
 	${RANLIB} ${SIM_BSP}

libgloss/bfin/clear_cache_range.c

@@ -0,0 +1,33 @@
+/*
+ * C library support files for the Blackfin processor
+ *
+ * Copyright (C) 2010 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/* This is a callback which gcc itself wants to flush jump tables.
+
+   Map it into L1 Text because of anomalies 05-00-0312 and 05-00-0419.  */
+
+__attribute__ ((l1_text))
+void __clear_cache_range (char *beg, char *end)
+{
+  char *ptr = beg;
+  do {
+    __asm__ __volatile__ ("FLUSH [%0++];" : "+a" (ptr) : : "memory");
+  } while (ptr <= end);
+  ptr = beg;
+  __asm__ __volatile__ ("SSYNC;");
+  do {
+    __asm__ __volatile__ ("IFLUSH [%0++];" : "+a" (ptr) : : "memory");
+  } while (ptr <= end);
+}