riscv/musl - musl - Gitea: Git with a cup of tea

History

Rich Felker 92637bb0d8 prevent reordering of or1k and powerpc thread pointer loads other archs use asm for the thread pointer load, so making that asm volatile is sufficient to inform the compiler that it has a "side effect" (crashing or giving the wrong result if the thread pointer was not yet initialized) that prevents reordering. however, powerpc and or1k have dedicated general purpose registers for the thread pointer and did not need to use any asm to access it; instead, "local register variables with a specified register" were used. however, there is no specification for ordering constraints on this type of usage, and presumably use of the thread pointer could be reordered across its initialization. to impose an ordering, I have added empty volatile asm blocks that produce the "local register variable with a specified register" as an output constraint.		11 years ago
..
aarch64	fix namespace violations in aarch64/bits/termios.h	11 years ago
arm	mark arm thread-pointer-loading inline asm as volatile	11 years ago
i386	introduce new symbol-lookup-free rcrt1/dlstart stage chaining	11 years ago
microblaze	new dlstart stage-2 chaining for microblaze	11 years ago
mips	add comment documenting hard-coded opcode for reading mips thread pointer	11 years ago
or1k	prevent reordering of or1k and powerpc thread pointer loads	11 years ago
powerpc	prevent reordering of or1k and powerpc thread pointer loads	11 years ago
sh	fix signal return for sh/fdpic	11 years ago
x32	new dlstart stage-2 chaining for x86_64 and x32	11 years ago
x86_64	new dlstart stage-2 chaining for x86_64 and x32	11 years ago