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musl/arch/riscv64

History

Palmer Dabbelt 7d5c5706a0 correct the operand specifiers in the riscv64 CAS routines The operand sepcifiers in a_cas and a_cas_p for riscv64 were incorrect: there's a backwards branch in the routine, so despite tmp being written at the end of the assembly fragment it cannot be allocated in one of the input registers because the input values may be needed for another trip around the loop. For code that follows the guaranteed forward progress requirements, the backwards branch is rarely taken: SiFive's hardware only fails a store conditional on execptional cases (ie, instruction cache misses inside the loop), and until recently a bug in QEMU allowed back-to-back store conditionals to succeed. The bug has been fixed in the latest QEMU release, but it turns out that the fix caused this latent bug in musl to manifest.		7 years ago
..
bits	add new syscall numbers from linux v5.2	7 years ago
atomic_arch.h	correct the operand specifiers in the riscv64 CAS routines	7 years ago
crt_arch.h	add riscv64 architecture support	7 years ago
kstat.h	decouple struct stat from kernel type	7 years ago
pthread_arch.h	add riscv64 architecture support	7 years ago
reloc.h	add riscv64 architecture support	7 years ago
syscall_arch.h	move IPC_64 from public bits/ipc.h to syscall_arch.h	7 years ago