3 Commits (f0eb2e77b2132a88e2f00d8e06ffa7638c40b4bc)

Author SHA1 Message Date
Rich Felker f0eb2e77b2 use register constraint instead of memory operand for riscv64 atomics 7 years ago
Rich Felker 2dcbeabd91 fix riscv64 atomic asm constraints 7 years ago
Rich Felker 0a48860c27 add riscv64 architecture support 7 years ago