Tree: 6f3ead0ae1

master

rs-1.0

v0.5.0

v0.5.9

v0.6.0

v0.7.0

v0.7.1

v0.7.10

v0.7.11

v0.7.12

v0.7.5

v0.7.6

v0.7.7

v0.7.8

v0.7.9

v0.8.0

v0.8.1

v0.8.10

v0.8.2

v0.8.3

v0.8.4

v0.8.5

v0.8.6

v0.8.7

v0.8.8

v0.8.9

v0.9.0

v0.9.1

v0.9.10

v0.9.11

v0.9.12

v0.9.13

v0.9.14

v0.9.15

v0.9.2

v0.9.3

v0.9.4

v0.9.5

v0.9.6

v0.9.7

v0.9.8

v0.9.9

v1.0.0

v1.0.1

v1.0.2

v1.0.3

v1.0.4

v1.0.5

v1.1.0

v1.1.1

v1.1.10

v1.1.11

v1.1.12

v1.1.13

v1.1.14

v1.1.15

v1.1.16

v1.1.17

v1.1.18

v1.1.19

v1.1.2

v1.1.20

v1.1.21

v1.1.22

v1.1.23

v1.1.24

v1.1.3

v1.1.4

v1.1.5

v1.1.6

v1.1.7

v1.1.8

v1.1.9

v1.2.0

v1.2.1

v1.2.2

v1.2.3

v1.2.4

v1.2.5

v1.2.6

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from '6f3ead0ae1'

${ noResults }

Commit Graph

1 Commits (6f3ead0ae16deb9f0004b275e29a276c9712ee3c)

Author	SHA1	Message	Date
Stefan Kristiansson	200d15479c	add or1k (OpenRISC 1000) architecture port With the exception of a fenv implementation, the port is fully featured. The port has been tested in or1ksim, the golden reference functional simulator for OpenRISC 1000. It passes all libc-test tests (except the math tests that requires a fenv implementation). The port assumes an or1k implementation that has support for atomic instructions (l.lwa/l.swa). Although it passes all the libc-test tests, the port is still in an experimental state, and has yet experienced very little 'real-world' use.	12 years ago
Rich Felker	0004ea613a	fix breakage from introducing bits header for sys/io.h apparently some other archs have sys/io.h and should not break just because they don't have the x86 port io functions. provide a blank bits/io.h everywhere for now.	14 years ago
Rich Felker	83023d1b50	PIE support for i386	14 years ago
Rich Felker	0b44a0315b	initial check-in, version 0.5.0	15 years ago