mirror of https://git.musl-libc.org/git/musl
Browse Source
the braf instruction's destination register is an offset from the address of the braf instruction plus 4 (or equivalently, the address of the next instruction after the delay slot). the code for dlsym was incorrectly computing the offset to pass using the address of the delay slot itself. in other places, a label was placed after the delay slot, but I find this confusing. putting the label on the branch instruction itself, and manually adding 4, makes it more clear which branch the offset in the constant pool goes with.master
1 changed files with 3 additions and 3 deletions
Loading…
Reference in new issue