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add-fakeroots-dir

arc-20081103-branch

arc-insight_6_8-branch

binutils-2_10-branch

binutils-2_11-branch

binutils-2_12-branch

binutils-2_13-branch

binutils-2_14-branch

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binutils-2_16-branch

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binutils-2_22-branch

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binutils-2_41-release-point

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binutils-csl-arm-2005q1-branch

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carlton_dictionary-branch

cgen-1_1-branch

cr-0x5f1

csl-arm-20050325-branch

cygnus

cygwin-64bit-branch

cygwin-64bit-premerge-branch

dberlin-typesystem-branch

dje-cgen-play1-branch

drow-cplus-branch

drow-reverse-20070409-branch

drow_intercu-20040221-branch

ezannoni_pie-20030916-branch

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gdb-csl-20060226-branch

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users/ARM/efi-aarch64-support-binutils

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users/aburgess/bp-inferior-calls

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users/aburgess/try-mips-disasm-styling

users/ahajkova/try-frob

users/ahayward/variable_sve

users/ahayward/variable_sve2

added-to-binutils

arc-20081103-branchpoint

arc-insight_6_8-branchpoint

arc-sim-20090309

binu_ss_19990502

binu_ss_19990602

binu_ss_19990721

binutils-2_10

binutils-2_10-branchpoint

binutils-2_10_1

binutils-2_11

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binutils-2_12

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binutils-2_34

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binutils-2_35_1

binutils-2_35_2

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binutils-2_36_1

binutils-2_37

binutils-2_38

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binutils-csl-renesas-4_1-8

binutils-csl-renesas-4_1-9

binutils-csl-sourcerygxx-3_4_4-17

binutils-csl-sourcerygxx-3_4_4-19

binutils-csl-sourcerygxx-3_4_4-21

binutils-csl-sourcerygxx-3_4_4-25

binutils-csl-sourcerygxx-3_4_4-32

binutils-csl-sourcerygxx-4_1-12

binutils-csl-sourcerygxx-4_1-13

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binutils-csl-sourcerygxx-4_1-21

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binutils-csl-sourcerygxx-4_1-23

binutils-csl-sourcerygxx-4_1-24

binutils-csl-sourcerygxx-4_1-25

binutils-csl-sourcerygxx-4_1-26

binutils-csl-sourcerygxx-4_1-27

binutils-csl-sourcerygxx-4_1-28

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binutils-csl-sourcerygxx-4_1-8

binutils-csl-sourcerygxx-4_1-9

binutils-csl-wrs-linux-3_4_4-20

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binutils-csl-wrs-linux-3_4_4-22

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binutils_latest_snapshot

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binutils-gdb/sim

History

Carlo Bramini 69b1ffdb01 sim/aarch64: Fix register ordering bug in blr (PR sim/25318) A comment in the implementation of blr says: /* The pseudo code in the spec says we update LR before fetching. the value from the rn. */ With 'rn' being the register holding the destination address. This may have been true at one point, but the ISA manual now clearly shows the destination register being read before the link register is written. This commit updates the implementation of blr to match. sim/aarch64/ChangeLog: PR sim/25318 * simulator.c (blr): Read destination register before calling aarch64_save_LR. Change-Id: Icb1c556064e3d9c807ac28440475caa205ab1064		6 years ago
..
aarch64	sim/aarch64: Fix register ordering bug in blr (PR sim/25318)	6 years ago
arm	Fix spelling errors	6 years ago
avr	Update copyright year range in all GDB files.	6 years ago
bfin	Update copyright year range in all GDB files.	6 years ago
common	sim: add some stdlib.h includes	6 years ago
cr16	Update copyright year range in all GDB files.	6 years ago
cris	Update copyright year range in all GDB files.	6 years ago
d10v	Update copyright year range in all GDB files.	6 years ago
erc32	Update copyright year range in all GDB files.	6 years ago
frv	Update copyright year range in all GDB files.	6 years ago
ft32	Update copyright year range in all GDB files.	6 years ago
h8300	Update copyright year range in all GDB files.	6 years ago
igen	Update copyright year range in all GDB files.	6 years ago
iq2000	Update copyright year range in all GDB files.	6 years ago
lm32	Update copyright year range in all GDB files.	6 years ago
m32c	Update copyright year range in all GDB files.	6 years ago
m32r	Update copyright year range in all GDB files.	6 years ago
m68hc11	Update copyright year range in all GDB files.	6 years ago
mcore	Update copyright year range in all GDB files.	6 years ago
microblaze	Update copyright year range in all GDB files.	6 years ago
mips	Update copyright year range in all GDB files.	6 years ago
mn10300	Update copyright year range in all GDB files.	6 years ago
moxie	Update copyright year range in all GDB files.	6 years ago
msp430	MSP430: Fix simulator execution of RRUX instruction	6 years ago
or1k	Update copyright year range in all GDB files.	6 years ago
ppc	Update copyright year range in all GDB files.	6 years ago
pru	Update copyright year range in all GDB files.	6 years ago
rl78	Update copyright year range in all GDB files.	6 years ago
rx	Update copyright year range in all GDB files.	6 years ago
sh	Update copyright year range in all GDB files.	6 years ago
sh64	Update copyright year range in all GDB files.	6 years ago
testsuite	MSP430: Fix simulator execution of RRUX instruction	6 years ago
v850	Update copyright year range in all GDB files.	6 years ago
.gitignore	sim: drop common/cconfig.h in favor of a single config.h	10 years ago
ChangeLog	Add install-strip to sim/	6 years ago
MAINTAINERS	sim: Add PRU simulator port	7 years ago
Makefile.in	Update copyright year range in all GDB files.	6 years ago
README-HACKING	sim: punt WITH_DEVICES & tconfig.h support	10 years ago
configure	sim: Add PRU simulator port	7 years ago
configure.ac	Bump to autoconf 2.69 and automake 1.15.1	8 years ago
configure.tgt	sim: Add PRU simulator port	7 years ago