binutils-gdb

History

Maciej W. Rozycki 9204ccd4b1 MIPS/opcodes: Do not use CP0 register names for control registers The CP0 control register set has never been defined, however encodings for the CFC0 and CTC0 instructions remained available for implementers up until the MIPS32 ISA declared them invalid and causing the Reserved Instruction exception[1]. Therefore we handle them for both assembly and disassembly, however in the latter case the names of CP0 registers from the regular set are incorrectly printed if named registers are requested. This is because we do not define separate operand classes for coprocessor regular and control registers respectively, which means the disassembler has no way to tell the two cases apart. Consequently nonsensical disassembly is produced like: cfc0 v0,c0_random Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 instructions[2] although it failed to document them in the relevant opcode table until MIPSr6 only. Correct the issue then by defining a new register class, OP_REG_CONTROL, and corresponding operand codes, `g' and `y' for the two positions in the machine instruction a control register operand can take. Adjust the test cases affected accordingly. While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries with each other so that they come in the alphabetical order. References: [1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 195, 216 include/ * opcode/mips.h: Document `g' and `y' operand codes. (mips_reg_operand_type): Add OP_REG_CONTROL enumeration constant. gas/ * tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case. (macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' operand code. opcodes/ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register handling code over to... <OP_REG_CONTROL>: ... this new case. * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries replacing the `G' operand code with `g'. Update "cftc1" and "cftc2" entries replacing the `E' operand code with `y'. * micromips-opc.c (decode_micromips_operand) <'g'>: New case. (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" entries replacing the `G' operand code with `g'. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 operand disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.		5 years ago
..
global-local-symtab-final-n32.d	MIPS: Make the IRIX naming of local section symbols consistent	6 years ago
global-local-symtab-final-n64.d	MIPS: Make the IRIX naming of local section symbols consistent	6 years ago
global-local-symtab-final-o32.d	MIPS: Make the IRIX naming of local section symbols consistent	6 years ago
global-local-symtab-n32.d	MIPS/LD: Set symtab's `sh_info' correctly for IRIX emulations	6 years ago
global-local-symtab-n32t.d	MIPS/LD: Set symtab's `sh_info' correctly for IRIX emulations	6 years ago
global-local-symtab-n64.d	MIPS/LD: Set symtab's `sh_info' correctly for IRIX emulations	6 years ago
global-local-symtab-o32.d	MIPS/LD: Set symtab's `sh_info' correctly for IRIX emulations	6 years ago
global-local-symtab-o32t.d	MIPS/LD: Set symtab's `sh_info' correctly for IRIX emulations	6 years ago
global-local-symtab-sort-n32.d	MIPS: Make the IRIX naming of local section symbols consistent	6 years ago
global-local-symtab-sort-n32t.d	MIPS: Make the IRIX naming of local section symbols consistent	6 years ago
global-local-symtab-sort-n64.d	MIPS: Make the IRIX naming of local section symbols consistent	6 years ago
global-local-symtab-sort-n64t.d	Adjust readelf's output so that section symbols without a name as shown with their section name.	5 years ago
global-local-symtab-sort-o32.d	MIPS: Make the IRIX naming of local section symbols consistent	6 years ago
global-local-symtab-sort-o32t.d	Adjust readelf's output so that section symbols without a name as shown with their section name.	5 years ago
mips-ase-1.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips-ase-1.s	MIPS/opcodes: Also set disassembler's ASE flags from ELF structures	9 years ago
mips-ase-2.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips-ase-2.s	MIPS/opcodes: Also set disassembler's ASE flags from ELF structures	9 years ago
mips-ase-3.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips-note-2-n32.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips-note-2-n64.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips-note-2.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips-note-2r-n32.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips-note-2r-n64.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips-note-2r.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips-reginfo-n32.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips-reginfo.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips-reginfo.s	MIPS/BFD: Correctly report unsupported `.reginfo' section size	8 years ago
mips-xpa-virt-1.d	MIPS/opcodes: Do not use CP0 register names for control registers	5 years ago
mips-xpa-virt-2.d	MIPS/binutils/testsuite: Fix XPA and Virtualization ASE cases	5 years ago
mips-xpa-virt-3.d	MIPS/opcodes: Do not use CP0 register names for control registers	5 years ago
mips-xpa-virt-4.d	MIPS/binutils/testsuite: Fix XPA and Virtualization ASE cases	5 years ago
mips-xpa-virt.s	MIPS: Fix XPA base and Virtualization ASE instruction handling	9 years ago
mips.exp	Update year range in copyright notice of binutils files	5 years ago
mips16-alias.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips16-alias.s	MIPS16/opcodes: Annotate instruction aliases	9 years ago
mips16-extend-insn.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips16-extend-insn.s	MIPS16: Handle non-extensible instructions correctly	9 years ago
mips16-extend-noinsn.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips16-extend-noinsn.s	MIPS16/opcodes: Reformat raw EXTEND and undecoded output	9 years ago
mips16-noalias.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips16-pcrel.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips16-pcrel.s	MIPS16/opcodes: Fix PC-relative operation delay-slot adjustment	9 years ago
mips16-undecoded.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips16-undecoded.s	MIPS16e2: Add new MIPS16e2 ASE binutils and GAS tests	9 years ago
mips16e2-extend-insn.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mips16e2-undecoded.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mixed-micromips.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mixed-micromips.s	opcodes/	13 years ago
mixed-mips16-micromips.d	MIPS/opcodes: Correct mixed MIPS16 and microMIPS disassembly	10 years ago
mixed-mips16-micromips.s	MIPS/opcodes: Correct mixed MIPS16 and microMIPS disassembly	10 years ago
mixed-mips16.d	MIPS/binutils/testsuite: Correct mips.exp test ABI/emul/endian arrangement	6 years ago
mixed-mips16.s	* binutils-all/mips/mixed-mips16.s: Add missing stack adjustment.	13 years ago