binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Nick Clifton	752937aa0c	Add copyright notices	14 years ago
H.J. Lu	43ecc30f09	Move 2009 binutils ChangeLog to ChangeLog-2009.	17 years ago
H.J. Lu	2426c15ff8	Replace VexNDS, VexNDD and VexLWP with VexVVVV. gas/ 2009-12-19 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check vexvvvv instead of vexnds and vexndd. (build_modrm_byte): Check vexvvvv instead of vexnds, vexndd and vexlwp. opcodes/ 2009-12-19 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and VexLWP. Add VexVVVV. * i386-opc.h (VexNDS): Removed. (VexNDD): Likewise. (VexLWP): Likewise. (VEXXDS): New. (VEXNDD): Likewise. (VEXLWP): Likewise. (VexVVVV): Likewise. (i386_opcode_modifier): Remove vexnds, vexndd and vexlwp. Add vexvvvv. * i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with VexVVVV=2 and VexLWP with VexVVVV=3. * i386-tbl.h: Regenerated.	17 years ago
H.J. Lu	94ff3a50d8	Move Imm1 before Imm8. 2009-12-18 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (operand_types): Move Imm1 before Imm8.	17 years ago
Nick Clifton	ff4a8d2b93	PR binutils/10924 * config/tc-arm.c (do_ldstv4): Do not allow r15 as the destination register. (do_mrs): Likewise. (do_mul): Likewise. * arm-dis.c: Add support for %<>ru and %<>rU formats to enforce unique register numbers. Extend support for %<>R format to thumb32 and coprocessor instructions. * gas/arm/unpredictable.s: Add more unpredictable instructions. * gas/arm/unpredictable.d: Add expected disassemblies.	17 years ago
H.J. Lu	2eb952a4d9	Remove ByteOkIntel. gas/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Set i.suffix to 0 in Intel syntax if size is ignored and b/l/w suffixes are illegal. (check_byte_reg): Remove byteokintel check. opcodes/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove ByteOkIntel. * i386-opc.h (ByteOkIntel): Removed. (i386_opcode_modifier): Remove byteokintel. * i386-opc.tbl: Remove ByteOkIntel. * i386-tbl.h: Regenerated.	17 years ago
H.J. Lu	7f399153c6	Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode. gas/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Replace vex0f, vex0f38, vex0f3a, xop08, xop09 and xop0a with vexopcode. opcodes/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A. Add VexOpcode. * i386-opc.h (Vex0F): Removed. (Vex0F38): Likewise. (Vex0F3A): Likewise. (VexOpcode): New. (VEX0F): Likewise. (VEX0F38): Likewise. (VEX0F3A): Likewise. (XOP08): Defined as a macro. (XOP09): Likewise. (XOP0A): Likewise. (i386_opcode_modifier): Remove vex0f, vex0f38, vex0f3a, xop08, xop09 and xop0a. Add vexopcode. * i386-opc.tbl: Replace Vex0F with VexOpcode=0, Vex0F38 with VexOpcode=1, Vex0F3A with VexOpcode=2, XOP08 with VexOpcode=3, XOP09 with VexOpcode=4 and XOP0A with VexOpcode=5. * i386-tbl.h: Regenerated.	17 years ago
H.J. Lu	25ac7f26dd	Fix a typo in ChangeLog.	17 years ago
H.J. Lu	8c43a48b28	Replace VEX2SOURCES with XOP2SOURCES. gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_modrm_byte): Check XOP2SOURCES instead VEX2SOURCES. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VEX2SOURCES): Renamed to ... (XOP2SOURCES): This.	17 years ago
H.J. Lu	8cd7925b45	Replace Vex2Sources and Vex3Sources with VexSources. gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check vexsources instead of vex3sources. (build_modrm_byte): Check vexsources instead of vex2sources and vex3sources. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove Vex3Sources and Vex2Sources. Add VexSources. * i386-opc.h ()Vex2Sources: Removed. (Vex3Sources): Likewise. (VEX2SOURCES): New. (VEX3SOURCES): Likewise. (VexSources): Likewise. (i386_opcode_modifier): Remove vex2sources and vex3sources. Add vexsources. * i386-opc.tbl: Replace Vex2Sources with VexSources=1 and Vex3Sourceswith VexSources=2. * i386-tbl.h: Regenerated.	17 years ago
H.J. Lu	1ef99a7be9	Remove VexW0 and VexW1. Add VexW. gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Replace vexw0/vexw1 with vexw. (build_modrm_byte): Likewise. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove VexW0 and VexW1. Add VexW. * i386-opc.h (VexW0): Removed. (VexW1): Likewise. (VEXW0): New. (VEXW1): Likewise. (VexW): Likewise. (i386_opcode_modifier): Remove vexw0 and vexw1. Add vexw. * i386-opc.tbl: Replace VexW0 with VexW=1 and VexW1 with Vex=2. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	17 years ago
H.J. Lu	bcf2684fb0	Add VEX_W_3818_P_2_M_0. 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (VEX_W_3818_P_2_M_0): New. (vex_w_table): Add VEX_W_3818_P_2_M_0. (mod_table): Use VEX_W_3818_P_2_M_0.	17 years ago
H.J. Lu	a179a9fdaa	Reformat vex_w_table. 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (vex_w_table): Reformat.	17 years ago
H.J. Lu	53aa04a0be	Add VEX_W_382X_P_2_M_0. 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (VEX_W_382X_P_2_M_0): New. (vex_w_table): Add VEX_W_382X_P_2_M_0. (mod_table): Use VEX_W_382X_P_2_M_0.	17 years ago
H.J. Lu	efdb52b70e	Reformat vex_w_table. 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (vex_w_table): Reformat.	17 years ago
H.J. Lu	9e30b8e093	Add USE_VEX_W_TABLE, VEX_W_TABLE and VEX_W_XXX. 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (USE_VEX_W_TABLE): New. (VEX_W_TABLE): Likewise. (VEX_W_XXX): Likewise. (vex_w_table): Likewise. (prefix_table): Use VEX_W_XXX. (vex_table): Likewise. (vex_len_table): Likewise. (mod_table): Likewise. (get_valid_dis386): Handle USE_VEX_W_TABLE. * i386-opc.tbl: Add VexW0 to AVX instructions where the VEX.W bit isn't used. * i386-tbl.h: Regenerated.	17 years ago
H.J. Lu	e3c58833bf	Define VEX128 and VEX256. gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Use VEX256. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VEX128): New. (VEX256): Likewise.	17 years ago
H.J. Lu	4c807e7262	Reformat vex_len_table. 2009-12-14 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (vex_len_table): Reformat.	17 years ago
H.J. Lu	976f1fde11	Rename MOD_VEX_51 to MOD_VEX_50. 2009-12-14 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (MOD_VEX_51): Renamed to ... (MOD_VEX_50): This. (vex_table): Updated. (mod_table): Likewise.	17 years ago
Nick Clifton	ab8e2090b6	PR binutils/10924 * arm-dis.c (arm_opcodes): Specify %R in cases where using r15 results in unpredictable behaviour. (print_insn_arm): Handle %R. * gas/arm/unpredictable.s: New test case - checks the disassembly of instructions with unpredictable behaviour. * gas/arm/unpredictable.d: New file - expected disassembly.	17 years ago
H.J. Lu	759a05ce24	Set vex.w to 0 for VEX C5 prefix. 2009-12-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (get_valid_dis386): Set vex.w to 0 for VEX C5 prefix. (print_insn): Don't set vex.w here.	17 years ago
H.J. Lu	5639ff8726	2009-12-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (print_insn): Set vex.w to 0.	17 years ago
Sebastian Pop	02e647f941	2009-12-11 Quentin Neill <quentin.neill@amd.com> gas/testsuite/ * gas/i386/fma4.d: Add test cases. * gas/i386/fma4.s: Add test cases. * gas/i386/x86-64-fma4.d: Add test cases. * gas/i386/x86-64-fma4.s: Add test cases. opcodes/ * i386-dis.c (get_vex_imm8): Extend logic to apply in all cases, to avoid fetching ahead for the immediate bytes when OP_E_memory has already been called. Fix indentation.	17 years ago
Nick Clifton	91d6fa6a03	Add -Wshadow to the gcc command line options used when compiling the binutils. Fix up all warnings generated by the addition of this switch.	17 years ago
Nick Clifton	07a28fab11	PR 10924 * arm-dis.c (print_insn_arm): Mark insns that use the PC in post-indexed addressing as unpredictable.	17 years ago
H.J. Lu	eacc9c891d	Support fxsave64 and fxrstor64. gas/testsuite/ 2009-12-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run x86-64-fxsave and x86-64-fxsave-intel. * gas/i386/rex.d: Updated for fxsave64. * gas/i386/x86-64-fxsave-intel.d: New. * gas/i386/x86-64-fxsave.d: Likewise. * gas/i386/x86-64-fxsave.s: Likewise. opcodes/ 2009-12-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (FXSAVE_Fixup): New. (FXSAVE): Likewise. (mod_table): Use FXSAVE on fxsave and fxrstor. * i386-opc.tbl: Add fxsave64 and fxrstor64. * i386-tbl.h: Regenerated.	17 years ago
Nick Clifton	03ee1b7f8e	PR gas/11013 * arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB and QDSUB. * gas/arm/arch7em.d: Update expected disassembly. * gas/arm/thumb32.d: Likewise. * config/tc-arm.c (do_t_simd2): New function. (insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB.	17 years ago
Nick Clifton	ee9fd255b7	PR gas/11030 * m68k-opc.c (m68k_opcodes): Allow the STLDSR instruction on the Coldfire ISA A+.	17 years ago
Sebastian Pop	ccc5981b93	2009-11-17 Quentin Neill <quentin.neill@amd.com> Sebastian Pop <sebastian.pop@amd.com> gas/testsuite/ * gas/i386/x86-64-fma4.d: Add new patterns. * gas/i386/x86-64-fma4.s: Same. * gas/i386/x86-64-xop.d: Adjusted. opcodes/ * i386-dis.c (get_vex_imm8): Increase bytes_before_imm when decoding the second source operand from the immediate byte. (OP_EX_VexW): Pass an extra integer to identify the second and third source arguments.	17 years ago
H.J. Lu	18d0c96eb9	Allow lock on cmpxch16b. gas/testsuite/ 2009-11-19 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/lock-1.s: Add cmpxchg16b test. * gas/i386/lock-1-intel.d: Updated. * gas/i386/lock-1.d: Likewise. opcodes/ 2009-11-19 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add IsLockable to cmpxch16b. * i386-tbl.h: Regenerated.	17 years ago
Nick Clifton	945ee43039	PR binutils/10924 * gas/arm/arch4t-eabi.d: Restore previous expected dissambly of instructions using Immediate Offset addressing with an offset of zero. * gas/arm/arch4t.d: Likewise. * gas/arm/arm7t.d: Likewise. * gas/arm/xscale.d: Likewise. * gas/arm/wince-inst.d: Remove 'p' suffix from cmp, cmn, teq and tst instructions. PR binutils/10924 * arm-dis.c (print_insn_arm): Do not print an offset of zero when decoding Immediaate Offset addressing.	17 years ago
Sebastian Pop	41effecb2d	2009-11-18 Sebastian Pop <sebastian.pop@amd.com> opcodes/ PR binutils/10973 * i386-dis.c (get_vex_imm8): Do not increment codep. Avoid incrementing bytes_before_imm when OP_E_memory has already forwarded the codep pointer. (OP_EX_VexW): Increment codep to skip mod/rm byte. gas/testsuite/ * gas/i386/x86-64-xop.d: Update patterns.	17 years ago
Sebastian Pop	f0ae4a24b0	2009-11-18 Sebastian Pop <sebastian.pop@amd.com> gas/ * config/tc-i386.c (cpu_arch): Remove cvt16. (md_show_usage): Same. * doc/c-i386.texi: Same. gas/testsuite/ * gas/i386/cvt16.d: Removed. * gas/i386/cvt16.s: Removed. * gas/i386/x86-64-cvt16.d: Removed. * gas/i386/x86-64-cvt16.s: Removed. * gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests. opcodes/ * i386-dis.c (VEX_LEN_XOP_08_A0): Removed. (VEX_LEN_XOP_08_A1): Removed. (xop_table): Remove entries for VEX_LEN_XOP_08_A0 and VEX_LEN_XOP_08_A1. (vex_len_table): Same. * i386-gen.c (CPU_CVT16_FLAGS): Removed. (cpu_flags): Remove field for CpuCVT16. * i386-opc.h (CpuCVT16): Removed. (i386_cpu_flags): Remove bitfield cpucvt16. (i386-opc.tbl): Remove CVT16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.	17 years ago
Sebastian Pop	5dd85c9970	2009-11-17 Sebastian Pop <sebastian.pop@amd.com> Quentin Neill <quentin.neill@amd.com> gas/ * config/tc-i386.c (cpu_arch): Added .xop and .cvt16. (build_vex_prefix): Handle xop08. (md_assemble): Don't special case the constant 3 for insns using MODRM. (build_modrm_byte): Handle vex2sources. (md_show_usage): Add xop and cvt16. * doc/c-i386.texi: Document fma4, xop, and cvt16. gas/testsuite/ * gas/i386/i386.exp: Run xop and cvt16 in 32-bit mode. Run x86-64-xop and x86-64-cvt16 in 64-bit mode. * gas/i386/lwp.d: Update name of the testcase. * gas/i386/x86-64-xop.d: New. * gas/i386/x86-64-xop.s: New. * gas/i386/xop.d: New. * gas/i386/xop.s: New. * gas/i386/cvt16.d: New. * gas/i386/cvt16.s: New. opcodes/ * i386-dis.c (OP_Vex_2src_1): New. (OP_Vex_2src_2): New. (Vex_2src_1): New. (Vex_2src_2): New. (XOP_08): Added. (VEX_LEN_XOP_08_A0): Added. (VEX_LEN_XOP_08_A1): Added. (VEX_LEN_XOP_09_80): Added. (VEX_LEN_XOP_09_81): Added. (xop_table): Added an entry for XOP_08. Handle xop instructions. (vex_len_table): Added entries for VEX_LEN_XOP_08_A0, VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81. (get_valid_dis386): Handle XOP_08. (OP_Vex_2src): New. * i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS. (cpu_flags): Add CpuXOP and CpuCVT16. (opcode_modifiers): Add XOP08, Vex2Sources. * i386-opc.h (CpuXOP): Added. (CpuCVT16): Added. (i386_cpu_flags): Add cpuxop and cpucvt16. (XOP08): Added. (Vex2Sources): Added. (i386_opcode_modifier): Add xop08, vex2sources. * i386-opc.tbl: Add entries for XOP and CVT16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.	17 years ago
Nick Clifton	aefd8a406c	* gas/arm/vfma1.d: Only run on ELF based targets. PR binutils/10924 * gas/arm/arch4t-eabi.d: Update expected disassembly. * gas/arm/arch4t.d: Likewise. * gas/arm/archv6t2.d: Likewise. * gas/arm/arm7t.d: Likewise. * gas/arm/inst.d: Likewise. * gas/arm/xscale.d: Likewise. PR binutils/10924 * arm-dis.c (arm_opcodes): Add patterns to match undefined LDRB instruction variants. Add pattern for MRS variant that was being confused with CMP. (arm_decode_shift): Place error message in a comment. (print_insn_arm): Note that writing back to the PC is unpredictable. Only print 'p' variants of cmp/cmn/teq/tst instructions if decoding for pre-V6 architectures.	17 years ago
Ramana Radhakrishnan	0bb027fd62	2009-11-17 Edward Nevill <edward.nevill@arm.com> * arm-dis.c (print_insn_thumb32): Handle undefined instruction.	17 years ago
Doug Evans	c7e770a030	opcodes/ * Makefile.am (stamp-xc16x): Use ../cpu/xc16x.cpu instead of ../cgen/cpu. * Makefile.in: Regenerate. cgen/ * cpu/xc16x.cpu: Delete, use copy in ../cpu. * cpu/xc16x.opc: Ditto.	17 years ago
H.J. Lu	8b3f93e7a1	2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_extended): Removed.	17 years ago
H.J. Lu	2a70cca486	Check rex_ignored. gas/testsuite/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/rex.s: Add a test for VEX insn. * gas/i386/rex.d: Updated. opcodes/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (print_insn): Check rex_ignored.	17 years ago
H.J. Lu	f16cd0d502	Rewrite prefix processing. gas/testsuite/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run long-1, long-1-intel, x86-64-long-1, and x86-64-long-1-intel. * gas/i386/long-1-intel.d: New. * gas/i386/long-1.d: Likewise. * gas/i386/long-1.s: Likewise. * gas/i386/x86-64-long-1-intel.d: Likewise. * gas/i386/x86-64-long-1.d: Likewise. * gas/i386/x86-64-long-1.s: Likewise. * gas/i386/jump16.d: Updated for prefix processing. * gas/i386/naked.d: Likewise. * gas/i386/nops-1-core2.d: Likewise. * gas/i386/nops-1-i686.d: Likewise. * gas/i386/nops-3-i686.d: Likewise. * gas/i386/nops-4-i686.d: Likewise. * gas/i386/nops-5-i686.d: Likewise. * gas/i386/nops-5.d: Likewise. * gas/i386/prefix.d: Likewise. * gas/i386/rep.d: Likewise. * gas/i386/string-ok.d: Likewise. * gas/i386/x86-64-addr32-intel.d: Likewise. * gas/i386/x86-64-addr32.d: Likewise. * gas/i386/x86-64-cbw-intel.d: Likewise. * gas/i386/x86-64-cbw.d: Likewise. * gas/i386/x86-64-io-intel.d: Likewise. * gas/i386/x86-64-io-suffix.d: Likewise. * gas/i386/x86-64-io.d: Likewise. * gas/i386/x86-64-lwp.d: Likewise. * gas/i386/x86-64-nops-1-core2.d: Likewise. * gas/i386/x86-64-nops-1-nocona.d: Likewise. * gas/i386/x86-64-nops-1.d: Likewise. * gas/i386/x86-64-nops-2.d: Likewise. * gas/i386/x86-64-nops-3.d: Likewise. * gas/i386/x86-64-nops-4-core2.d: Likewise. * gas/i386/x86-64-nops-4.d: Likewise. * gas/i386/x86-64-nops-5-k8.d: Likewise. * gas/i386/x86-64-nops-5.d: Likewise. * gas/i386/x86-64-rep.d: Likewise. * gas/i386/x86-64-stack-intel.d: Likewise. * gas/i386/x86-64-stack-suffix.d: Likewise. * gas/i386/x86-64-stack.d: Likewise. ld/testsuite/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * ld-x86-64/tlsbin.dd: Updated for prefix processing. * ld-x86-64/tlsgdesc.dd: Likewise. * ld-x86-64/tlsld1.dd: Likewise. * ld-x86-64/tlspic.dd: Likewise. opcodes/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (ckprefix): Updated to return 0 if number of prefixes > 14 and record the last position for each prefix. (lock_prefix): Removed. (data_prefix): Likewise. (addr_prefix): Likewise. (repz_prefix): Likewise. (repnz_prefix): Likewise. (last_lock_prefix): New. (last_repz_prefix): Likewise. (last_repnz_prefix): Likewise. (last_data_prefix): Likewise. (last_addr_prefix): Likewise. (last_rex_prefix): Likewise. (last_seg_prefix): Likewise. (MAX_CODE_LENGTH): Likewise. (ADDR16_PREFIX): Likewise. (ADDR32_PREFIX): Likewise. (DATA16_PREFIX): Likewise. (DATA32_PREFIX): Likewise. (REP_PREFIX): Likewise. (seg_prefix): Likewise. (all_prefixes): Change size to MAX_CODE_LENGTH - 1. (prefix_name): Handle ADDR16_PREFIX, ADDR32_PREFIX, DATA16_PREFIX, DATA32_PREFIX and REP_PREFIX. (get_valid_dis386): Updated. (OP_C): Likewise. (OP_Monitor): Likewise. (REP_Fixup): Likewise. (print_insn): Display all prefixes. (putop): Set PREFIX_DATA on used_prefixes only if it is used. (intel_operand_size): Likewise. (OP_E_register): Likewise. (OP_G): Likewise. (OP_REG): Likewise. (OP_IMREG): Likewise. (OP_I): Likewise. (OP_I64): Likewise. (OP_sI): Likewise. (CRC32_Fixup): Likewise. (MOVBE_Fixup): Likewise. (OP_E_memory): Set REFIX_DATA on used_prefixes when it is used in 16bit mode. (OP_J): Set REX_W used if it is used. Set PREFIX_DATA on used_prefixes only if it is used.	17 years ago
H.J. Lu	20efc68957	2009-11-12 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Remove IsLockable from add, adc, and, dec, inc, or, sbb, sub, xor and xchg with register only operands. * i386-tbl.h: Regenerated.	17 years ago
H.J. Lu	c32fa91d70	gas/ 2009-11-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (LOCKREP_PREFIX): Removed. (REP_PREFIX): New. (LOCK_PREFIX): Likewise. (PREFIX_GROUP): Likewise. (REX_PREFIX): Updated. (MAX_PREFIXES): Likewise. (add_prefix): Updated. Return enum PREFIX_GROUP. (md_assemble): Check for lock without a lockable instruction. (parse_insn): Updated. (output_insn): Likewise. gas/testsuite/ 2009-11-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run lock-1, lock-1-intel, lockbad-1, x86-64-lock-1, x86-64-lock-1-intel and x86-64-lockbad-1. * gas/i386/lock-1-intel.d: New. * gas/i386/lock-1.d: Likewise. * gas/i386/lock-1.s: Likewise. * gas/i386/lockbad-1.l: Likewise. * gas/i386/lockbad-1.s: Likewise. * gas/i386/x86-64-lock-1-intel.d: Likewise. * gas/i386/x86-64-lock-1.d: Likewise. * gas/i386/x86-64-lock-1.s: Likewise. * gas/i386/x86-64-lockbad-1.l: Likewise. * gas/i386/x86-64-lockbad-1.s: Likewise. opcodes/ 2009-11-12 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add IsLockable. * i386-opc.h (IsLockable): New. (i386_opcode_modifier): Add islockable. * i386-opc.tbl: Add IsLockable to add, adc, and, btc, btr, bts, cmpxchg, cmpxch8b, dec, inc, neg, not, or, sbb, sub, xor, xadd and xchg. * i386-tbl.h: Regenerated.	17 years ago
Daniel Jacobowitz	79862e4574	gas/testsuite/ * gas/arm/copro.d, gas/arm/fp-save.d, gas/arm/float.d, gas/arm/fpa-mem.d: Update for removed generic coprocessor instructions and expanded PC-relative offsets. opcodes/ * arm-dis.c (coprocessor_opcodes): Use %A instead of %C. Remove generic coprocessor instructions for FPA loads and stores. (print_insn_coprocessor): Remove %C support. Display address for PC-relative offsets in %A.	17 years ago
H.J. Lu	f310f33d50	gas/testsuite/ 2009-11-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/prefix.d: Swap order of ADDR and REP prefixes. * gas/i386/rep.d: Likewise. * gas/i386/x86-64-rep.d: Likewise. opcodes/ 2009-11-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (all_prefixes): New. (ckprefix): Set all_prefixes. (print_insn): Print all_prefixes instead of lock_prefix, repz_prefix, repnz_prefix, addr_prefix and data_prefix.	17 years ago
Nick Clifton	c1e2689731	PR binutils/10924 * arm-dis.c (UNPREDICTABLE_INSTRUCTION): New macro. (print_insn_arm): Extend %s format control code to check for unpredictable addressing modes. Add support for %S format control code which suppresses this check. (W_BIT, I_BIT, U_BIT, P_BIT): New macros. (WRITEBACK_BIT_SET, IMMEDIATE_BIT_SET, NEGATIVE_BIT_SET, PRE_BIT_SET): New macros. (print_insn_coprocessor): Use the new macros instead of magic constants. (print_arm_address): Likewise. (pirnt_insn_arm): Likewise. (print_insn_thumb32): Likewise.	17 years ago
Nick Clifton	41327c9d6d	Updated Indonesian translation.	17 years ago
Maxim Kuvyrkov	0d999f3337	* config/m68k-parse.h (enum m68k_register): Add ACR[4-7], RGPIOBAR. * config/tc-m68k.c (mcf5206_ctrl): Fix whitespace. (mcf52223_ctrl): Remove non-existent registers. (mcf54418): Define. (mcf54455): Remove MBAR. (m68k_cpus): Add lines for MCF5441x family. (m68k_ip, init_table): Handle RGPIOBAR, ACR[4-7]. * m68k-dis.c (print_insn_arg): Handle RGPIOBAR, ACR[4-7] and MBAR[01].	17 years ago
Sebastian Pop	c48244a521	2009-11-06 Sebastian Pop <sebastian.pop@amd.com> * opcodes/i386-dis.c (reg_table): Add XOP_8F_TABLE (XOP_09) to reg_table[REG_8F][1]: for XOP instructions, ModRM.reg first points to B.mm in the RXB.mmmmm byte, and so when B is set, we still should use the xop_table. (get_valid_dis386): Removed unused condition (from cut/n/paste) for XOP instructions. * gas/testsuite/gas/i386/x86-64-lwp.s: Updated to also contain patterns with r[8-15] registers. * gas/testsuite/gas/i386/x86-64-lwp.d: Same.	17 years ago
Sebastian Pop	f88c9eb030	2009-11-05 Sebastian Pop <sebastian.pop@amd.com> Quentin Neill <quentin.neill@amd.com> * gas/config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS. (build_vex_prefix): Handle xop09 and xop0a. (build_modrm_byte): Handle vexlwp. (md_show_usage): Add lwp. * gas/doc/c-i386.texi (i386-LWP): New section. * gas/testsuite/gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode, run lwp in 32-bit mode. * gas/testsuite/gas/i386/x86-64-lwp.d: New. * gas/testsuite/gas/i386/x86-64-lwp.s: New. * gas/testsuite/gas/i386/lwp.d: New. * gas/testsuite/gas/i386/lwp.s: New. * opcodes/i386-dis.c (OP_LWPCB_E): New. (OP_LWP_E): New. (OP_LWP_I): New. (USE_XOP_8F_TABLE): New. (XOP_8F_TABLE): New. (REG_XOP_LWPCB): New. (REG_XOP_LWP): New. (XOP_09): New. (XOP_0A): New. (reg_table): Redirect REG_8F to XOP_8F_TABLE. Add entries for REG_XOP_LWPCB and REG_XOP_LWP. (xop_table): New. (get_valid_dis386): Handle USE_XOP_8F_TABLE. Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values to access to the vex_table. (OP_LWPCB_E): New. (OP_LWP_E): New. (OP_LWP_I): New. * opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP. (cpu_flags): Add CpuLWP. (opcode_modifiers): Add VexLWP, XOP09, and XOP0A. * opcodes/i386-opc.h (CpuLWP): New. (i386_cpu_flags): Add bit cpulwp. (VexLWP): New. (XOP09): New. (XOP0A): New. (i386_opcode_modifier): Add vexlwp, xop09, and xop0a. * opcodes/i386-opc.tbl (llwpcb): Added. (lwpval): Added. (lwpins): Added.	17 years ago
DJ Delorie	0d734b5d06	[opcodes] * rx-decode.opc (rx_decode_opcode) (mvtipl): Add. (mvtcp, mvfcp, opecp): Remove. * rx-decode.c: Regenerate. * rx-dis.c (cpen): Remove. [gas] * config/rx-parse.y (MVTIPL): Update bit pattern. (cpen): Remove. [include/opcode] * rx.h (rx_decode_opcode) (mvtipl): Add. (mvtcp, mvfcp, opecp): Remove.	17 years ago

2 Commits (f3f6c0df60c4e8a6c3409db4f23f2cdec5a9d41c)