binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Jan Beulich	f2f6a710f4	x86: avoid SSE check for LDMXCSR/STMXCSR Neither touches any XMM register, so the check is pointless. It is imo even questionable whether in SSE2AVX mode the two should be converted to their AVX counterparts.	8 years ago
Jan Beulich	38e314eb06	x86: drop FloatD It can be expressed by D, when making the consumer look at operand size to tell apart both uses.	8 years ago
Jan Beulich	d53e6b98a2	x86/Intel: correct disassembly of fsub/fdiv fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly should match (a) the Intel SDM and (b) respective input fed to gas (both of course with the exception of when we intentionally convert bogus insns, accompanied by a warning).	8 years ago
Jan Beulich	2907c2f555	x86: bogus VMOVD with 64-bit operands should only allow for registers These templates exist solely to satisfy gcc's needs, and gcc only produces these with register operands.	8 years ago
Jan Beulich	73053c1fc4	x86: fold AVX vcvtpd2ps memory forms This requires a change to ModR/M handling: Recording of displacement types must not discard operand size information. Change the respective code to alter only .disp<N>.	8 years ago
Alan Modra	52fe4420b7	XCOFF disassembler xcoff (32-bit) objdump accepted but ignored -M options unless -mpowerpc was also given. This patch fixes that, leaving the default as -Mpwr for xcoff. I've also enabled more tests for xcoff targets. binutils/ * configure.ac: Add objdump_private_desc_xcoff for rs6000. * configure: Regenerate. gas/ * testsuite/gas/ppc/aix.exp: Run for rs6000 too. * testsuite/gas/ppc/ppc.exp: Run more tests for non-ELF targets. * testsuite/gas/ppc/machine.d: Don't run for PE targets. opcodes/ * disassemble.c (disassembler): Use bfd_arch_powerpc entry for bfd_arch_rs6000. * disassemble.h (print_insn_rs6000): Delete. * ppc-dis.c (powerpc_init_dialect): Handle rs6000. (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000. (print_insn_rs6000): Delete.	8 years ago
Alan Modra	a6743a5420	opcodes error messages Another patch aimed at making binutils comply with the GNU coding standard. The generated files require https://sourceware.org/ml/cgen/2018-q1/msg00004.html cpu/ * frv.opc: Include opintl.h. (add_next_to_vliw): Use opcodes_error_handler to print error. Standardize error message. (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise. opcodes/ * sysdep.h (opcodes_error_handler): Define. (_bfd_error_handler): Declare. * Makefile.am: Remove stray #. * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT EDIT" comment. * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use opcodes_error_handler to print errors. Standardize error messages. * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, and include opintl.h. * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. * i386-gen.c: Standardize error messages. * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. * Makefile.in: Regenerate. * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.	8 years ago
H.J. Lu	8305403a1f	x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128 When 2 source registers are identical, AVX256 and AVX512 vpsub[bwdq] instructions can be encoded with VEX128 or EVEX128 encodings. gas/ * config/tc-i386.c (optimize_encoding): Optimize AVX256 and AVX512 vpsub[bwdq] instructions. * testsuite/gas/i386/optimize-1.s: Add tests for AVX256 and AVX512 vpsub[bwdq] instructions. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. opcodes/ * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512 vpsub[bwdq] instructions. * i386-tbl.h: Regenerated.	8 years ago
Alan Modra	e184813fdb	Add missing translations to ALL_LINGUAS binutils/ * configure.ac (ALL_LINGUAS): Add sr. Sort. * configure: Regenerate. gas/ * configure.ac (ALL_LINGUAS): Add uk. Sort. * configure: Regenerate. gprof/ * configure.ac (ALL_LINGUAS): Add it, ro, ru, uk. Sort. * configure: Regenerate. ld/ * configure.ac (ALL_LINGUAS): Add ja. Sort. * configure: Regenerate. opcodes/ * configure.ac (ALL_LINGUAS): Sort. * configure: Regenerate.	8 years ago
Thomas Preud'homme	5b616beff4	[ARM] Remove ARM_FEATURE_COPY macro Among the macros to manipulate an arm_feature_set structure is the ARM_FEATURE_COPY which copy the value of a feature set into another. This can be achieved with a simple assignement which most of the existing code does. This patch removes the last 2 uses of that macro and remove the macro altogether. 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com> include/ * opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition. 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com> opcodes/ * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY macro by assignements.	8 years ago
H.J. Lu	b6f8c7c452	x86: Add -O[2\|s] assembler command-line options On x86, some instructions have alternate shorter encodings: 1. When the upper 32 bits of destination registers of andq $imm31, %r64 testq $imm31, %r64 xorq %r64, %r64 subq %r64, %r64 known to be zero, we can encode them without the REX_W bit: andl $imm31, %r32 testl $imm31, %r32 xorl %r32, %r32 subl %r32, %r32 This optimization is enabled with -O, -O2 and -Os. 2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit immediate to 64-bit destination register, we can use it to encode 64-bit mov with 32-bit immediates. This optimization is enabled with -O, -O2 and -Os. 3. Since the upper bits of destination registers of VEX128 and EVEX128 instructions are extended to zero, if all bits of destination registers of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128 encoding to encode AVX256 or AVX512 instructions. When 2 source registers are identical, AVX256 and AVX512 andn and xor instructions: VOP %reg, %reg, %dest_reg can be encoded with VOP128 %reg, %reg, %dest_reg This optimization is enabled with -O2 and -Os. 4. 16-bit, 32-bit and 64-bit register tests with immediate may be encoded as 8-bit register test with immediate. This optimization is enabled with -Os. This patch does: 1. Add {nooptimize} pseudo prefix to disable instruction size optimization. 2. Add optimize to i386_opcode_modifier to tell assembler that encoding of an instruction may be optimized. gas/ PR gas/22871 * NEWS: Mention -O[2\|s]. * config/tc-i386.c (_i386_insn): Add no_optimize. (optimize): New. (optimize_for_space): Likewise. (fits_in_imm7): New function. (fits_in_imm31): Likewise. (optimize_encoding): Likewise. (md_assemble): Call optimize_encoding to optimize encoding. (parse_insn): Handle {nooptimize}. (md_shortopts): Append "O::". (md_parse_option): Handle -On. * doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well as {nooptimize}. * testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler. * testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise. * testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2, optimize-3, x86-64-optimize-1, x86-64-optimize-2, x86-64-optimize-3 and x86-64-optimize-4. * testsuite/gas/i386/optimize-1.d: New file. * testsuite/gas/i386/optimize-1.s: Likewise. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-2.s: Likewise. * testsuite/gas/i386/optimize-3.d: Likewise. * testsuite/gas/i386/optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-1.s: Likewise. * testsuite/gas/i386/x86-64-optimize-1.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-4.d: Likewise. * testsuite/gas/i386/x86-64-optimize-4.s: Likewise. opcodes/ PR gas/22871 * i386-gen.c (opcode_modifiers): Add Optimize. * i386-opc.h (Optimize): New enum. (i386_opcode_modifier): Add optimize. * i386-opc.tbl: Add "Optimize" to "mov $imm, reg", "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem", "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem", "movq $imm, reg" and AVX256 and AVX512 versions of vandnps, vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor, vpxord and vpxorq. * i386-tbl.h: Regenerated.	8 years ago
Alan Modra	e95b887f85	crx string overflow warning gcc8 complains wrongly about the buffer not being large enough, at least at -Og optimization. * crx-dis.c (getregliststring): Allocate a large enough buffer to silence false positive gcc8 warning.	8 years ago
Jim Wilson	0bccfb2994	RISC-V: Make disassebler work for --enable-targets=all config. opcodes/ * disassemble.c (ARCH_riscv): Define if ARCH_all.	8 years ago
H.J. Lu	6b6b680700	x86: Add {rex} pseudo prefix Add {rex} pseudo prefix to generate a REX byte for integer and legacy vector instructions if possible. Note that this differs from the rex prefix which generates REX prefix unconditionally. gas/ * config/tc-i386.c (_i386_insn): Add rex_encoding. (md_assemble): When i.rex_encoding is true, generate a REX byte if possible. (parse_insn): Set i.rex_encoding for {rex}. * doc/c-i386.texi: Document {rex}. * testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests. * testsuite/gas/i386/x86-64-pseudos.d: Updated. opcodes/ * i386-opc.tbl: Add {rex}, * i386-tbl.h: Regenerated.	8 years ago
Maciej W. Rozycki	75f3166520	MIPS16/opcodes: Free up `M' operand code The `M' and `m' MIPS16 operand codes are functionally the same, denoting a 7-bit register list that is encoded the same way for both SAVE and RESTORE. Use `m' for both instructions then, making `M' available for a different use. opcodes/ * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case. (mips16_opcodes): Replace `M' with `m' for "restore". include/ * opcode/mips.h: Remove `M' operand code.	8 years ago
Thomas Preud'homme	e207bc53a4	[ARM] Fix bxns mask Bit 7 of BXNS is a fixed bit which distinguish it from BLXNS. Yet it is not set in the disassembler entry mask. This commit fixes that. 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com> opcodes/ * arm-dis.c (thumb_opcodes): Fix BXNS mask.	8 years ago
Nick Clifton	68d2067666	Fix compile time warning messages from gcc version 8 about cast between incompatible function types. PR 22823 bfd Fix compile time warnings generated by gcc version 8. * libbfd-in.h: Remove extraneous text from prototypes. Add prototypes for bfd_false_any, bfd_true_any, bfd_nullvoidptr_any, bfd_0_any, bfd_0u_any, bfd_0l_any, bfd_n1_any, bfd_void_any. (_bfd_generic_bfd_copy_private_bfd_data): Use vararg based dummy function. (_bfd_generic_bfd_merge_private_bfd_data): Likewise. (_bfd_generic_bfd_set_private_flags): Likewise. (_bfd_generic_bfd_copy_private_section_data): Likewise. (_bfd_generic_bfd_copy_private_symbol_data): Likewise. (_bfd_generic_bfd_copy_private_header_data): Likewise. (_bfd_generic_bfd_print_private_bfd_data): Likewise. (_bfd_noarchive_construct_extended_name_table): Likewise. (_bfd_noarchive_truncate_arname): Likewise. (_bfd_noarchive_write_ar_hdr): Likewise. (_bfd_noarchive_get_elt_at_index): Likewise. (_bfd_nosymbols_canonicalize_symtab): Likewise. (_bfd_nosymbols_print_symbol): Likewise. (_bfd_nosymbols_get_symbol_info): Likewise. (_bfd_nosymbols_get_symbol_version_string): Likewise. (_bfd_nosymbols_bfd_is_local_label_name): Likewise. (_bfd_nosymbols_bfd_is_target_special_symbol): Likewise. (_bfd_nosymbols_get_lineno): Likewise. (_bfd_nosymbols_find_nearest_line): Likewise. (_bfd_nosymbols_find_line): Likewise. (_bfd_nosymbols_find_inliner_info): Likewise. (_bfd_nosymbols_bfd_make_debug_symbol): Likewise. (_bfd_nosymbols_read_minisymbols): Likewise. (_bfd_nosymbols_minisymbol_to_symbol): Likewise. (_bfd_norelocs_bfd_reloc_type_lookup): Likewise. (_bfd_norelocs_bfd_reloc_name_lookup): Likewise. (_bfd_nowrite_set_arch_mach): Likewise. (_bfd_nowrite_set_section_contents): Likewise. (_bfd_nolink_sizeof_headers): Likewise. (_bfd_nolink_bfd_get_relocated_section_contents): Likewise. (_bfd_nolink_bfd_relax_section): Likewise. (_bfd_nolink_bfd_gc_sections): Likewise. (_bfd_nolink_bfd_lookup_section_flags): Likewise. (_bfd_nolink_bfd_merge_sections): Likewise. (_bfd_nolink_bfd_is_group_section): Likewise. (_bfd_nolink_bfd_discard_group): Likewise. (_bfd_nolink_bfd_link_hash_table_create): Likewise. (_bfd_nolink_bfd_link_add_symbols): Likewise. (_bfd_nolink_bfd_link_just_syms): Likewise. (_bfd_nolink_bfd_copy_link_hash_symbol_type): Likewise. (_bfd_nolink_bfd_final_link): Likewise. (_bfd_nolink_bfd_link_split_section): Likewise. (_bfd_nolink_section_already_linked): Likewise. (_bfd_nolink_bfd_define_common_symbol): Likewise. (_bfd_nolink_bfd_define_start_stop): Likewise. (_bfd_nodynamic_canonicalize_dynamic_symtab): Likewise. (_bfd_nodynamic_get_synthetic_symtab): Likewise. (_bfd_nodynamic_get_dynamic_reloc_upper_bound _bfd_): Likewise. (_bfd_nodynamic_canonicalize_dynamic_reloc): Likewise. * libbfd.c (bfd_false_any): New function. Like bfd_false but accepts one or more arguments. (bfd_true_any): Likewise. (bfd_nullvoidptr_any): Likewise. (bfd_0_any): Likewise. (bfd_0u_any): Likewise. (bfd_0l_any): Likewise. (_bfd_n1_any): Likewise. (bfd_void_any): Likewise. * libbfd.h (extern): Regenerate * aout-target.h (MY_bfd_is_target_special_symbol): Use vararg based dummy function. * aout-tic30.c (tic30_aout_set_arch_mach): Likewise. * binary.c (binary_get_symbol_info): Likewise. * coff-alpha.c (alpha_ecoff_backend_data): Likewise. * coff-mips.c (mips_ecoff_backend_data): Likewise. * coffcode.h (coff_set_alignment_hook): Likewise. (symname_in_debug_hook): Likewise. (bfd_coff_backend_data bigobj_swap_table): Likewise. * elf-m10300.c (elf_backend_omit_section_dynsym): Likewise. * elf32-cr16.c (elf_backend_omit_section_dynsym): Likewise. * elf32-lm32.c (elf_backend_omit_section_dynsym): Likewise. * elf32-m32r.c (elf_backend_omit_section_dynsym): Likewise. * elf32-metag.c (elf_backend_omit_section_dynsym): Likewise. * elf32-score.c (elf_backend_omit_section_dynsym): Likewise. * elf32-score7.c (elf_backend_omit_section_dynsym): Likewise. * elf32-xstormy16.c (elf_backend_omit_section_dynsym): Likewise. * elf32-xtensa.c (elf_backend_omit_section_dynsym): Likewise. * elf64-alpha.c (elf_backend_omit_section_dynsym): Likewise. * elf64-hppa.c (elf_backend_omit_section_dynsym): Likewise. * elf64-ia64-vms.c (elf_backend_omit_section_dynsym): Likewise. * elf64-mmix.c (elf_backend_omit_section_dynsym): Likewise. * elf64-sh64.c (elf_backend_omit_section_dynsym): Likewise. * elfnn-ia64.c (elf_backend_omit_section_dynsym): Likewise. * elfxx-target.h (bfd_elfNN_bfd_debug_info_accumulate): Likewise. (bfd_elfNN_bfd_make_debug_symbol): Likewise. (bfd_elfNN_bfd_merge_private_bfd_data): Likewise. (bfd_elfNN_bfd_set_private_flags): Likewise. (bfd_elfNN_bfd_is_target_special_symbol): Likewise. (elf_backend_init_index_section): Likewise. (elf_backend_allow_non_load_phdr): Likewise. * elfxx-x86.h (elf_backend_omit_section_dynsym): Likewise. * i386msdos.c (msdos_bfd_is_target_special_symbol): Likewise. * ieee.c (ieee_construct_extended_name_table): Likewise. (ieee_write_armap): Likewise. (ieee_write_ar_hdr): Likewise. (ieee_bfd_is_target_special_symbol): Likewise. * ihex.c (ihex_canonicalize_symtab): Likewise. (ihex_bfd_is_target_special_symbol): Likewise. * libaout.h (aout_32_bfd_is_target_special_symbol): Likewise. * libecoff.h (_bfd_ecoff_bfd_is_target_special_symbol): Likewise. (_bfd_ecoff_set_alignment_hook): Likewise. * mach-o-target.c (bfd_mach_o_bfd_is_target_special_symbol): Likewise. * mmo.c (mmo_bfd_is_target_special_symbol): Likewise. * nlm-target.h (nlm_bfd_is_target_special_symbol): Likewise. * oasys.c (oasys_construct_extended_name_table): Likewise. (oasys_write_armap): Likewise. (oasys_write_ar_hdr): Likewise. (oasys_bfd_is_target_special_symbol): Likewise. * pef.c (bfd_pef_bfd_is_target_special_symbol): Likewise. * plugin.c (bfd_plugin_bfd_is_target_special_symbol): Likewise. * ppcboot.c (ppcboot_bfd_is_target_special_symbol): Likewise. * som.c (som_bfd_is_target_special_symbol): Likewise. * srec.c (srec_bfd_is_target_special_symbol): Likewise. * tekhex.c (tekhex_bfd_is_target_special_symbol): Likewise. * verilog.c (verilog_bfd_is_target_special_symbol): Likewise. * versados.c (versados_bfd_is_target_special_symbol): Likewise. (versados_bfd_reloc_name_lookup): Likewise. * vms-alpha.c (vms_bfd_is_target_special_symbol): Likewise. (vms_bfd_define_start_stop): Likewise. (alpha_vms_bfd_is_target_special_symbol): Likewise. * wasm-module.c (wasm_bfd_is_target_special_symbol): Likewise. * xsym.c (bfd_sym_bfd_is_target_special_symbol): Likewise. * elf32-arc.c (get_replace_function): Assign replacement function to func pointer. * elf32-i370.c (i370_noop): Update prototype. gas * config/obj-elf.c (elf_pseudo_table): Remove now redundant casts. (obj_elf_vtable_inherit): Rename to obj_elf_get_vtable_inherit. (obj_elf_vtable_inherit): New stub function that calls obj_elf_get_vtable_inherit. (obj_elf_vtable_entry): Rename to obj_elf_get_vtable_entry. (obj_elf_vtable_entry): New stub function that calls obj_elf_get_vtable_entry. * config/obj-elf.h (obj_elf_vtable_inherit): Update prototype. (obj_elf_vtable_entry) Likewise. (obj_elf_get_vtable_inherit) Likewise. (obj_elf_get_vtable_entry) Likewise. * config/tc-arm.c (md_pseudo_table): Remove now redundant cast. * config/tc-i386c (md_pseudo_table): Likewise. * config/tc-hppa.c (pa_vtable_entry): Call obj_elf_get_vtable_entry. (pa_vtable_inherit): Call obj_elf_get_vtable_inherit. * config/tc-mips.c (s_mips_file): Replace call to dwarf2_get_file with call to dwarf2_get_filename. * dwarf2dbg.c (dwarf2_directive_file): Rename to dwarf2_directive_filename. (dwarf2_directive_file): New stub function that calls dwarf2_directive_filename. * dwarf2dbg.h: Prototype dwarf2_directive_filename. opcodes * metag-dis.c (print_fmmov): Double buffer size to avoid warning about truncation of printing.	8 years ago
Maciej W. Rozycki	87993319a5	WebAssembly: Correct an `index' global shadowing error for pre-4.8 GCC Remove `-Wshadow' compilation errors: cc1: warnings being treated as errors .../bfd/wasm-module.c: In function 'wasm_scan_name_function_section': .../bfd/wasm-module.c:312: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here .../bfd/wasm-module.c: In function 'wasm_register_section': .../bfd/wasm-module.c:494: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here .../bfd/wasm-module.c: In function 'wasm_compute_custom_section_file_position': .../bfd/wasm-module.c:523: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here and: cc1: warnings being treated as errors .../opcodes/wasm32-dis.c: In function 'print_insn_wasm32': .../opcodes/wasm32-dis.c:272: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here make[4]: *** [wasm32-dis.lo] Error 1 which for versions of GCC before 4.8 prevent support for the WebAssembly target from being built. See also GCC PR c/53066. bfd/ * wasm-module.c (wasm_scan_name_function_section): Rename `index' local variable to `idx'. opcodes/ * wasm32-dis.c (print_insn_wasm32): Rename `index' local variable to `function_index'.	8 years ago
Henry Wong	d2159fdc0f	MIPS: Fix encoding for MIPSr6 sigrie instruction. The instruction encoding for the MIPS r6 sigrie instruction seems to be incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp, and dvp), but should be 0x0417xxxx. See ISA reference[1][2]. References: [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies, Inc., Document Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32 REGIMM Encoding of rt Field", p. 452 [2] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies, Inc., Document Number: MD00087, Revision 6.06, December 15, 2016, Table A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581 opcodes/ * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding. gas/ * testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise.	8 years ago
Nick Clifton	f174ef9fb2	Updated Brazillian portuguese and Russian translation	8 years ago
Igor Tsimbalist	be3a8dca2d	Enable Intel PCONFIG instruction. Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel PCONFIG instruction. gas/ * config/tc-i386.c (cpu_arch): Add .pconfig. * doc/c-i386.texi: Document .pconfig. * testsuite/gas/i386/i386.exp: Add PCONFIG tests. * testsuite/gas/i386/pconfig-intel.d: New test. * testsuite/gas/i386/pconfig.d: Likewise. * testsuite/gas/i386/pconfig.s: Likewise. * testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.s: Likewise. opcodes/ * i386-dis.c (enum): Add pconfig. * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. (cpu_flags): Add CpuPCONFIG. * i386-opc.h (enum): Add CpuPCONFIG. (i386_cpu_flags): Add cpupconfig. * i386-opc.tbl: Add PCONFIG instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.	8 years ago
Igor Tsimbalist	3233d7d074	Enable Intel WBNOINVD instruction. Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel WBNOINVD instruction. gas/ * config/tc-i386.c (cpu_arch): Add .wbnoinvd. * doc/c-i386.texi: Document .wbnoinvd. * testsuite/gas/i386/i386.exp: Add WBNOINVD tests. * testsuite/gas/i386/wbnoinvd-intel.d: New test. * testsuite/gas/i386/wbnoinvd.d: Likewise. * testsuite/gas/i386/wbnoinvd.s: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F09. * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. (cpu_flags): Add CpuWBNOINVD. * i386-opc.h (enum): Add CpuWBNOINVD. (i386_cpu_flags): Add cpuwbnoinvd. * i386-opc.tbl: Add WBNOINVD instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.	8 years ago
Jim Wilson	e925c834ec	RISC-V: Fix bug in prior addi/c.nop patch. gas/ * config/tc-riscv.c (validate_riscv_insn) <'z'>: New. (riscv_ip) <'z'>: New. opcodes/ * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.	8 years ago
Igor Tsimbalist	d777820bf5	Replace CET bit with IBT and SHSTK bits. The latest specification for Intel CET technology defined two new bits instead of previously used CET bit. These are IBT and SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits. gas/ * config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk. (cpu_noarch): Add noibt, noshstk. (parse_insn): Change cpucet to cpuibt. * doc/c-i386.texi: Delete .cet. Add .ibt, .shstk. * testsuite/gas/i386/cet-ibt-inval.l: New test. * testsuite/gas/i386/cet-ibt-inval.s: Likewise. * testsuite/gas/i386/cet-shstk-inval.l: Likewise. * testsuite/gas/i386/cet-shstk-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. (cpu_flags): Add CpuIBT, CpuSHSTK. * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. (i386_cpu_flags): Add cpuibt, cpushstk. * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.	8 years ago
Nick Clifton	f6efed019b	Update translations for various binutils components. ld * po/pt_BR.po: Updated Brazilian Portugese translation. opcodes * po/pt_BR.po: Updated Brazilian Portugese translation. * po/de.po: Updated German translation. gas * po/fr.po: Updated French translation. binutils* po/fr.po: Updated French translation.	8 years ago
Jim Wilson	2721d702a0	RISC-V: Add support for addi that compresses to c.nop. gas/ * testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop. * testsuite/gas/riscv/c-zero-imm.d: Likewise. opcodes/ * riscv-opc.c (match_c_nop): New. (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.	8 years ago
Nick Clifton	616dcb87ab	Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodes	8 years ago
Nick Clifton	3957a4963f	Update pot files	8 years ago
Nick Clifton	769c7ea507	Bump version number to 2.30.51 bfd/ * version.m4: Bump version to 2.30.51 * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.	8 years ago
Nick Clifton	faf766e317	Add note about 2.30 branch creation to changelogs	8 years ago
Igor Tsimbalist	888a89da7f	Remove VL variants for 4FMAPS and 4VNNIW insns. AVX512_4FMAPS and AVX512_4VNNIW insns are marked as having AVX512VL variants. That is wrong as SDM doesn't define such instructions. The patch removes these VL variants. gas/ * testsuite/gas/i386/avx512_4fmaps-warn.l: Change xmm to zmm. * testsuite/gas/i386/avx512_4fmaps-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Delete _vl tests for 4fmaps an 4vnniw tests. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s: Likewise. opcodes/ * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns. * i386-tbl.h: Regenerate.	8 years ago
Jan Beulich	cbda583ada	x86: fix Disp8 handling for scalar AVX512_4FMAPS insns Just like their packed counterparts the memory operand is always 16 bytes wide, and the Disp8 scaling is the same for all of them. (As a side note: I'm also surprised by there being AVX512VL variants of these as well as the AVX512_4VNNIW ones - the SDM doesn't define any such.) Adjust the test cases also for the packed forms to actually live up to their promise of testing correct Disp8 encoding.	8 years ago
Jan Beulich	c9e9227878	x86: fix Disp8 handling for AVX512VL VPCMP{B,W} variants In commit `2645e1d079` ("x86: add support for AVX-512 VPCMP{B,W} pseudo-ops") I screwed up the Disp8MemShift values of the AVX512VL variants.	8 years ago
Jim Wilson	35fd2b2bcf	RISC-V: Disassemble x0 based addresses as 0. gas/ * testsuite/gas/riscv/auipc-x0.d: New. * testsuite/gas/riscv/auipc-x0.s: New. opcodes/ * riscv-dis.c (maybe_print_address): If base_reg is zero, then the hi_addr value is zero.	8 years ago
James Greenhalgh	91d8b67066	[Arm] Add CSDB instruction CSDB is a new instruction which Arm has defined. As it shares the encoding space with NOP instructions, it is available from Armv3 in Arm mode, and Armv6T2 in Thumb mode. OK? If so, please commit on my behalf as I don't have commit rights over here. Thanks, James --- opcodes/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * arm-dis.c (arm_opcodes): Add csdb. (thumb32_opcodes): Add csdb. gas/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above in Arm execution state, and Armv6T2 and above in Thumb execution state. * testsuite/gas/arm/csdb.s: New. * testsuite/gas/arm/csdb.d: New. * testsuite/gas/arm/thumb2_it_bad.l: Add csdb. * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.	8 years ago
James Greenhalgh	be2e7d9541	Add support for the AArch64's CSDB instruction. CSDB is a new instruction which Arm has defined. It has the same encoding as HINT #0x14 and is available at all architecture levels. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.d: Update expected results to expect CSDB.	8 years ago
H.J. Lu	704a705d7a	x86: Properly encode vmovd with 64-bit memeory For historical reason, we allow movd/vmovd with 64-bit register and memeory operands. But for vmovd, we failed to handle 64-bit memeory operand. This has been gone unnoticed since AT&T syntax always treats memory operand as 32-bit memory. This patch properly encodes vmovd with 64-bit memeory operands. It also removes AVX512 vmovd with 64-bit operands since GCC has case TYPE_SSEMOV: switch (get_attr_mode (insn)) { case MODE_DI: /* Handle broken assemblers that require movd instead of movq. / if (!HAVE_AS_IX86_INTERUNIT_MOVQ && (GENERAL_REG_P (operands[0]) \|\| GENERAL_REG_P (operands[1]))) return "%vmovd\t{%1, %0\|%0, %1}"; return "%vmovq\t{%1, %0\|%0, %1}"; and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't generate AVX512 vmovd with 64-bit operand. gas/ PR gas/22681 testsuite/gas/i386/i386.exp: Run x86-64-movd and x86-64-movd-intel. * testsuite/gas/i386/x86-64-movd-intel.d: New file. * testsuite/gas/i386/x86-64-movd.d: Likewise. * testsuite/gas/i386/x86-64-movd.s: Likewise. opcodes/ PR gas/22681 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. Remove AVX512 vmovd with 64-bit operands. * i386-tbl.h: Regenerated.	8 years ago
Jim Wilson	35eeb78fa9	RISC-V: Print symbol address for jalr w/ zero offset. ld/ * testsuite/ld-riscv-elf/disas-jalr.d: New. * testsuite/ld-riscv-elf/disas-jalr.s: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run new testcase. opcodes/ * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a jalr.	8 years ago
Alan Modra	219d1afa89	Update year range in copyright notice of binutils files	8 years ago
Alan Modra	1e56386871	ChangeLog rotation	8 years ago
Jan Beulich	1508bbf535	x86: partial revert of `10c17abdd0` Other than the variables in tc-i386.c using them, OPERAND_TYPE_REGYMM and OPERAND_TYPE_REGZMM they aren't entirely unused. No need to update i386-init.h though, as it mistakenly wasn't updated by the original commit.	8 years ago
Jim Wilson	21a186f280	RISC-V: Add compressed instruction hints, and a few misc cleanups. gas/ * config/tc-riscv.c (risc_ip) <o>: Add comment. * testsuite/gas/riscv/c-nonzero-imm.d, * testsuite/gas/riscv/c-nonzero-imm.l, * testsuite/gas/riscv/c-nonzero-imm.s, * testsuite/gas/riscv/c-nonzero-reg.d, * testsuite/gas/riscv/c-nonzero-reg.l, * testsuite/gas/riscv/c-nonzero-reg.s, * testsuite/gas/riscv/c-zero-imm-64.d, * testsuite/gas/riscv/c-zero-imm-64.s, * testsuite/gas/riscv/c-zero-imm.d, testsuite/gas/riscv/c-zero-imm.s, * testsuite/gas/riscv/c-zero-reg.d, * testsuite/gas/riscv/c-zero-reg.s: New. opcodes/ * riscv-opc.c (match_c_add_with_hint, match_c_lui_with_hint): New. (riscv_opcodes) <li>: Delete "d,0" line. Change Cj to Co. <andi, and, add, addiw, addw, c.addi>: Change Cj to Co. <add>: Add explanatory comment for 4-operand add instruction. <c.nop>: Add support for immediate operand. <c.mv, c.add>: Use match_c_add_with_hint instead of match_c_add. <c.lui>: Use match_c_lui_with_hint instead of match_c_lui. <c.li, c.slli>: Use match_opcode instead of match_rd_nonzero.	8 years ago
Tamar Christina	00c2093f69	Correct disassembly of dot product instructions. Dot products deviate from the normal disassembly rules for lane indexed instruction. Their canonical representation is in the form of: v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote that these instructions select 4x 1 byte elements instead of a single 1 byte element. Previously we were disassembling them following the normal rules, this patch corrects the disassembly. gas/ PR gas/22559 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B. * gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly. include/ PR gas/22559 * aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B. opcodes/ PR gas/22559 * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant. * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.	8 years ago
Tamar Christina	a3b3345ae6	Add support for V_4B so we can properly reject it. Previously parse_vector_type_for_operand was changed to allow the use of 4b register size for indexed lane instructions. However this had the unintended side effect of also allowing 4b for normal vector registers. Because this support was only partial the rest of the tool silently treated 4b as 8b and continued. This patch adds full support for 4b so it can be properly distinguished from 8b and the correct errors are generated. With this patch you still can't encode any instruction which actually requires v<num>.4b but such instructions don't exist so to prevent needing a workaround in get_vreg_qualifier_from_value this was just omitted. gas/ PR gas/22529 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B. * gas/testsuite/gas/aarch64/pr22529.s: New. * gas/testsuite/gas/aarch64/pr22529.d: New. * gas/testsuite/gas/aarch64/pr22529.l: New. include/ PR gas/22529 * opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B. opcodes/ PR gas/22529 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.	8 years ago
Jan Beulich	10c17abdd0	x86: fold certain AVX and AVX2 templates Just like for instructions in GPRs, there's no need to have separate templates for otherwise identical insns acting on XMM or YMM registers (or memory of the same size).	8 years ago
Jan Beulich	1b54b8d7e4	x86: fold RegXMM/RegYMM/RegZMM into RegSIMD ... qualified by their respective sizes, allowing to drop FirstXmm0 at the same time.	8 years ago
Jan Beulich	ca0d63fe07	x86: drop FloatReg and FloatAcc Express them as Reg\|Tbyte and Acc\|Tbyte respectively.	8 years ago
Jan Beulich	dc821c5f9a	x86: replace Reg8, Reg16, Reg32, and Reg64 Use a combination of a single new Reg bit and Byte, Word, Dword, or Qword instead. Besides shrinking the number of operand type bits this has the benefit of making register handling more similar to accumulator handling (a generic flag is being accompanied by a "size qualifier"). It requires, however, to split a few insn templates, as it is no longer correct to have combinations like Reg32\|Reg64\|Byte. This slight growth in size will hopefully be outweighed by this change paving the road for folding a presumably much larger number of templates later on.	8 years ago
Dimitar Dimitrov	fbc2255575	Fix disassembly for PowerPC * disassemble.c (disassemble_init_for_target): Don't put PRU between powerpc and rs6000 cases.	8 years ago
Jan Beulich	93b71a2666	x86: drop stray CheckRegSize uses They are relevant only when multiple operands permit registers: operand_type_register_match() returns true if either operand is not a register one. IOW grep -i CheckRegSize i386-opc.tbl \| grep -Ev "(Reg[8136]\|Acc).,.(Reg\|Acc)" should produce no output.	8 years ago

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2777 Commits (f2f6a710f46e3e7b357128d907002945751afcfd)