binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Alan Modra	f9a6a8f09d	PR27116, Spelling errors found by Debian style checker PR 27116 bfd/ * xcofflink.c: Correct spelling in comments. binutils/ * coffgrok.c (do_type): Correct spelling of auxiliary in errors. * doc/binutils.texi: Correct grammar. * readelf.c (process_version_sections): Correct spelling of auxiliary in warning. * testsuite/binutils-all/vax/objdump.exp: Comment grammar fix. config/ * override.m4: Correct comment grammar. gas/ * config/tc-i386.c: Correct comment spelling. * config/tc-riscv.c: Likewise. * config/tc-s390.c: Correct comment grammar. * doc/c-i386.texi: Correct spelling. * doc/c-s390.texi: Correct grammar. gold/ * tilegx.cc: Correct comment spelling. gprof/ * README: Correct grammar. * gprof.texi: Likewise. include/ * coff/internal.h: Correct comment spelling. * coff/sym.h: Likewise. * opcode/aarch64.h: Likewise. ld/ * configure.tgt: Correct comment grammar. * emultempl/m68hc1xelf.em: Likewise. * ld.texi: Correct grammar.	5 years ago
Alan Modra	5c1ad6b5bb	ChangeLog rotation	9 years ago
Alan Modra	ae4c0df4b6	Fix riscv breakage * disassemble.c (disassembler): Add break accidentally removed by PRU patch.	9 years ago
Dimitar Dimitrov	1114684964	PRU Opcode Port opcodes/ * Makefile.am: Add PRU source files. * configure.ac: Add PRU target. * disassemble.c (disassembler): Register PRU arch. * pru-dis.c: New file. * pru-opc.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>	9 years ago
Yao Qi	0a7e10188e	Return 'int' rather than 'unsigned short' in avrdis_opcode avrdis_opcode return type is unsigned short, but -1 at the end of this function is returned. Additionally, print_insn_avr doesn't handle when -1 (in case of memory error) is returned from avrdis_opcode. This patch changes avrdis_opcode returning int indicating the error, and adds a new argument for instruction we got on success. The opcode is 16-bit, so I change local variables type to uint16_t, and include "bfd_stdint.h" as a result. On memory error, print_insn_avr returns -1, which is a common convention among most of print_insn_$ARCH functions. opcodes: 2016-12-29 Yao Qi <yao.qi@linaro.org> * avr-dis.c: Include "bfd_stdint.h" (avrdis_opcode): Change return type to int, add argument insn. Set *INSN on success. (print_insn_avr): Check return value of avrdis_opcode, and return -1 on error.	9 years ago
Alan Modra	0fa6f7cee7	Check bfd support for bfd_mips_elf_get_abiflags in mips make rule The previous scheme with a dependency in opcodes on libbfd.la broke "make distclean". * configure.ac: Revert 2016-12-23. * Makefile.am: Likewise. (MIPS_DEFS): Define. (mips-dis.lo): Add rule. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * config.in: Regenerate. * configure: Regenerate.	9 years ago
Maciej W. Rozycki	5284e471d5	MIPS16: Add ASMACRO instruction support Add ASMACRO instruction support as per the MIPS16e ASE architecture specifications [1][2], completing MIPS16e instruction set support. [1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65 [2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66 include/ * opcode/mips.h: Document `0', `1', `2', `3', `4' and `s' operand codes. opcodes/ * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3', `4' and `s' operand codes. (mips16_opcodes): Add "asmacro" entry. binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: Update for ASMACRO support. gas/ * testsuite/gas/mips/mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-asmacro.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.	9 years ago
Maciej W. Rozycki	bdd152861c	MIPS16: Simplify extended operand handling Simplify extended operand handling and only specially process immediates which require bit shuffling, using the generic operand insertion and extraction handlers for the '<' (5-bit shift amount) operand code in particular. Require the least significant bit of all extended operand forms to be (artificially) set to 0 for their special processing to trigger. gas/ * config/tc-mips.c (mips16_immed): Limit `mips16_immed_extend' use to operands whose LSB position is zero. opcodes/ * mips-dis.c (print_mips16_insn_arg): Simplify processing of extended operands. * mips16-opc.c (decode_mips16_operand): Switch the extended form of the `<' operand type to LSB position 22.	9 years ago
Maciej W. Rozycki	d8722d7641	MIPS16: Reassign `0' and `4' operand codes Replace `0' and `4' operand codes with `.' and `F' respectively to free up the `0'-`4' consecutive range. No functional change. gas/ * config/tc-mips.c (mips16_macro_build): Replace `0' and `4' operand codes with `.' and `F' respectively. (mips16_macro): Likewise. include/ * opcode/mips.h: Replace `0' and `4' operand codes with `.' and `F' respectively. opcodes/ * mips16-opc.c (decode_mips16_operand): Replace `0' and `4' operand codes with `.' and `F' respectively. (mips16_opcodes): Likewise.	9 years ago
Maciej W. Rozycki	0674ee5dad	MIPS16: Handle non-extensible instructions correctly Identify non-extensible instructions in the MIPS16 opcode table and disallow their use with the `.e' instruction size suffix in assembly and do not interpret any EXTEND prefix present as a part of the instruction in disassembly. According to all versions of the MIPS16 ASE specifications the following instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R, I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e ASE specifications it has been further clarified what was previously implied, that non-extesiable instructions when preceded with an EXTEND prefix must cause a Reserved Instruction exception [3][5]. Therefore in the presence of an EXTEND prefix none of these instructions are supposed to be handled as extended instructions and supporting these forms in disassembly causes confusion, and in the case of the RRR major opcode it also clashes with the ASMACRO encoding. References: [1] "Product Description, MIPS16 Application-Specific Extension", Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16 Instruction Set Summary", p. 5 [2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10 [3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39 [4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49 [5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41 [6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51 include/ * opcode/mips.h (INSN2_SHORT_ONLY): New macro. gas/ * config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix instruction size override for INSN2_SHORT_ONLY opcode table entries. * testsuite/gas/mips/mips16-extend-swap.d: Adjust output. * testsuite/gas/mips/mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-insn-e.s: New test source. * testsuite/gas/mips/mips16-insn-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix matching for INSN2_SHORT_ONLY opcode table entries. * mips16-opc.c (SH): New macro. (mips16_opcodes): Set SH in `pinfo2' for non-extensible instruction entries: "nop", "addu", "and", "break", "cmp", "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu", "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv", "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j", "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg", "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu", "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb", "seh", "sew", "zeb", "zeh", "zew" and "extend". binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: New test. * testsuite/binutils-all/mips/mips16-extend-insn.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.	9 years ago
Maciej W. Rozycki	b2805ed554	MIPS16: Remove "extended" BREAK/SDBBP handling Remove special casing for the `6' operand code used for the embedded trap code of the BREAK and the SDBBP instructions to support supposedly extended forms of these instructions. According to all versions of the MIPS16 ASE specifications these instructions are not extensible [1][2][3][4][5][7][8][10][11], and as from revision 2.50 of the MIPS16e ASE specifications it has been further clarified what was previously implied, that non-extesiable instructions when preceded with an EXTEND prefix must cause a Reserved Instruction exception [5][6][9][10]. Therefore supposedly extended BREAK and SDBBP instructions do not serve their purpose anymore as they do not cause a Bp and a Debug exception respectively and supporting these forms in disassembly only causes confusion. References: [1] "Product Description, MIPS16 Application-Specific Extension", Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16 Instruction Set Summary", p. 5 [2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10 [3] same, Table 18. "Extendable MIPS16 Instructions", p. 24 [4] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Table 3.8 "MIPS16e Special Instructions", p. 38 [5] same, Section 3.11 "MIPS16e Extensible Instructions, p. 41 [6] same, Table 3.15 "MIPS16e Extensible Instructions", p. 41 [7] same, Table 3.24 "MIPS16e RR Encoding of the Funct Field", p. 49 [8] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Table 1.8 "MIPS16e Special Instructions", p. 39 [9] same, Section 1.11 "MIPS16e Extensible Instructions", p. 42 [10] same, Table 1.15 "MIPS16e Extensible Instructions", pp. 42-43 [11] same, Table 1.24 "MIPS16e RR Encoding of the Funct Field", p. 50 gas/ * config/tc-mips.c (match_mips16_insn): Remove the `6' operand code special case and its associated comment. opcodes/ * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended encoding support.	9 years ago
Maciej W. Rozycki	645c455650	MIPS16/GAS: Disallow EXTEND delay-slot scheduling Do not allow any explicitly coded EXTEND instruction to be automatically scheduled into a jump delay slot, as an EXTEND prefix is coupled with the next regular MIPS16 instruction and therefore swapping it with a jump would change program's semantics; EXTEND is not architecturally allowed to be present in a jump delay slot anyway. opcodes/ * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for "extend". gas/ * testsuite/gas/mips/mips16-extend-swap.d: New test. * testsuite/gas/mips/mips16-extend-swap.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.	9 years ago
Maciej W. Rozycki	9e76c212e6	opcodes: Use autoconf to check for `bfd_mips_elf_get_abiflags' in BFD Fix a regression introduced with commit `5e7fc731f8` ("MIPS/opcodes: Also set disassembler's ASE flags from ELF structures"), further updated with commit `4df995c771` ("MIPS/opcodes: Also set disassembler's ASE flags from ELF structures"), and use autoconf to check for the presence of `bfd_mips_elf_get_abiflags' in BFD. opcodes/ * mips-dis.c (set_default_mips_dis_options): Use HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the call to `bfd_mips_elf_get_abiflags'. * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD. * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'. * aclocal.m4: Regenerate. * configure: Regenerate. * config.in: Regenerate. * Makefile.in: Regenerate.	9 years ago
Tristan Gingold	99b5dbf2e7	Bump version to 2.28.51 bfd/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * version.m4: Bump version to 2.28.51 * configure: Regenerate. binutils/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gas/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gprof/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. ld/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. opcodes/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate.	9 years ago
Tristan Gingold	e0e7a9d436	Regenerate pot files.	9 years ago
Alan Modra	b2c6190bfc	ChangeLog formatting fixes	9 years ago
Andrew Waterman	58a6d3c9d8	Avoid creating symbol table entries for registers Instructions like "jal t0, foo" were erroneously creating symbol table entries for t0 as well as foo, which causes linking problems. Fix by reordering instruction alternatives so that t0 is first attempted to be parsed as a register, rather than as a symbol. * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.	9 years ago
Maciej W. Rozycki	11dd08e9a0	MIPS16/opcodes: Respect ISA and ASE in disassembly Limit MIPS16 instruction disassembly according to the ISA level and ASE set selected, as with the regular MIPS and microMIPS instruction sets. Retain the property of `objdump -m mips:16' disassembling all MIPS16 instructions however, regardless of any ISA level recorded in the binary examined. To validate the disassembler use the GAS test suite for its convenience of running tests across multiple ISAs, even though placing the tests in the binutils test suite would be more appropriate. Adjust the single binutils test which depends on 64-bit instruction disassembly to have the ISA level required actually recorded in the binary examined. opcodes/ * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry. (print_insn_mips16): Check opcode entries for validity against the ISA level and ASE set selected. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module' rather than `.set' to set the ISA level. gas/ * testsuite/gas/mips/mips16-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-sub.d: New test. * testsuite/gas/mips/mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-sub.s: New test source. * testsuite/gas/mips/mips16e-sub.s: New test source. * testsuite/gas/mips/mips16e-64-sub.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.	9 years ago
Maciej W. Rozycki	7fd5392005	MIPS16: Switch to 32-bit opcode table interpretation Switch to 32-bit MIPS16 opcode table entry interpretation, similar to how the microMIPS opcode table is handled, for both the `match' and `mask' fields, removing special casing for JAL and JALX instructions and their `a' and `i' operand codes throughout, while retaining automatic processing of extendable opcodes in assembly and disassembly. In assembly disallow size enforcement suffixes as appropriate: `.t' for both 32-bit instructions and macros and `.e' for macros only, making macro handling consistent with the microMIPS instruction set. In disassembly fully decode EXTEND prefixes prepended to unsupported instruction encodings (according to the ISA selection) rather than dumping them as hexadecimal data along with the following instruction, removing all special casing for the EXTEND prefix and making its handling rely on its opcode table entry, except where it is considered a part of an extendable instruction. include/ * opcode/mips.h (mips_opcode_32bit_p): New inline function. gas/ * config/tc-mips.c (micromips_insn_length): Use `mips_opcode_32bit_p'. (is_size_valid): Adjust description. (is_size_valid_16): New function. (validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16 operand decoding. (validate_mips16_insn): Remove `a' and `i' operand code special casing, use `mips_opcode_32bit_p' to determine instruction width. (append_insn): Adjust forced MIPS16 instruction size determination. (match_mips16_insn): Likewise. Don't shift the instruction's opcode with the `a' and `i' operand codes. Use `mips_opcode_32bit_p' in operand decoding. (match_mips16_insns): Check for forced instruction size's validity. (mips16_ip): Don't force instruction size in the `noautoextend' mode. * testsuite/gas/mips/mips16-jal-e.d: New test. * testsuite/gas/mips/mips16-jal-t.d: New test. * testsuite/gas/mips/mips16-macro-e.d: New test. * testsuite/gas/mips/mips16-macro-t.d: New test. * testsuite/gas/mips/mips16-jal-t.l: New stderr output. * testsuite/gas/mips/mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16-jal-e.s: New test source. * testsuite/gas/mips/mips16-jal-t.s: New test source. * testsuite/gas/mips/mips16-macro-e.s: New test source. * testsuite/gas/mips/mips16-macro-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and `insn' together, with `extend' as the high-order 16 bits. (match_kind): New enum. (print_insn_mips16): Rework for 32-bit instruction matching. Do not dump EXTEND prefixes here. * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end. Recode `match' and `mask' fields as 32-bit in absolute "jal" and "jalx" entries. binutils/ * testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust test for separate EXTEND prefix disassembly.	9 years ago
Maciej W. Rozycki	4ebce1a0a5	MIPS16/opcodes: Correct 64-bit macros' ISA membership Limit the DDIV, DDIVU, DREM, DREMU and DSUBU macros to the MIPS III rather than MIPS I ISA. These macros expand to machine code sequences including 64-bit instructions which require a 64-bit ISA. Entries for those instructions are already correctly marked, however the marking is ignored if entries are used in the process of macro expansion rather than directly, making it possible to indirectly produce 64-bit machine code even when output requested has been limited to a 32-bit ISA. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu" INSN_MACRO entries. gas/ * testsuite/gas/mips/mips16-macro.l: New list test. * testsuite/gas/mips/mips.exp: Run the new test.	9 years ago
Maciej W. Rozycki	c97dda72b9	MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membership Limit the `SD ra, offset(sp)' instruction (I64/SDRASP major/minor opcode) to the MIPS III rather than MIPS I ISA. This is a 64-bit instruction requiring a 64-bit ISA. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the SP-relative "sd"/$ra entry (SDRASP minor opcode). gas/ * testsuite/gas/mips/mips16-sdrasp.d: New test. * testsuite/gas/mips/mips16-sdrasp.l: New stderr output. * testsuite/gas/mips/mips16-sdrasp.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.	9 years ago
Andrew Waterman	3e67a37820	Correct assembler mnemonic for RISC-V aqrl AMOs sc is a misnomer, because they aren't inherently sc. * riscv-opc.c (riscv_opcodes): Rename the ".sc" instructions to ".aqrl".	9 years ago
Andrew Waterman	04386d9ed5	Fix disassembly of RISC-V CSR instructions under -Mno-aliases This fixes https://github.com/riscv/riscv-binutils-gdb/issues/36. * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as INSN_ALIAS.	9 years ago
Andrew Waterman	755c5297bd	Add canonical JALR for RISC-V jalr rd,offset(rs1) rather than jalr rd,rs1,offset This matches the format of other instructions. * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)" format.	9 years ago
Andrew Waterman	2922d21da1	Re-work RISC-V gas flags: now we just support -mabi and -march We've decided to standardize on two flags for RISC-V: "-march" sets the target architecture (which determines which instructions can be generated), and "-mabi" sets the target ABI. We needed to rework this because the old flag set didn't support soft-float or single-float ABIs, and didn't support an x32-style ABI on RISC-V. Additionally, we've changed the behavior of the -march flag: it's now a lot stricter and only parses things we can actually understand. Additionally, it's now lowercase-only: the rationale is that while the RISC-V ISA manual specifies that ISA strings are case-insensitive, in Linux-land things are usually case-sensitive. Since this flag can be used to determine library paths, we didn't want to bake some case-insensitivity in there that would case trouble later. This patch implements these two new flags and removes the old flags that could conflict with these. There wasn't a RISC-V release before, so we want to just support a clean flag set. include/ * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define. (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define. (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define. (EF_RISCV_FLOAT_ABI_QUAD): Define. bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT. binutils/ * readelf.c (get_machine_flags): Use EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of EF_RISCV_{SOFT,HARD}_FLOAT. gas/ * config/tc-riscv.h (xlen): Delete. * config/tc-riscv.c (xlen): Make static. (abi_xlen): New variable. (options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC} with OPTION_MABI. (md_longopts): Likewise. (md_parse_option): Likewise. (riscv_elf_final_processing): Likewise. * doc/as.texinfo (Target RISC-V options): Likewise. * doc/c-riscv.texi (OPTIONS): Likewise. * config/tc-riscv.c (float_mode): Removed. (float_abi): New type, specifies the floating-point ABI. (riscv_set_abi): New function. (riscv_add_subset): Only allow lower-case ISA names and require them to start with "rv". (riscv_after_parse_args): Likewise. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's XLEN when none is provided.	9 years ago
Andrew Waterman	1d65abb5e2	Formatting changes for RISC-V This is a mixed bag of format changes: * Replacing constants with macros (0xffffffff with MINUS_ONE, for example). There's one technically functional change in here (some MINUS_ONEs are changed to 0), but it only changes the behavior of an otherwise-unused field. * Using 0 instead of 0x0 in the relocation table. * There were some missing spaces before parens, the spaces have been added. * A handful of comments are now more descriptive. * A bunch of whitespace-only changes, mostly alignment and brace newlines. bfd/ * elfnn-riscv.c: Formatting and comment fixes throughout. * elfxx-riscv.c: Likewise. (howto_table): Change the src_mask field from MINUS_ONE to 0 for R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32, R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64. opcodes/ * riscv-opc.c: Formatting fixes. gas/ * config/tc-riscv.c: Formatting and comment fixes throughout.	9 years ago
Alan Modra	dd1d944e23	Add opcodes RISC-V dependencies * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.	9 years ago
Maciej W. Rozycki	91068ec6ae	MIPS/opcodes: Only examine ELF file structures if SYMTAB_AVAILABLE Correct commit `640c0ccdc9` ("some objdump -M options, better reg dumps"), <https://sourceware.org/ml/binutils/2002-12/msg00706.html>, and only execute code setting up disassembler options based on ELF file structures if SYMTAB_AVAILABLE is set. opcodes/ * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]: Only examine ELF file structures here.	9 years ago
Maciej W. Rozycki	4df995c771	MIPS/opcodes: Only call `bfd_mips_elf_get_abiflags' if BFD64 Complement commit `5e7fc731f8` ("MIPS/opcodes: Also set disassembler's ASE flags from ELF structures") and fix an `--enable-targets=all' GDB build regression on 32-bit hosts where the MIPS target is a secondary: ../opcodes/libopcodes.a(mips-dis.o): In function `set_default_mips_dis_options': mips-dis.c:(.text+0x906): undefined reference to `bfd_mips_elf_get_abiflags' collect2: error: ld returned 1 exit status make[2]: *** [gdb] Error 1 by avoiding making a call to the `bfd_mips_elf_get_abiflags' function, which is not available, because there is no MIPS/ELF BFD included in 32-bit BFD builds. This call is only made from a conditional code block guarded by a check against `bfd_target_elf_flavour', which is dead in such a configuration, however cannot be optimized away by the compiler. Also some other MIPS BFDs may be available, such as a.out, ECOFF or PE, so the disassembler has to remain functional. opcodes/ * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call `bfd_mips_elf_get_abiflags' here.	9 years ago
Nick Clifton	db7b55faa1	Fix compile time warning building arm-dis.c	9 years ago
Maciej W. Rozycki	5e7fc731f8	MIPS/opcodes: Also set disassembler's ASE flags from ELF structures Respect any ASE flags recorded in ELF file structures for the purpose of selecting instructions to be disassembled, preventing code from being hex-dumped even though having been clearly indicated as valid at the assembly time. Use date from the MIPS ABI flags structure if present, and otherwise there may be an MDMX ASE flag set in the ELF file header. For backwards compatibility only set extra flags and do not clear any, preserving all previously set by the architecture selected to be disassembled for. include/ * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct typedef as `elf_internal_abiflags_v0'. bfd/ * bfd-in.h (elf_internal_abiflags_v0): New struct declaration. (bfd_mips_elf_get_abiflags): New prototype. * elfxx-mips.c (bfd_mips_elf_get_abiflags): New function. * bfd-in2.h: Regenerate. opcodes/ * mips-dis.c (mips_convert_abiflags_ases): New function. (set_default_mips_dis_options): Also infer ASE flags from ELF file structures. binutils/ * testsuite/binutils-all/mips/mips-ase-1.d: New test. * testsuite/binutils-all/mips/mips-ase-2.d: New test. * testsuite/binutils-all/mips/mips-ase-3.d: New test. * testsuite/binutils-all/mips/mips-ase-1.s: New test source. * testsuite/binutils-all/mips/mips-ase-2.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.	9 years ago
Maciej W. Rozycki	8184783a40	MIPS/opcodes: Reorder ELF file header flag handling in disassembler Move ELF file header flag interpretation code, used to set disassembler options, beyond architecture setup. No functional change as the effects of both code sections are disjoint from each other, but this provides for a further expansion of ELF file header flag interpretation. opcodes/ * mips-dis.c (set_default_mips_dis_options): Reorder ELF file header flag interpretation code.	9 years ago
Maciej W. Rozycki	353abf7c10	MIPS16: Fix SP-relative SD instruction annotation Fix the annotation of SP-relative SD instructions incorrectly marked as reading from the PC rather than SP, which in turn prevented their 16-bit forms from being scheduled into jump delay slots. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in `pinfo2' with SP-relative "sd" entries. gas/ * testsuite/gas/mips/mips16-sprel-swap.d: New test. * testsuite/gas/mips/mips16-sprel-swap.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.	9 years ago
Maciej W. Rozycki	63e014fccd	MIPS16/opcodes: Fix and clarify MIPS16e commentary Correct the note about JALRC/JRC being compact jumps rather than branches, and add a reference from where the remaining MIPS16e additions live and the jumps used to be too, complementing commit `ceb94aa50d` ("Update insn_mo when converting to a MIPS16e compact jump"), <https://sourceware.org/ml/binutils/2011-06/msg00369.html>. opcodes/ * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e compact jumps.	9 years ago
Renlin Li	a6a5175474	[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field The internal CN register representation for coprocessor fields used in aarch64 sys, sysl instructions are removed in this patch. After the change, those fields are represented as immediate. Related checks are added as well. opcodes/ * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range qualifier. (operand_general_constraint_met_p): Remove case for CP_REG. (aarch64_print_operand): Print CRn, CRm operand using imm field. * aarch64-tbl.h (QL_SYS): Use CR qualifier. (QL_SYSL): Likewise. (aarch64_opcode_table): Change CRn, CRm operand class and type. * aarch64-opc-2.c : Regenerate. * aarch64-asm-2.c : Likewise. * aarch64-dis-2.c : Likewise. include/ * opcode/aarch64.h (aarch64_operand_class): Remove AARCH64_OPND_CLASS_CP_REG. (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn, AARCH64_OPND_Cm to AARCH64_OPND_CRm. (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier. gas/ * config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register. (get_reg_expected_msg): Remove CN register case. (parse_operands): rewrite parser for CRn, CRm operand. (reg_names): Remove CN register. * testsuite/gas/aarch64/diagnostic.s: Add a new test case. * testsuite/gas/aarch64/diagnostic.l: Adjust error message.	9 years ago
Yao Qi	029e9d52de	Handle memory error in print_insn_rx Nowadays, memory error in rx disassembly is not handled, so if I start a fresh GDB, and disassemble, (gdb) set architecture rx The target architecture is assumed to be rx (gdb) disassemble 0x0,+4 Dump of assembler code from 0x0 to 0x4: 0x00000000: brk 0x00000001: brk 0x00000002: brk 0x00000003: brk the output is wrong. This patch adds code to call dis->memory_error_func on memory error, and longjmp to print_insn_rx. With this patch applied, (gdb) set architecture rx The target architecture is assumed to be rx (gdb) disassemble 0,+4 Dump of assembler code from 0x0 to 0x4: 0x00000000: Cannot access memory at address 0x0 opcodes: 2016-12-12 Yao Qi <yao.qi@linaro.org> * rx-dis.c: Include <setjmp.h> (struct private): New. (rx_get_byte): Check return value of read_memory_func, and call memory_error_func and OPCODES_SIGLONGJMP on error. (print_insn_rx): Call OPCODES_SIGSETJMP.	9 years ago
Yao Qi	3a0b8f7ddb	Handle memory error in print_insn_rl78_common Nowadays, memory error in rl78 disassembly is not handled, so if I start a fresh GDB, and disassemble, (gdb) set architecture rl78 The target architecture is assumed to be rl78 (gdb) disassemble 0x0,+4 Dump of assembler code from 0x0 to 0x4: 0x00000000: nop 0x00000001: nop 0x00000002: nop 0x00000003: nop the output is wrong. This patch adds code to call dis->memory_error_func on memory error, and longjmp to print_insn_rl78_common. With this patch applied, (gdb) set architecture rl78 The target architecture is assumed to be rl78 (gdb) disassemble 0,+4 Dump of assembler code from 0x0 to 0x4: 0x00000000: Cannot access memory at address 0x0 opcodes: 2016-12-12 Yao Qi <yao.qi@linaro.org> * rl78-dis.c: Include <setjmp.h>. (struct private): New. (rl78_get_byte): Check return value of read_memory_func, and call memory_error_func and OPCODES_SIGLONGJMP on error. (print_insn_rl78_common): Call OPCODES_SIGJMP.	9 years ago
Maciej W. Rozycki	64c1118340	MIPS16: Remove unused `>' operand code This code has never been used throughout the repository history, and likely not before either, as due to the assymetry of MIPS16 instruction set encoding there are no 32-bit shift operations having their immediate shift count placed in the position of the usual `rx' instruction field. gas/ * config/tc-mips.c (mips16_macro_build) <'>'>: Remove case. include/ * opcode/mips.h: Remove references to `>' operand code. opcodes/ * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.	9 years ago
Maciej W. Rozycki	f17ecb4bac	MIPS16/opcodes: Use hexadecimal interpretation for the `e' operand code Make the `e' operand code used with raw EXTEND instructions use the hexadecimal rather than decimal format, for consistency with what is actually produced by code in `print_insn_mips16' dedicated to EXTEND disassembly. Due to that special handling the operand code is only interpreted for assembly however, which accepts either format either way, so there is no functional change here. opcodes/ * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather than UINT. gas/ * testsuite/gas/mips/mips16-extend.d: New test. * testsuite/gas/mips/mips16-extend.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.	9 years ago
Maciej W. Rozycki	55af478400	MIPS16/opcodes: Reformat raw EXTEND and undecoded output Use a tab rather than a space to separate `extend' and its uninterpreted argument output, like with regular instructions. Separate hexadecimal halves of undecoded extended instructions output with a space instead of presenting them concatenated. opcodes/ * mips-dis.c (print_insn_mips16): Use a tab rather than a space to separate `extend' and its uninterpreted argument output. Separate hexadecimal halves of undecoded extended instructions output. binutils/ * testsuite/binutils-all/mips/mips16-extend-noinsn.d: New test. * testsuite/binutils-all/mips/mips16-extend-noinsn.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new test.	9 years ago
Maciej W. Rozycki	39f66f3ae2	MIPS16/opcodes: Fix off-by-one indentation in `print_mips16_insn_arg' opcodes/ * mips-dis.c (print_mips16_insn_arg): Remove extraneous indentation space across.	9 years ago
Maciej W. Rozycki	860b03a8f3	MIPS16/opcodes: Fix PC-relative operation delay-slot adjustment Complement commit `dd8b7c222e` ("MIPS: mips16e jalrc/jrc opcodes"), <https://sourceware.org/ml/binutils/2005-07/msg00349.html>, and stop the disassembler making a delay-slot adjustment for PC-relative operations following either MIPS16e compact jumps, or undefined RR/J(AL)R(C) encodings that have the `l' (link) and `ra' (source register is `ra') bits set both at a time. Adjust code description for accuracy. Add a suitable test case. opcodes/ * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot adjustment for PC-relative operations following MIPS16e compact jumps or undefined RR/J(AL)R(C) encodings. binutils/ * testsuite/binutils-all/mips/mips16-pcrel.d: New test. * testsuite/binutils-all/mips/mips16-pcrel.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new test.	9 years ago
Maciej W. Rozycki	329d01f70e	AArch64/opcodes: Correct another `index' global shadowing error Fix a commit `c2c4ff8d52` ("[AArch64] Add ARMv8.3 FCMLA and FCADD instructions") build regression: cc1: warnings being treated as errors .../opcodes/aarch64-dis.c: In function 'aarch64_ext_sve_addr_rr_lsl': .../opcodes/aarch64-dis.c:1324: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here make[4]: *** [aarch64-asm.lo] Error 1 in a way following commit `91d6fa6a03` ("Add -Wshadow to the gcc command line options used when compiling the binutils."). opcodes/ * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local variable to `reglane_index'.	9 years ago
Luis Machado	3a2488dd21	Fix crash when disassembling invalid range on powerpc vle I got a report of a gdb crash for vle and further investigation showed an attempt to disassemble an invalid memory range. I tracked the crash down to the code in get_powerpc_dialect, where we fail to make sure we have a valid section pointer before dereferencing it. There is no such problem for rs6000-based disassembling. opcodes/ChangeLog: 2016-12-08 Luis Machado <lgustavo@codesourcery.com> * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.	9 years ago
Maciej W. Rozycki	5f5c6e032e	MIPS/opcodes: Correct an `interaction' comment typo opcodes/ * mips-dis.c (print_mips16_insn_arg): Fix comment typo.	10 years ago
Maciej W. Rozycki	343fa69063	MIPS16/opcodes: Update opcode table comment opcodes/ * mips16-opc.c (mips16_opcodes): Update comment naming structure members.	10 years ago
Maciej W. Rozycki	6725647ca2	MIPS/opcodes: Reformat `-M' disassembler option's help text Align output produced consistently and fix other formatting issues. opcodes/ * mips-dis.c (print_mips_disassembler_options): Reformat output.	10 years ago
Szabolcs Nagy	c28eeff2ea	[ARM] Add ARMv8.3 VCMLA and VCADD instructions Add support for VCMLA and VCADD advanced SIMD complex number instructions. The command line option is -march=armv8.3-a+fp16+simd for enabling all instructions. In arm-dis.c the formatting syntax was abused a bit to select between 0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of duplicating entries in the opcode table. gas/ * config/tc-arm.c (do_vcmla, do_vcadd): Define. (neon_scalar_for_vcmla): Define. (enum operand_parse_code): Add OP_IROT1 and OP_IROT2. (NEON_ENC_TAB): Add DDSI and QQSI variants. (insns): Add vcmla and vcadd. * testsuite/gas/arm/armv8_3-a-simd.d: New. * testsuite/gas/arm/armv8_3-a-simd.s: New. * testsuite/gas/arm/armv8_3-a-simd-bad.d: New. * testsuite/gas/arm/armv8_3-a-simd-bad.l: New. * testsuite/gas/arm/armv8_3-a-simd-bad.s: New. opcodes/ * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd. (print_insn_coprocessor): Add 'V' format for neon D or Q regs.	10 years ago
Szabolcs Nagy	49e8a72582	[ARM] Add ARMv8.3 VJCVT instruction Add support for VJCVT javascript conversion instruction. gas/ * config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define. (insns): Add vjcvt. * testsuite/gas/aarch64/armv8_3-a-fp.s: New. * testsuite/gas/aarch64/armv8_3-a-fp.d: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New. opcodes/ * arm-dis.c (coprocessor_opcodes): Add vjcvt.	10 years ago
Nick Clifton	a37a2806e3	Fix abort in x86 disassembler. PR binutils/20893 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad opcode designator.	10 years ago

2 Commits (ee0fa6627079ebd16843d9d3fb4e24a5af545ded)