binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Simon Marchi	ecc3c38667	gdb: ignore -Wregister instead of -Wdeprecated-register When building GDB on Centos 7 (which has flex 2.5.37) and Clang, I get: $ make ada-exp.o YACC ada-exp.c LEX ada-lex.c CXX ada-exp.o In file included from /home/smarchi/src/binutils-gdb/gdb/ada-exp.y:1179: <stdout>:1106:2: error: ISO C++17 does not allow 'register' storage class specifier [-Wregister] 1106 \| register yy_state_type yy_current_state; \| ^~~~~~~~ In ada-lex.l, we already use `DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER`, which for Clang translates to ignoring `-Wdeprecated-register` [1]. I think that was produced when compiling as C++11, but now that we always compile as C++17, Clang produces a `-Wregister` error [2]. For GCC, `DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER` already translates to ignoring `-Wregister`. So, rename `DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER` to `DIAGNOSTIC_IGNORE_REGISTER` and ignore `-Wregister` for Clang too. [1] https://releases.llvm.org/17.0.1/tools/clang/docs/DiagnosticsReference.html#wdeprecated-register [2] https://releases.llvm.org/17.0.1/tools/clang/docs/DiagnosticsReference.html#wregister include/ChangeLog: * diagnostics.h (DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER): Rename to... (DIAGNOSTIC_IGNORE_REGISTER): ... this. Ignore `-Wregister` instead of `-Wdeprecated-register`. Change-Id: I8a4a51c7222c68577fa22ecacdddfcba32d9dbc5	2 years ago
Yuriy Kolerov	c0852af056	arc: Put DBNZ instruction to a separate class DBNZ instruction decrements its source register operand, and if the result is non-zero it branches to the location defined by a signed half-word displacement operand. DBNZ instruction is in BRANCH class as other branch instrucitons like B, Bcc, etc. However, DBNZ is the only branch instruction that stores a branch offset in the second operand. Thus it must be placed in a distinct class and treated differently. For example, current logic of arc_insn_get_branch_target in GDB assumes that a branch offset is always stored in the first operand for BRANCH class and it's wrong for DBNZ. include/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * opcode/arc.h (enum insn_class_t): Add DBNZ class. opcodes/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * arc-tbl.h (dbnz): Use "DBNZ" class. * arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class. gas/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ".	2 years ago
Frederic Cambus	d86205c3ec	Add support to readelf for the PT_OPENBSD_SYSCALLS segment type. binutils * readelf.c (get_segment_type): Handle PT_OPENBSD_SYSCALLS segment type. include * elf/common.h (PT_OPENBSD_SYSCALLS): Define.	2 years ago
Jose E. Marchesi	0c45feb159	bpf: there is no ldinddw nor ldabsdw instructions There are no legacy ldind nor ldabs BPF instructions with BPF_SIZE_DW. For some reason we were (incorrectly) supporting these. This patch updates the opcodes so the instructions get removed and modifies the GAS manual and testsuite accordingly. See discussion at https://lore.kernel.org/bpf/110aad7a-f8a3-46ed-9fda-2f8ee54dcb89@linux.dev Tested in bpf-uknonwn-none target, x86-64-linux-gnu host. include/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Remove BPF_INSN_LDINDDW and BPF_INSN_LDABSDW instructions. opcodes/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and BPF_INSN_LDABSDW instructions. gas/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): There is no indirect 64-bit load instruction. (BPF Instructions): There is no absolute 64-bit load instruction. * testsuite/gas/bpf/mem.s: Update test accordingly. * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/mem.s: Likewise.	2 years ago
Nick Clifton	299b91cd85	Add markers for 2.42 branch	2 years ago
Alan Modra	fd67aa1129	Update year range in copyright notice of binutils files Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out /po/.pot which we don't update frequently.	2 years ago
Jakub Jelinek	4a50820ee8	libiberty, ld: Use x86 HW optimized sha1 The following patch attempts to use x86 SHA ISA if available to speed up in my testing about 2.5x sha1 build-id processing (in my case on AMD Ryzen 5 3600) while producing the same result. I believe AArch64 has similar HW acceleration for SHA1, perhaps it could be added similarly. Note, seems lld uses BLAKE3 rather than md5/sha1. I think it would be a bad idea to lie to users, if they choose --buildid=sha1, we should be using SHA1, not some other checksum, but perhaps we could add some other --buildid= styles and perhaps make one of the new the default. Tested on x86_64-linux, both on Intel i9-7960X (which doesn't have sha_ni ISA support) without/with the patch and on AMD Ryzen 5 3600 (which does have it) without/with the patch. 2023-11-28 Jakub Jelinek <jakub@redhat.com> include/ * sha1.h (sha1_process_bytes_fn): New typedef. (sha1_choose_process_bytes): Declare. libiberty/ * configure.ac (HAVE_X86_SHA1_HW_SUPPORT): New check. * sha1.c: If HAVE_X86_SHA1_HW_SUPPORT is defined, include x86intrin.h and cpuid.h. (sha1_hw_process_bytes, sha1_hw_process_block, sha1_choose_process_bytes): New functions. * config.in: Regenerated. * configure: Regenerated. ld/ * ldbuildid.c (generate_build_id): Use sha1_choose_process_bytes () instead of &sha1_process_bytes.	2 years ago
Simon Marchi	a7a0cb6c92	bfd, binutils: add gfx11 amdgpu architectures Teach bfd and readelf about some recent gfx11 architectures. This code is taken from the rocgdb 5.7.x branch [1]. [1] https://github.com/rocm-Developer-Tools/rocgdb/tree/rocm-5.7.x bfd/ChangeLog: * archures.c (bfd_mach_amdgcn_gfx1100, bfd_mach_amdgcn_gfx1101, bfd_mach_amdgcn_gfx1102): New. * bfd-in2.h (bfd_mach_amdgcn_gfx1100, bfd_mach_amdgcn_gfx1101, bfd_mach_amdgcn_gfx1102): New. * cpu-amdgcn.c (arch_info_struct): Add entries for bfd_mach_amdgcn_gfx1100, bfd_mach_amdgcn_gfx1101, bfd_mach_amdgcn_gfx1102. binutils/ChangeLog: * readelf.c (decode_AMDGPU_machine_flags): Handle gfx1100, gfx1101, gfx1102. include/ChangeLog: * elf/amdgpu.h (EF_AMDGPU_MACH_AMDGCN_GFX1100, EF_AMDGPU_MACH_AMDGCN_GFX1101, EF_AMDGPU_MACH_AMDGCN_GFX1102): New. Change-Id: I95a8a62942e359781a1c9fa2079950fbcf2a78b8 Co-Authored-By: Laurent Morichetti <laurent.morichetti@amd.com> Cc: Lancelot Six <lancelot.six@amd.com>	2 years ago
Nick Clifton	e922d1eaa3	Add ability to change linker warning messages into errors when reporting executable stacks and/or executable segments. include * bfdlink.h (struct bfd_link_info): Update descriptions of the 'execstack', 'noexecstack' and 'warn_execstack' fields. Add 'error_exectack' and 'warn_is_error_for_rwx_segments' fields. bfd * elf.c (assign_file_positions_except_relocs): Turn warnings about executable segments into errors if so requested. * elflink.c (bfd_elf_size_dynamic_sections): Turn warnings about executable stacks into errors if so requested. ld * ldlex.h (enum option_values): Add OPTION_ERROR_EXECSTACK, OPTION_NO_ERROR_EXECSTACK, OPTION_WARN_EXECSTACK_OBJECTS, OPTION_ERROR_RWX_SEGMENTS and OPTION_NO_ERROR_RWX_SEGMENTS. (struct ld_option): Add new long options. (parse_args): Parse new long options. (elf_static_list_options): Display the new options. * ld.texi: Document the new command line options. * configure.ac (error-execstack): New configuration option. (error-rwx-segments): New configuration option. * emultempl/elf.em (_before_parse): Initialse the new linkinfo fields. * NEWS: Mention the new features. * config.in: Regenerate. * configure: Regenerate. * testsuite/ld-elf/commonpage2.d: Disable errors for RWX segments and/or executable stacks. * testsuite/ld-elf/elf.exp: Likewise. * testsuite/ld-elf/header.d: Likewise. * testsuite/ld-elf/loadaddr1.d: Likewise. * testsuite/ld-elf/loadaddr2.d: Likewise. * testsuite/ld-elf/maxpage4.d: Likewise. * testsuite/ld-elf/nobits-1.d: Likewise. * testsuite/ld-elf/note-1.d: Likewise. * testsuite/ld-elf/orphan-10.d: Likewise. * testsuite/ld-elf/orphan-11.d: Likewise. * testsuite/ld-elf/orphan-12.d: Likewise. * testsuite/ld-elf/orphan-5.d: Likewise. * testsuite/ld-elf/orphan-7.d: Likewise. * testsuite/ld-elf/orphan-8.d: Likewise. * testsuite/ld-elf/orphan-9.d: Likewise. * testsuite/ld-elf/orphan-region.d: Likewise. * testsuite/ld-elf/orphan.d: Likewise. * testsuite/ld-elf/pr19539.d: Likewise. * testsuite/ld-elf/pr26256-1a.d: Likewise. * testsuite/ld-elf/pr26907.d: Likewise. * testsuite/ld-elf/pr28597.d: Likewise. * testsuite/ld-elf/retain2.d: Likewise. * testsuite/ld-elf/shared.exp: Likewise. * testsuite/ld-elf/size-1.d: Likewise. * testsuite/ld-elf/textaddr7.d: Likewise. * testsuite/ld-elf/warn1.d: Likewise. * testsuite/ld-elf/warn2.d: Likewise. * testsuite/ld-i386/discarded1.d: Likewise. * testsuite/ld-i386/pr19175.d: Likewise. * testsuite/ld-i386/pr19539.d: Likewise. * testsuite/ld-i386/pr23189.d: Likewise. * testsuite/ld-plugin/lto-3r.d: Likewise. * testsuite/ld-plugin/lto-5r.d: Likewise. * testsuite/ld-plugin/lto.exp: Likewise. * testsuite/ld-powerpc/ppc476-shared.d: Likewise. * testsuite/ld-powerpc/ppc476-shared2.d: Likewise. * testsuite/ld-powerpc/pr28827-2.d: Likewise. * testsuite/ld-s390/s390.exp: Likewise. * testsuite/ld-scripts/align2a.d: Likewise. * testsuite/ld-scripts/align2b.d: Likewise. * testsuite/ld-scripts/align5.d: Likewise. * testsuite/ld-scripts/alignof.exp: Likewise. * testsuite/ld-scripts/crossref.exp: Likewise. * testsuite/ld-scripts/defined2.d: Likewise. * testsuite/ld-scripts/defined3.d: Likewise. * testsuite/ld-scripts/defined5.d: Likewise. * testsuite/ld-scripts/pr14962.d: Likewise. * testsuite/ld-scripts/pr18963.d: Likewise. * testsuite/ld-scripts/pr20302.d: Likewise. * testsuite/ld-scripts/print-memory-usage.exp: Likewise. * testsuite/ld-scripts/rgn-at1.d: Likewise. * testsuite/ld-scripts/rgn-at10.d: Likewise. * testsuite/ld-scripts/rgn-at4.d: Likewise. * testsuite/ld-scripts/rgn-at6.d: Likewise. * testsuite/ld-scripts/rgn-at8.d: Likewise. * testsuite/ld-scripts/rgn-at9.d: Likewise. * testsuite/ld-scripts/rgn-over1.d: Likewise. * testsuite/ld-scripts/rgn-over2.d: Likewise. * testsuite/ld-scripts/rgn-over4.d: Likewise. * testsuite/ld-scripts/rgn-over5.d: Likewise. * testsuite/ld-scripts/rgn-over6.d: Likewise. * testsuite/ld-scripts/script.exp: Likewise. * testsuite/ld-scripts/sizeof.exp: Likewise. * testsuite/ld-scripts/sort-file.d: Likewise. * testsuite/ld-x86-64/discarded1.d: Likewise. * testsuite/ld-x86-64/pr19175.d: Likewise. * testsuite/ld-x86-64/pr19539a.d: Likewise. * testsuite/ld-x86-64/pr19539b.d: Likewise. * testsuite/ld-x86-64/pr23189.d: Likewise.	2 years ago
Nick Clifton	a4a51292bb	Accept and ignore the R_BPF_64_NODLYD32 relocation.	2 years ago
Frederic Cambus	73b22419ed	Add support to readelf for the PT_OPENBSD_NOBTCFI segment type.	3 years ago
Tom Tromey	f559e52a8e	Remove PEI_HEADERS define I noticed a few files double-included libcoff.h, and digging deeper I found that the PEI_HEADERS define is a sort of external include guard. This patch adds include guards to the few files in include/coff that were missing one, and then removes the PEI_HEADERS workaround and the redundant includes. I didn't see anything in these files that indicated that double-inclusion would be useful, so it seems to me that this approach is ok. Tested by rebuilding with --enable-targets=all. 2023-08-02 Tom Tromey <tromey@adacore.com> * pei-x86_64.c (PEI_HEADERS): Do not define. * pei-loongarch64.c (PEI_HEADERS): Do not define. * pei-aarch64.c (PEI_HEADERS): Do not define. * pe-x86_64.c (PEI_HEADERS): Do not define. * pe-aarch64.c (PEI_HEADERS): Do not define. * libpei.h (_LIBPEI_H): Add include guard. * coff-x86_64.c (PEI_HEADERS): Do not check. * coff-loongarch64.c (PEI_HEADERS): Do not check. * coff-aarch64.c (PEI_HEADERS): Do not check. include/ChangeLog 2023-08-02 Tom Tromey <tromey@adacore.com> * coff/x86_64.h (COFF_X86_64_H): Add include guard. * coff/loongarch64.h (COFF_LOONGARCH64_H): Add include guard. * coff/aarch64.h (COFF_AARCH64_H): Add include guard.	3 years ago
Sam James	b5c37946cc	Revert "2.41 Release sources" This reverts commit `675b9d612c`. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.	3 years ago
Nick Clifton	675b9d612c	2.41 Release sources	3 years ago
Jose E. Marchesi	1e18ffc991	bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flags This patch adds support for EF_BPF_CPUVER bits in the ELF machine-dependent header flags. These bits encode the BPF CPU version for which the object file has been compiled for. The BPF assembler is updated so it annotates the object files it generates with these bits. The BPF disassembler is updated so it honors EF_BPF_CPUVER to use the appropriate ISA version if the user didn't specify an explicit ISA version in the command line. Note that a value of zero in EF_BPF_CPUVER is interpreted by the disassembler as "use the later supported version" (the BPF CPU versions start with v1.) The readelf utility is updated to pretty print EF_BPF_CPUVER when it prints out the ELF header: $ readelf -h a.out ELF Header: ... Flags: 0x4, CPU Version: 4 Tested in bpf-unknown-none. include/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/bpf.h (EF_BPF_CPUVER): Define. * opcode/bpf.h (BPF_XBPF): Change from 0xf to 0xff so it fits in EF_BPF_CPUVER. binutils/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * readelf.c (get_machine_flags): Recognize and pretty print BPF machine flags. opcodes/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-dis.c: Initialize asm_bpf_version to -1. (print_insn_bpf): Set BPF ISA version from the cpu version ELF header flags if no explicit version set in the command line. * disassemble.c (disassemble_init_for_target): Remove unused code. gas/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.h (elf_tc_final_processing): Define. * config/tc-bpf.c (bpf_elf_final_processing): New function.	3 years ago
Jose E. Marchesi	5cbe549257	bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64} This patch adds support for the BPF V4 ISA byte swap instructions to opcodes, assembler and disassembler. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (BPF_IMM32_BSWAP16): Define. (BPF_IMM32_BSWAP32): Likewise. (BPF_IMM32_BSWAP64): Likewise. (enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}. opcodes/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP* instructions. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions. * testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions. * testsuite/gas/bpf/alu.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.	3 years ago
Jose E. Marchesi	c2ca88d74b	bpf: add support for jal/gotol jump instruction with 32-bit target This patch adds support for the V4 BPF instruction jal/gotol, which is like ja/goto but it supports a signed 32-bit PC-relative (in number of 64-bit words minus one) target operand instead of the 16-bit signed operand of the other instruction. This greatly increases the jump range in BPF programs. Tested in bpf-unkown-none. bfd/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32. * elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc. * libbfd.h (bfd_reloc_code_real_names): Regenerate. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (struct bpf_insn): New field `id'. (md_assemble): Save the ids of successfully parsed instructions and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate. (md_apply_fix): Adapt to the new BFD reloc. * testsuite/gas/bpf/jump.s: Test JAL. * testsuite/gas/bpf/jump.d: Likewise. * testsuite/gas/bpf/jump-pseudoc.d: Likewise. * testsuite/gas/bpf/jump-be.d: Likewise. * testsuite/gas/bpf/jump-be-pseudoc.d: Likewise. * doc/c-bpf.texi (BPF Instructions): Document new instruction jal/gotol. Document new operand type disp32. include/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL. (enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI. opcodes/ChangeLog: 2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entry for jal.	3 years ago
Jose E. Marchesi	c24fd9547f	bpf: opcodes, gas: support for signed load V4 instructions This commit adds the signed load to register (ldxs) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> opcode/bpf.h (enum bpf_insn_id): Add entries for signed load instructions. (BPF_MODE_SMEM): Define. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW} instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: Add signed load instructions. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be.d: Likewise. * doc/c-bpf.texi (BPF Instructions): Document the signed load instructions.	3 years ago
Jose E. Marchesi	2f3dbc5fb5	bpf: opcodes, gas: support for signed register move V4 instructions This commit adds the signed register move (movs) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. (BPF_OFFSET16_MOVS16): Likewise. (BPF_OFFSET16_MOVS32): Likewise. (enum bpf_insn_id): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R instructions. and MOVS32I instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.s: Test movs instructions. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu.d: Add expected results. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.	3 years ago
Nick Clifton	d501d38488	Add markers for the 2.41 branch	3 years ago
Andreas Schwab	5fd6b60d86	Remove duplicate definition * coff/pe.h (IMAGE_FILE_MACHINE_AMD64): Remove duplicate definition. Alphabetize.	3 years ago
Frederic Cambus	80251d4185	Add support to readelf for the PT_OPENBSD_MUTABLE segment type. binutils * readelf.c (get_segment_type): Handle PT_OPENBSD_MUTABLE segment type. include * elf/common.h (PT_OPENBSD_MUTABLE): Define.	3 years ago
Luis Machado	a8f175d9d0	Add new NT_ARM_ZA and NT_ARM_SSVE register set constants.	3 years ago
Alan Modra	d87bef3a7b	Update year range in copyright notice of binutils files The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.	3 years ago
Nick Clifton	a72b07181d	Add markers for 2.40 branch	3 years ago
Jan-Benedict Glaw	aef1974a66	Fix self-move warning check for GCC 13+ GCC 13 got the self-move warning (0abb78dda084a14b3d955757c6431fff71c263f3), but that warning is only checked for clang, resulting in: /usr/lib/gcc-snapshot/bin/g++ -x c++ -I. -I. -I./config -DLOCALEDIR="\"/tmp/gdb-m68k-linux/share/locale\"" -DHAVE_CONFIG_H -I./../include/opcode -I./../readline/readline/.. -I./../zlib -I../bfd -I./../bfd -I./../include -I../libdecnumber -I./../libdecnumber -I./../gnulib/import -I../gnulib/import -I./.. -I.. -I./../libbacktrace/ -I../libbacktrace/ -DTUI=1 -I./.. -pthread -Wall -Wpointer-arith -Wno-unused -Wunused-value -Wunused-variable -Wunused-function -Wno-switch -Wno-char-subscripts -Wempty-body -Wunused-but-set-parameter -Wunused-but-set-variable -Wno-sign-compare -Wno-error=maybe-uninitialized -Wno-mismatched-tags -Wsuggest-override -Wimplicit-fallthrough=3 -Wduplicated-cond -Wshadow=local -Wdeprecated-copy -Wdeprecated-copy-dtor -Wredundant-move -Wmissing-declarations -Wstrict-null-sentinel -Wformat -Wformat-nonliteral -Werror -g -O2 -c -o unittests/environ-selftests.o -MT unittests/environ-selftests.o -MMD -MP -MF unittests/.deps/environ-selftests.Tpo unittests/environ-selftests.c unittests/environ-selftests.c: In function 'void selftests::gdb_environ_tests::test_self_move()': unittests/environ-selftests.c:228:7: error: moving 'env' of type 'gdb_environ' to itself [-Werror=self-move] 228 \| env = std::move (env); \| ~~~~^~~~~~~~~~~~~~~~~ unittests/environ-selftests.c:228:7: note: remove 'std::move' call cc1plus: all warnings being treated as errors make[1]: * [Makefile:1896: unittests/environ-selftests.o] Error 1 make[1]: Leaving directory '/var/lib/laminar/run/gdb-m68k-linux/3/binutils-gdb/gdb' make: * [Makefile:13193: all-gdb] Error 2	4 years ago
Nick Clifton	0bd0932314	Add markers for 2.39 branch	4 years ago
Cl?ment Chigot	1876a54217	Stubs (added in a later patch) will generate new .loader symbols, once the allocations have been done. Thus, the .loader section cannot be layout before that. bfd/ChangeLog: * coff-rs6000.c (_bfd_xcoff_put_ldsymbol_name): Write len in ldinfo->strings instead of directly in the output_bfd. * coff64-rs6000.c (_bfd_xcoff64_put_ldsymbol_name): Likewise. * xcofflink.c (struct xcoff_link_hash_table): Remove ldrel_count field. Add ldinfo field. (xcoff_mark_symbol): Adjust to new ldinfo field. (xcoff_mark): Likewise. (bfd_xcoff_link_count_reloc): Likewise. (xcoff_build_loader_section): Split into two functions: one that build the loader section (this function) and one that only size it... (xcoff_size_loader_section): ... (this function). (bfd_xcoff_size_dynamic_sections): Adapt to new ldinfo field. Move the part where the dynamic sections are build to ... (bfd_xcoff_build_dynamic_sections): ... this function. * xcofflink.h: Add bfd_xcoff_build_dynamic_sections prototype. include/ChangeLog: * coff/xcoff.h (struct xcoff_loader_info): Add ldrel_count and libpath fields. ld/ChangeLog: * emultempl/aix.em (_after_allocation): New function.	4 years ago
Mark Harmstone	145667f8d9	Add support for COFF secidx relocations bfd * coff-i386.c (in_reloc_p): Add R_SECTION. (howto_table): Add R_SECTION. (coff_pe_i386_relocation_section): Add support for R_SECTION. (coff_i386_reloc_type_lookup): Add support for BFD_RELOC_16_SECCIDX. * coff-x86_64.c (in_reloc_p): Add R_SECTION. (howto_table): Add R_SECTION. (coff_pe_amd64_relocation_section): Add support for R_SECTION. (coff_amd64_reloc_type_lookup): Add support for BFD_RELOC_16_SECCIDX. * reloc.c: Add BFD_RELOC_16_SECIDX. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas * config/tc-i386.c (pe_directive_secidx): New function. (md_pseudo_table): Add support for secidx. (x86_cons_fix_new): Likewise. (tc_gen_reloc): Likewise. * expr.c (op_rank): Add O_secidx. * expr.h (operatorT): Likewise. * symbols.c (resolve_symbol_value): Add support for O_secidx. * testsuite/gas/i386/secidx.s: New test source file. * testsuite/gas/i386/secidx.d: New test driver file. * testsuite/gas/i386/i386.exp: Run new test. include * coff/i386.h: Define R_SECTION. * coff/x86_64.h: Likewise. ld * testsuite/ld-pe/secidx1.s: New test source file. * testsuite/ld-pe/secidx2.s: New test source file. * testsuite/ld-pe/secidx.d: New test driver file. * testsuite/ld-pe/secidx_64.d: New test driver file. * testsuite/ld-pe/pe.exp: Add new tests.	4 years ago
John Baldwin	a171378aa4	Recognize FreeBSD core dump note for x86 segment base registers. This core dump note contains the value of the base address of the %fs and %gs segments for both i386 and amd64 core dumps. It is primarily useful in resolving the address of TLS variables in core dumps. binutils/ChangeLog: * readelf.c (get_freebsd_elfcore_note_type): Handle NT_FREEBSD_X86_SEGBASES. include/ChangeLog: * elf/common.h (NT_FREEBSD_X86_SEGBASES): Define.	4 years ago
Simon Marchi	0c857ef4df	binutils/readelf: handle AMDGPU relocation types Make readelf recognize AMDGPU relocation types, as documented here: https://llvm.org/docs/AMDGPUUsage.html#amdgpu-relocation-records The user-visible change looks like: -000000000004 000400000001 unrecognized: 1 0000000000000000 SCRATCH_RSRC_DWORD0 -00000000000c 000500000001 unrecognized: 1 0000000000000000 SCRATCH_RSRC_DWORD1 -000000000014 000600000007 unrecognized: 7 0000000000000000 global_var0 -00000000001c 000700000008 unrecognized: 8 0000000000000000 global_var1 -000000000024 000800000009 unrecognized: 9 0000000000000000 global_var2 -00000000002c 00090000000a unrecognized: a 0000000000000000 global_var3 -000000000034 000a0000000b unrecognized: b 0000000000000000 global_var4 +000000000004 000400000001 R_AMDGPU_ABS32_LO 0000000000000000 SCRATCH_RSRC_DWORD0 +00000000000c 000500000001 R_AMDGPU_ABS32_LO 0000000000000000 SCRATCH_RSRC_DWORD1 +000000000014 000600000007 R_AMDGPU_GOTPCREL 0000000000000000 global_var0 +00000000001c 000700000008 R_AMDGPU_GOTPCREL 0000000000000000 global_var1 +000000000024 000800000009 R_AMDGPU_GOTPCREL 0000000000000000 global_var2 +00000000002c 00090000000a R_AMDGPU_REL32_LO 0000000000000000 global_var3 +000000000034 000a0000000b R_AMDGPU_REL32_HI 0000000000000000 global_var4 binutils/ChangeLog: * readelf.c (dump_relocations): Handle EM_AMDGPU. include/ChangeLog: * elf/amdgpu.h: Add relocation values. Change-Id: I2ed4589f4cd37ea11ad2e0cb38d4b682271e1334	4 years ago
Simon Marchi	28cdbb183b	binutils/readelf: handle NT_AMDGPU_METADATA note name Handle the NT_AMDGPU_METADATA note, which is described here: https://llvm.org/docs/AMDGPUUsage.html#code-object-v3-note-records As of this patch, just print out the name, not the contents, which is in the msgpack format. binutils/ChangeLog: * readelf.c (get_amdgpu_elf_note_type): New. (process_note): Handle "AMDGPU" notes. include/ChangeLog: * elf/amdgcn.h (NT_AMDGPU_METADATA): New. Change-Id: Id2dba2e2aeaa55ef7464fb35aee9c7d5f96ddb23	4 years ago
Simon Marchi	c077c5802c	binutils/readelf: decode AMDGPU-specific e_flags Decode and print the AMDGPU-specific fields of e_flags, as documented here: https://llvm.org/docs/AMDGPUUsage.html#header That is: - The specific GPU model - Whether the xnack and sramecc features are enabled The result looks like: - Flags: 0x52f + Flags: 0x52f, gfx906, xnack any, sramecc any The flags for the "HSA" OS ABI are properly versioned and documented on that page. But the NONE, PAL and MESA3D OS ABIs are not well documented nor versioned. Taking a peek at the LLVM source code, we see that they encode their flags the same way as HSA v3. For example, for PAL: `c8b614cd74/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp (L601)` So for those other OS ABIs, we read them the same as HSA v3. binutils/ChangeLog: * readelf.c: Include elf/amdgcn.h. (decode_AMDGPU_machine_flags): New. (get_machine_flags): Handle flags for EM_AMDGPU machine type. include/ChangeLog: * elf/amdgcn.h: Add EF_AMDGPU_MACH_AMDGCN_* and EF_AMDGPU_FEATURE_* defines. Change-Id: Ib5b94df7cae0719a22cf4e4fd0629330e9485c12	4 years ago
Simon Marchi	37870be874	binutils/readelf: handle AMDGPU OS ABIs When the machine is EM_AMDGPU, handle the various OS ABIs described here: https://llvm.org/docs/AMDGPUUsage.html#header For a binary with the HSA OS ABI, the change looks like: - OS/ABI: <unknown: 40> + OS/ABI: AMD HSA binutils/ChangeLog: * readelf.c (get_osabi_name): Handle EM_AMDGPU OS ABIs. include/ChangeLog: * elf/common.h (ELFOSABI_AMDGPU_PAL, ELFOSABI_AMDGPU_MESA3D): New. Change-Id: I383590c390f7dc2fe0f902f50038735626d71863	4 years ago
Simon Marchi	978602e83f	bfd: add AMDGCN architecture Add support for the AMDGCN architecture to BFD. This is the bare minimum to get $ ./configure --target=amdgcn-hsa-amdhsa --disable-gas $ make all-binutils working later in this series. The specific AMDGCN models added here are a bit arbitrary, based on what we intend to initially support in GDB. This list will need to be updated in the future anyway. The complete up-to-date list of existing AMDGPU models can be found here: https://llvm.org/docs/AMDGPUUsage.html#processors The ELF format for this architecture is documented here: https://llvm.org/docs/AMDGPUUsage.html#elf-code-object The flags for the "HSA" OS ABI are properly versioned and documented on that page. But the NONE, PAL and MESA3D OS ABIs are not well documented nor versioned. Taking a peek at the LLVM source code, we see that they encode their flags the same way as HSA v3. For example, for PAL: `c8b614cd74/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp (L601)` So at least, we know that all AMDGPU objects (of which AMDGCN objects are a subset of) at the time of writing encode the specific GPU model in the EF_AMDGPU_MACH field of e_flags. bfd/ChangeLog: * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add cpu-amdgcn.c. (BFD64_BACKENDS): Add elf64-amdgcn.lo. (BFD64_BACKENDS_CFILES): Add elf64-amdgcn.c. * Makefile.in: Re-generate. * cpu-amdgcn.c: New. * elf64-amdgcn.c: New. * archures.c (bfd_architecture): Add bfd_arch_amdgcn and related mach defines. (bfd_amdgcn_arch): New. (bfd_archures_list): Add bfd_amdgcn_arch. * bfd-in2.h: Re-generate. * config.bfd: Handle amdgcn* target. * configure.ac: Handle amdgcn_elf64_le_vec. * configure: Re-generate. * elf-bfd.h (elf_target_id): Add AMDGCN_ELF_DATA. * targets.c (amdgcn_elf64_le_vec): New. (_bfd_target_vector): Add amdgcn_elf64_le_vec. include/ChangeLog: * elf/amdgpu.h: New. * elf/common.h (ELFOSABI_AMDGPU_HSA): Add. Change-Id: I969f7b14960797e88891c308749a6e341eece5b2	4 years ago
Vladimir Mezentsev	bb368aad29	gprofng: a new GNU profiler top-level * Makefile.def: Add gprofng module. * configure.ac: Add --enable-gprofng option. * src-release.sh: Add gprofng. * Makefile.in: Regenerate. * configure: Regenerate. * gprofng: New directory. binutils * MAINTAINERS: Add gprofng maintainer. * README-how-to-make-a-release: Add gprofng. include. * collectorAPI.h: New file. * libcollector.h: New file. * libfcollector.h: New file.	4 years ago
Klaus Ziegler	b6437be687	Fix a probem building the binutils on SPARC/amd64 PR 28816 * elf/common.h (AT_SUN_HWCAP): Make definition conditional.	4 years ago
Nick Clifton	a74e1cb344	Add markers for 2.38 branch	4 years ago
Nick Clifton	ce2d3708bc	Synchronize binutils libiberty sources with gcc version. +2021-12-30 Lancelot SIX <lsix@lancelotsix.com> + + * cp-demangle.c (d_clone_suffix): Support digits in clone tag + names. + * testsuite/demangle-expected: Check demangling of clone symbols + with digits in name. + +2021-12-16 H.J. Lu <hjl.tools@gmail.com> + + Revert: + 2021-12-16 H.J. Lu <hjl.tools@gmail.com> + + * Makefile.in (AR): Add @AR_PLUGIN_OPTION@ + (RANLIB): Add @RANLIB_PLUGIN_OPTION@. + (configure_deps): Depend on ../config/gcc-plugin.m4. + * configure.ac: AC_SUBST AR_PLUGIN_OPTION and + RANLIB_PLUGIN_OPTION. + * aclocal.m4: Regenerated. + * configure: Likewise. + +2021-12-15 H.J. Lu <hjl.tools@gmail.com> + + * Makefile.in (AR): Add @AR_PLUGIN_OPTION@ + (RANLIB): Add @RANLIB_PLUGIN_OPTION@. + (configure_deps): Depend on ../config/gcc-plugin.m4. + * configure.ac: AC_SUBST AR_PLUGIN_OPTION and + RANLIB_PLUGIN_OPTION. + * aclocal.m4: Regenerated. + * configure: Likewise. + +2021-11-29 Eric Gallager <egallager@gcc.gnu.org> + + PR other/103021 + * Makefile.in: Use ETAGS variable in TAGS target. + * configure: Regenerate. + * configure.ac: Allow ETAGS variable to be overridden. + +2021-11-29 Andrew Pinski <apinski@marvell.com> + + * make-temp-file.c (try_dir): Check to see if the dir + is actually a directory. + +2021-10-22 Eric Gallager <egallager@gcc.gnu.org> + + PR other/102663 + * Makefile.in: Allow dvi-formatted documentation + to be installed. + +2021-10-17 Lu?s Ferreira <contact@lsferreira.net> + + PR d/102618 + * d-demangle.c (dlang_parse_qualified): Handle anonymous + symbols correctly. + * testsuite/d-demangle-expected: New tests to cover anonymous + symbols. + +2021-10-14 Lu?s Ferreira <contact@lsferreira.net> + + * testsuite/d-demangle-expected: Add test case for function literals. + +2021-10-14 Lu?s Ferreira <contact@lsferreira.net> + + * testsuite/d-demangle-expected: Add test cases for simple special + mangles. + +2021-10-12 Lu?s Ferreira <contact@lsferreira.net> + + * d-demangle.c (dlang_parse_qualified): Remove redudant parenthesis + around lhs and rhs of assignments. + +2021-10-01 Lu?s Ferreira <contact@lsferreira.net> + + * testsuite/d-demangle-expected: Add missing format for new test + +2021-09-23 Lu?s Ferreira <contact@lsferreira.net> + + * d-demangle.c (dlang_Type): Validate MANGLED is nonnull. + * testsuite/d-demangle-expected: New test. + +2021-09-23 Lu?s Ferreira <contact@lsferreira.net> + + * d-demangle.c (dlang_symbol_backref): Ensure strlen of + string is less than length computed by dlang_number. + +2021-09-01 Iain Sandoe <iain@sandoe.co.uk> * configure: Regenerate. + * configure.ac: Do not search for sbrk on Darwin. + * xmalloc.c: Do not declare sbrk unless it has been found + by configure. + +2021-08-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * d-demangle.c (dlang_identifier): Skip over fake parent manglings. + * testsuite/d-demangle-expected: Add tests. + +2021-08-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * d-demangle.c (dlang_parse_arrayliteral): Add 'info' parameter. + (dlang_parse_assocarray): Likewise. + (dlang_parse_structlit): Likewise. + (dlang_value): Likewise. Handle function literal symbols. + (dlang_template_args): Pass 'info' to dlang_value. + * testsuite/d-demangle-expected: Add new test. + +2021-08-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * d-demangle.c (dlang_attributes): Handle typeof(null). + (dlang_type): Likewise. Demangle 'n' as typeof(null). + testsuite/d-demangle-expected: Update tests. + +2021-08-23 Iain Sandoe <iain@sandoe.co.uk> + + * simple-object-mach-o.c (simple_object_mach_o_write_segment): + Cast the first argument to set_32 as needed. -2021-07-03 Nick Clifton <nickc@redhat.com> +2021-08-18 Iain Sandoe <iain@sandoe.co.uk> + * simple-object-mach-o.c (simple_object_mach_o_write_segment): + Arrange to swap the LTO index tables where needed. # Please enter the commit message for your changes. Lines starting	4 years ago
Alan Modra	a2c5833233	Update year range in copyright notice of binutils files The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out /po/.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.	4 years ago
John Baldwin	b4992e9990	Support AT_FXRNG and AT_KPRELOAD on FreeBSD. FreeBSD's kernel has recently added two new ELF auxiliary vector entries. AT_FXRNG points to a root seed version for the kernel's PRNG. Userland can use this to reseed a userland PRNG after the kernel's PRNG has reseeded. AT_KPRELOAD is the base address of a kernel-provided vDSO. This change displays the proper name and description of these entries in 'info auxv'. include/ChangeLog: * elf/common.h (AT_FREEBSD_FXRNG, AT_FREEBSD_KPRELOAD): Define.	4 years ago
Nick Clifton	92fc129e2b	Fix the fields in the x_n union inside the the x_file structure so that pointers can be stored. PR 28630 * coff/internal.h (x_n): Use bfd_hostptr_t for the fields in this structure.	4 years ago
Andrew Burgess	3a337a86d9	opcodes/riscv: add disassembler options support to libopcodes In preparation for the next commit, which will add GDB support for RISC-V disassembler options, this commit restructures how the disassembler options are managed within libopcodes. The implementation provided here is based on this mailing list patch which was never committed: https://sourceware.org/pipermail/binutils/2021-January/114944.html which in turn took inspiration from the MIPS implementation of the same feature. The biggest changes from the original mailing list post are: 1. The GDB changes have been split into a separate patch, and 2. The `riscv_option_args_privspec` variable, which held the valid priv-spec values is now gone, instead we use the `riscv_priv_specs` array from bfd/cpu-riscv.c instead. Co-authored-by: Simon Cook <simon.cook@embecosm.com> include/ChangeLog: * dis-asm.h (disassembler_options_riscv): Declare. opcodes/ChangeLog: * riscv-dis.c (enum riscv_option_arg_t): New enum typedef. (riscv_options): New static global. (disassembler_options_riscv): New function. (print_riscv_disassembler_options): Rewrite to use disassembler_options_riscv.	5 years ago
Fangrui Song	a7fd118627	readelf: Support SHT_RELR/DT_RELR for -r The -r output for SHT_RELR looks like: Relocation section '.relr.dyn' at offset 0x530 contains 4 entries: 7 offsets 00000000000028c0 00000000000028c8 0000000000003ad0 0000000000003ad8 0000000000003ae0 0000000000003ae8 0000000000003af0 For --use-dynamic, the header looks like 'RELR' relocation section at offset 0x530 contains 32 bytes: include/ * elf/common.h (DT_ENCODING): Bump to 38. * elf/external.h (Elf32_External_Relr): New. (Elf64_External_Relr): New. binutils/ * readelf.c (enum relocation_type): New. (slurp_relr_relocs): New. (dump_relocations): Change is_rela to rel_type. Dump RELR. (dynamic_relocations): Add DT_RELR. (process_relocs): Check SHT_RELR and DT_RELR. (process_dynamic_section): Store into dynamic_info for DT_RELR/DT_RELRENT/DT_RELRSZ.	4 years ago
Luis Machado	64dbf74d42	Revert: [AArch64] MTE corefile support bfd * elf.c (elfcore_make_memtag_note_section): New function. (elfcore_grok_note): Handle NT_MEMTAG note types. binutils* readelf.c (get_note_type): Handle NT_MEMTAG note types. include * elf/common.h (NT_MEMTAG): New constant. (NT_MEMTAG_TYPE_AARCH_MTE): New constant.	5 years ago
Nick Clifton	514192487e	Add markers for 2.37 branch	5 years ago
Nick Clifton	20c4b12e93	Synchronize libiberty sources (and include/demangle.h) with GCC master version	5 years ago
Mike Frysinger	6c2ede018c	opcodes: constify aarch64_opcode_tables This table is huge (~350k), so stop putting it into writable .data since it's only const data.	5 years ago
Richard Earnshaw	417f991f08	arm: don't treat XScale features as part of the FPU [PR 28031] Although the XScale and its iwMMX extensions are implemented in the Arm co-processor space, they are not considered to be part of the FPU specification. In particular, they cannot be enabled or disabled via a .fpu directive. It's therefore incorrect to strip these properties when a new .fpu directive is encountered. Note that the legacy Maverick co-processor is considered to be a FPU and it is possible to control this via the .fpu directive. include: PR gas/28031 * opcode/arm.h (FPU_ANY): Exclude XScale-related features.	5 years ago
H.J. Lu	5a767724d7	elf: Add GNU_PROPERTY_UINT32_AND_XXX/GNU_PROPERTY_UINT32_OR_XXX Implement GNU_PROPERTY_UINT32_AND_XXX/GNU_PROPERTY_UINT32_OR_XXX: https://sourceware.org/pipermail/gnu-gabi/2021q1/000467.html 1. GNU_PROPERTY_UINT32_AND_LO..GNU_PROPERTY_UINT32_AND_HI #define GNU_PROPERTY_UINT32_AND_LO 0xb0000000 #define GNU_PROPERTY_UINT32_AND_HI 0xb0007fff A bit in the output pr_data field is set only if it is set in all relocatable input pr_data fields. If all bits in the the output pr_data field are zero, this property should be removed from output. If the bit is 1, all input relocatables have the feature. If the bit is 0 or the property is missing, the info is unknown. 2. GNU_PROPERTY_UINT32_OR_LO..GNU_PROPERTY_UINT32_OR_HI #define GNU_PROPERTY_UINT32_OR_LO 0xb0008000 #define GNU_PROPERTY_UINT32_OR_HI 0xb000ffff A bit in the output pr_data field is set if it is set in any relocatable input pr_data fields. If all bits in the the output pr_data field are zero, this property should be removed from output. If the bit is 1, some input relocatables have the feature. If the bit is 0 or the property is missing, the info is unknown. bfd/ * elf-properties.c (_bfd_elf_parse_gnu_properties): Handle GNU_PROPERTY_UINT32_AND_LO, GNU_PROPERTY_UINT32_AND_HI, GNU_PROPERTY_UINT32_OR_LO and GNU_PROPERTY_UINT32_OR_HI. (elf_merge_gnu_properties): Likewise. binutils/ * readelf.c (print_gnu_property_note): Handle GNU_PROPERTY_UINT32_AND_LO, GNU_PROPERTY_UINT32_AND_HI, GNU_PROPERTY_UINT32_OR_LO and GNU_PROPERTY_UINT32_OR_HI. include/ * elf/common.h (GNU_PROPERTY_UINT32_AND_LO): New. (GNU_PROPERTY_UINT32_AND_HI): Likewise. (GNU_PROPERTY_UINT32_OR_LO): Likewise. (GNU_PROPERTY_UINT32_OR_HI): Likewise. ld/ * testsuite/ld-elf/property-and-1.d: New file. * testsuite/ld-elf/property-and-1.s: Likewise. * testsuite/ld-elf/property-and-2.d: Likewise. * testsuite/ld-elf/property-and-2.s: Likewise. * testsuite/ld-elf/property-and-3.d: Likewise. * testsuite/ld-elf/property-and-3.s: Likewise. * testsuite/ld-elf/property-and-4.d: Likewise. * testsuite/ld-elf/property-and-empty.s: Likewise. * testsuite/ld-elf/property-or-1.d: Likewise. * testsuite/ld-elf/property-or-1.s: Likewise. * testsuite/ld-elf/property-or-2.d: Likewise. * testsuite/ld-elf/property-or-2.s: Likewise. * testsuite/ld-elf/property-or-3.d: Likewise. * testsuite/ld-elf/property-or-3.s: Likewise. * testsuite/ld-elf/property-or-4.d: Likewise. * testsuite/ld-elf/property-or-empty.s: Likewise.	5 years ago

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