binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Paul Brook	62b3e31101	2006-02-24 Paul Brook <paul@codesourcery.com> gas/ * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7, arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables. (struct asm_barrier_opt): Define. (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables. (parse_psr): Accept V7M psr names. (parse_barrier): New function. (enum operand_parse_code): Add OP_oBARRIER. (parse_operands): Implement OP_oBARRIER. (do_barrier): New function. (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions. (do_t_cpsi): Add V7M restrictions. (do_t_mrs, do_t_msr): Validate V7M variants. (md_assemble): Check for NULL variants. (v7m_psrs, barrier_opt_names): New tables. (insns): Add V7 instructions. Mark V6 instructions absent from V7M. (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh. (arm_cpu_option_table): Add Cortex-M3, R4 and A8. (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m. (struct cpu_arch_ver_table): Define. (cpu_arch_ver): New. (aeabi_set_public_attributes): Use cpu_arch_ver. Set Tag_CPU_arch_profile. * doc/c-arm.texi: Document new cpu and arch options. gas/testsuite/ * gas/arm/thumb32.d: Fix expected msr and mrs output. * gas/arm/arch7.d: New test. * gas/arm/arch7.s: New test. * gas/arm/arch7m-bad.l: New test. * gas/arm/arch7m-bad.d: New test. * gas/arm/arch7m-bad.s: New test. include/opcode/ * arm.h: Add V7 feature bits. opcodes/ * arm-dis.c (arm_opcodes): Add V7 instructions. (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants. (print_arm_address): New function. (print_insn_arm): Use it. Add 'P' and 'U' cases. (psr_name): New function. (print_insn_thumb32): Add 'U', 'C' and 'D' cases.	21 years ago
H.J. Lu	59cf82fe74	bfd/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * cpu-ia64-opc.c (ins_immu5b): New. (ext_immu5b): Likewise. (elf64_ia64_operands): Add IMMU5b. gas/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b. gas/testsuite/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * gas/ia64/opc-i.s: Add tests for tf. * gas/ia64/pseudo.s: Likewise. * gas/ia64/opc-i.d: Updated. * gas/ia64/pseudo.d: Likewise. include/opcode/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. opcodes/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * ia64-opc-i.c (bXc): New. (mXc): Likewise. (OpX2TaTbYaXcC): Likewise. (TF). Likewise. (TFCM). Likewise. (ia64_opcodes_i): Add instructions for tf. * ia64-opc.h (IMMU5b): New. * ia64-asmtab.c: Regenerated.	21 years ago
H.J. Lu	19a7219fd1	Update copyright years.	21 years ago
H.J. Lu	7f3dfb9cf7	gas/ 2006-02-22 H.J. Lu <hongjiu.lu@intel.com> * config/tc-ia64.c (specify_resource): Add the rule 17 from SDM 2.2. gas/testsuite/ 2006-02-22 H.J. Lu <hongjiu.lu@intel.com> * gas/ia64/dv-raw-err.s: Add check for vmsw.0. * gas/ia64/dv-raw-err.l: Updated. * gas/ia64/opc-b.s: Add vmsw.0 and vmsw.1. * gas/ia64/opc-b.d: Updated. opcodes/ 2006-02-22 H.J. Lu <hongjiu.lu@intel.com> * ia64-gen.c (lookup_regindex): Handle ".vm". (print_dependency_table): Handle '\"'. * ia64-ic.tbl: Updated from SDM 2.2. * ia64-raw.tbl: Likewise. * ia64-waw.tbl: Likewise. * ia64-asmtab.c: Regenerated. * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.	21 years ago
Nick Clifton	d70c5fc7c5	Add support for the Infineon XC16X.	21 years ago
H.J. Lu	a1cfb73ee0	gas/testsuite/ 2006-02-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add "x86-64-drx" and "x86-64-drx-suffix". * gas/i386/x86-64-crx-suffix.d: Minor update. * gas/i386/x86-64-drx-suffix.d: New file. * gas/i386/x86-64-drx.d: Likewise. * gas/i386/x86-64-drx.s: Likewise. opcodes/ 2006-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Use "movZ" for debug register moves.	21 years ago
H.J. Lu	6dd5059a06	gas/testsuite/ 2006-02-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add "x86-64-crx" and "x86-64-crx-suffix". * gas/i386/x86-64-crx-suffix.d: New file. * gas/i386/x86-64-crx.d: Likewise. * gas/i386/x86-64-crx.s: Likewise. opcodes/ 2006-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c ('Z'): Add a new macro. (dis386_twobyte): Use "movZ" for control register moves.	21 years ago
Nick Clifton	8536c657ff	Fix %hi() operator for 64-bit hosts.	21 years ago
Nathan Sidwell	266abb8f72	* bfd/archures.c (bfd_mach_mcf5200, bfd_mach_mcf5206e, bfd_mach_mcf5307, bfd_mach_mcf5407, bfd_mach_mcf528x, bfd_mach_mcfv4e, bfd_mach_mcf521x, bfd_mach_mcf5249, bfd_mach_mcf547x, bfd_mach_mcf548x): Remove. (bfd_mach_mcf_isa_a, bfd_mach_mcf_isa_a_div, bfd_mach_mcf_isa_a_div_mac, bfd_mach_mcf_isa_a_div_emac, bfd_mach_mcf_isa_aplus, bfd_mach_mcf_isa_aplus_mac, bfd_mach_mcf_isa_aplus_emac, bfd_mach_mcf_isa_aplus_usp, bfd_mach_mcf_isa_aplus_usp_mac, bfd_mach_mcf_isa_aplus_usp_emac, bfd_mach_mcf_isa_b, bfd_mach_mcf_isa_b_mac, bfd_mach_mcf_isa_b_emac, bfd_mach_mcf_isa_b_usp_float, bfd_mach_mcf_isa_b_usp_float_mac, bfd_mach_mcf_isa_b_usp_float_emac): New. (bfd_default_scan): Update coldfire mapping. * bfd/bfd-in.h (bfd_m68k_mach_to_features, bfd_m68k_features_to_mach): Declare. * bfd/bfd-in2.h: Rebuilt. * bfd/cpu-m68k.c (arch_info_struct): Add new coldfire machines, adjust legacy names. (m68k_arch_features): New. (bfd_m68k_mach_to_features, bfd_m68k_features_to_mach): Define. * bfd/elf32-m68k.c (elf32_m68k_object_p): New. (elf32_m68k_merge_private_bfd_data): Merge the CF EF flags. (elf32_m68k_print_private_bfd_data): Print the CF EF flags. (elf_backend_object_p): Define. * bfd/ieee.c (ieee_write_processor): Update coldfire machines. * bfd/libbfd.h: Rebuilt. * gas/config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs, mcf5329_control_regs): New. (not_current_architecture, selected_arch, selected_cpu): New. (m68k_archs, m68k_extensions): New. (archs): Renamed to ... (m68k_cpus): ... here. Adjust. (n_arches): Remove. (md_pseudo_table): Add arch and cpu directives. (find_cf_chip, m68k_ip): Adjust table scanning. (no_68851, no_68881): Remove. (md_assemble): Lazily initialize. (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329. (md_init_after_args): Move functionality to m68k_init_arch. (mri_chip): Adjust table scanning. (md_parse_option): Reimplement 'm' processing to add -march & -mcpu options with saner parsing. (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension, m68k_init_arch): New. (s_m68k_cpu, s_m68k_arch): New. (md_show_usage): Adjust. (m68k_elf_final_processing): Set CF EF flags. * gas/config/tc-m68k.h (m68k_init_after_args): Remove. (tc_init_after_args): Remove. * gas/doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options. (M68k-Directives): Document .arch and .cpu directives. * gas/testsuite/gas/m68k/all.exp: Add arch-cpu-1 test. * gas/testsuite/gas/m68k/arch-cpu-1.[sd]: New. * include/elf/m68k.h (EF_CPU32, EF_M68000, EF_CFV4E): Rename to ... (EF_M68K_CPU32, EF_M68K_M68000, EF_M68K_CFV4E): ... here. (EF_M68K_ISA_MASK, EF_M68K_ISA_A, EF_M68K_M68K_ISA_A_PLUS, EF_M68K_ISA_B, EF_M68K_HW_DIV, EF_M68K_MAC_MASK, EF_M68K_MAC, EF_M68K_EMAC, EF_M68K_USP, EF_M68K_FLOAT): New. * include/opcode/m68k.h (m68008, m68ec030, m68882): Remove. (m68k_mask): New. (cpu_m68k, cpu_cf): New. (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. * opcodes/m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features. * binutils/readelf.c (get_machine_flags): Add logic for EF_M68K flags.	21 years ago
David Ung	f1a64f4922	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx, ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d, floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d, nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d, rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.	21 years ago
Arnold Metselaar	9e919b5f1d	fixes related to indexed operands	21 years ago
Arnold Metselaar	c9021189f6	Use unsigned char to hold data to be disassembled.	21 years ago
Andreas Schwab	d99b646536	PR binutils/1486 binutils/: * configure.in: Don't define DISASSEMBLER_NEEDS_RELOCS. * configure: Regenerate. * objdump.c (struct objdump_disasm_info): Don't check for DISASSEMBLER_NEEDS_RELOCS. (objdump_print_addr): Likewise. (disassemble_bytes): Check disassembler_needs_relocs from disassemble_info at run-time instead of DISASSEMBLER_NEEDS_RELOCS at compile-time. (disassemble_section): Likewise. (disassemble_data): Initialize it. include/: * dis-asm.h (struct disassemble_info): Add disassembler_needs_relocs. objdump/: * disassemble.c (disassemble_init_for_target): Set disassembler_needs_relocs for bfd_arch_arm.	21 years ago
Alan Modra	e88d958a4f	split changelogs	21 years ago
Paul Brook	c2fe93275a	2006-01-16 Paul Brook <paul@codesourcery.com> opcodes/ * m68k-opc.c(m68k_opcodes): Fix opcodes for ColdFire f?abss, f?add?, and f?sub? instructions. gas/testsuite/ * gas/m68k/all.exp: Add mcf-fpu. * gas/m68k/mcf-fpu.d: New file. * gas/m68k/mcf-fpu.s: New file.	21 years ago
Nick Clifton	32fba81dfe	Add new Chinese (simplified) translation	21 years ago
Paul Brook	1b3a26b59c	2006-01-05 Paul Brook <paul@codesourcery.com> * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.	21 years ago
DJ Delorie	db313fa614	* m32c-desc.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.	21 years ago
DJ Delorie	54d46aca35	* cgen-ibld.in (extract_normal): Avoid memory range errors. * m32c-ibld.c: Regenerated.	21 years ago
Alan Modra	c85a332d60	* Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.	21 years ago
Nick Clifton	54758c3e39	Fix PicoJava opcodes	21 years ago
Nathan Sidwell	d031aafbfe	Second part of ms1 to mt renaming. * bfd/archures.c (bfd_arch_mt): Renamed. (bfd_mt_arch): Renamed. (bfd_archures_list): Adjusted. * bfd/bfd-in2.h: Rebuilt. * bfd/config.bfd (mt): Remove special case targ_archs. (mt--elf): Rename bfd_elf32_mt_vec. bfd/configure: Rebuilt. * bfd/configure.in (bfd_elf32_mt_vec): Renamed. (selarchs) Remove mt special case. * bfd/cpu-mt.c (arch_info_struct): Adjust. (bfd_mt_arch): Renamed, adjust. * bfd/elf32-mt.c (mt_reloc_type_lookup, mt_info_to_howto_rela, mt_elf_relocate_hi16, mt_final_link_relocate, mt_relocate_section, mt_elf_howto_table): Renamed, adjusted. (mt_elf_gc_mark_hook, mt_elf_gc_sweep_hook, mt_elf_check_relocs, elf32_mt_machine, mt_elf_object_p, mt_elf_set_private_flags, mt_elf_copy_private_bfd_data, mt_elf_merge_private_bfd_data, mt_elf_print_private_bfd_data): Renamed, adjusted. (TARGET_BIG_SYM, TARGET_BIG_NAME, ELF_ARCH, ELF_MACHINE_CODE, ELF_MAXPAGESIZE, elf_info_to_howto, elf_backend_relocate_section, bfd_elf32_bfd_reloc_type_lookup, elf_backend_gc_mark_hook, elf_backend_gc_sweep_hook, elf_backend_check_relocs, eld_backend_object_p, bfd_elf32_bfd_set_private_flags, bfd_elf32_bfd_copy_private_bfd_data, bfd_elf32_bfd_merge_private_bfd_data, bfd_elf32_bfd_print_private_bfd_data): Adjusted. * bfd/libbfd.h: Regenerated. * bfd/reloc.c (BFD_RELOC_MT_PC16, BFD_RELOC_MT_HI16, BFD_RELOC_MT_LO16, BFD_RELOC_MT_GNU_VTINHERIT, BFD_RELOC_MT_GNU_VTENTRY, BFD_RELOC_MT_PCINSN8): Renamed. * bfd/targets.c (bfd_elf32_mt_vec): Renamed. (_bfd_target_vector): Adjusted. * binutils/readelf.c (guess_is_rela): Use EM_MT. (dump_relocations, get_machine_name): Adjust. * cpu/mt.cpu (define-arch, define-isa): Set name to mt. (define-mach): Adjust. * cpu/mt.opc (CGEN_ASM_HASH): Update. (mt_asm_hash, mt_cgen_insn_supported): Renamed. (parse_loopsize, parse_imm16): Adjust. * gas/configure: Rebuilt. * gas/configure.in (mt): Remove special case. * gas/config/tc-mt.c (opcodes/mt-desc.h, opcodes/mt-opc.h): Change #includes. (mt_insn, mt_mach, mt_mach_bitmask, mt_flags, mt_architectures): Rename, adjust. (md_parse_option, md_show_usage, md_begin, md_assemble, md_cgen_lookup_reloc, md_atof): Adjust. (mt_force_relocation, mt_apply_fix, mt_fix_adjustable): Rename, adjust. * gas/config/tc-mt.h (TC_MT): Rename. (LISTING_HEADER, TARGET_ARCH, TARGET_FORMAT): Adjust. (md_apply_fix): Adjust. (mt_apply_fix, mt_fix_adjustable, mt_force_relocation): Rename. (TC_FORCE_RELOCATION, tc_fix_adjustable): Adjust. * gdb/mt-tdep.c (mt_arch_constants, mt_gdb_regnums): Rename, adjust. (mt_register_name, mt_register_type, mt_register_reggroup_p, mt_return_value, mt_skip_prologue, mt_breapoint_from_pc, mt_pseudo_register_read, mt_pseudo_register_write, mt_frame_align, mt_registers_info, mt_push_dummy_call, mt_unwind_cache, mt_frame_unwind_cache, mt_unwind_pc, mt_unwind_dummy_id, mt_frame_this_id, mt_frame_prev_register, mt_frame_base_address, mt_frame_unwind, mt_frame_sniffer, mt_frame_base, mt_gdbarch_init, _initialize_mt_tdep): Rename & adjust. * include/dis-asm.h (print_insn_mt): Renamed. * include/elf/common.h (EM_MT): Renamed. * include/elf/mt.h: Rename relocs, cpu & other defines. * ld/emulparams/elf32mt.sh (ARCH, OUTPUT_FORMAT): Adjust. * opcodes/Makefile.am (HFILES, CFILES, ALL_MACHINES): Adjust. (stamp-mt): Adjust rule. (mt-asm.lo, mt-desc.lo, mt-dis.lo, mt-ibld.lo, mt-opc.lo): Rename & adjust. * opcodes/Makefile.in: Rebuilt. * opcodes/configure: Rebuilt. * opcodes/configure.in (bfd_mt_arch): Rename & adjust. * opcodes/disassemble.c (ARCH_mt): Renamed. (disassembler): Adjust. * opcodes/mt-asm.c: Renamed, rebuilt. * opcodes/mt-desc.c: Renamed, rebuilt. * opcodes/mt-desc.h: Renamed, rebuilt. * opcodes/mt-dis.c: Renamed, rebuilt. * opcodes/mt-ibld.c: Renamed, rebuilt. * opcodes/mt-opc.c: Renamed, rebuilt. * opcodes/mt-opc.h: Renamed, rebuilt. * sid/Makefile.in: Rebuilt. * sid/aclocal.m4: Rebuilt. * sid/configure: Rebuilt. * sid/sid.spec: Adjust. * sid/bsp/Makefile.am: Adjust. * sid/bsp/Makefile.in: Rebuilt. * sid/bsp/aclocal.m4: Rebuilt. * sid/bsp/configrun-sid.in: Adjust. * sid/bsp/pregen/Makefile.in: Rebuilt. * sid/bsp/pregen/mt-gdb.conf: Renamed & rebuilt. * sid/bsp/pregen/mt-gloss.conf: Renamed & rebuilt. * sid/bsp/pregen/pregen-configs.in: Adjust. * sid/component/aclocal.m4: Rebuilt. * sid/component/configure: Rebuilt. * sid/component/tconfig.in: Adjust. * sid/component/bochs/aclocal.m4: Rebuilt. * sid/component/cache/Makefile.in: Rebuilt. * sid/component/cgen-cpu/Makefile.in: Rebuilt. * sid/component/cgen-cpu/aclocal.m4: Rebuilt. * sid/component/cgen-cpu/compCGEN.cxx: Adjust. * sid/component/cgen-cpu/configure: Rebuilt. * sid/component/cgen-cpu/configure.in: Rebult. * sid/component/cgen-cpu/mt/Makefile.am: Adjust. * sid/component/cgen-cpu/mt/Makefile.in: Rebuilt. * sid/component/cgen-cpu/mt/hw-cpu-mt.txt: Adjust. * sid/component/cgen-cpu/mt/mt-cpu.h: Rebuilt. * sid/component/cgen-cpu/mt/mt-decode.cxx: Rebuilt. * sid/component/cgen-cpu/mt/mt-decode.h: Rebuilt. * sid/component/cgen-cpu/mt/mt-defs.h: Rebuilt. * sid/component/cgen-cpu/mt/mt-desc.h: Rebuilt. * sid/component/cgen-cpu/mt/mt-sem.cxx: Rebuilt. * sid/component/cgen-cpu/mt/mt-write.cxx: Rebuilt. * sid/component/cgen-cpu/mt/mt.cxx: Adjust. * sid/component/cgen-cpu/mt/mt.h: Adjust. * sid/component/consoles/Makefile.in: Rebuilt. * sid/component/families/aclocal.m4: Rebuilt. * sid/component/families/configure: Rebuilt. * sid/component/gdb/Makefile.in: Rebuilt. * sid/component/gloss/Makefile.in: Rebuilt. * sid/component/glue/Makefile.in: Rebuilt. * sid/component/ide/Makefile.in: Rebuilt. * sid/component/interrupt/Makefile.in: Rebuilt. * sid/component/lcd/Makefile.in: Rebuilt. * sid/component/lcd/testsuite/Makefile.in: Rebuilt. * sid/component/loader/Makefile.am: Rebuilt. * sid/component/loader/Makefile.in: Rebuilt. * sid/component/mapper/Makefile.in: Rebuilt. * sid/component/mapper/testsuite/Makefile.in: Rebuilt. * sid/component/memory/Makefile.in: Rebuilt. * sid/component/mmu/Makefile.in: Rebuilt. * sid/component/parport/Makefile.in: Rebuilt. * sid/component/profiling/Makefile.in: Rebuilt. * sid/component/rtc/Makefile.in: Rebuilt. * sid/component/sched/Makefile.in: Rebuilt. * sid/component/testsuite/Makefile.in: Rebuilt. * sid/component/timers/aclocal.m4: Rebuilt. * sid/component/timers/configure: Rebuilt. * sid/component/uart/Makefile.in: Rebuilt. * sid/component/uart/testsuite/Makefile.in: Rebuilt. * sid/config/config.sub: Adjust. * sid/config/info.tcl.in: Adjust. * sid/config/sidtargets.m4: Adjust. * sid/doc/Makefile.in: Rebuilt. * sid/main/dynamic/Makefile.am: Rebuilt. * sid/main/dynamic/Makefile.in: Rebuilt. * sid/main/dynamic/aclocal.m4: Rebuilt. * sid/main/dynamic/configure: Rebuilt.	21 years ago
DJ Delorie	eda87aba05	* m32c.cpu (jsri): Fix order so register names aren't treated as symbols. (indexb, indexbd, indexbs, indexl, indexld, indexls, indexw, indexwd, indexws): Fix encodings. * m32c-desc.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.	21 years ago
Nathan Sidwell	4970f871a7	Rename ms1 to mt, part 1	21 years ago
Jan Beulich	272c92178a	opcodes/ 2005-12-08 Jan Beulich <jbeulich@novell.com> * i386-dis.c (MAXLEN): Reduce to architectural limit. (fetch_data): Check for sufficient buffer size.	21 years ago
Jan Beulich	422673a90b	opcodes/ 2005-12-08 Jan Beulich <jbeulich@novell.com> * i386-dis.c (OP_ST): Remove prefix in Intel mode.	21 years ago
Alan Modra	6e50d963b0	* i386-dis.c (dofloat): Handle %rip-relative floating point addressing.	21 years ago
Hans-Peter Nilsson	cf54500c3c	* cris-opc.c (cris_opcodes) <"move" "s,P">: Define using MOVE_M_TO_PREG_OPCODE and MOVE_M_TO_PREG_ZBITS instead of constants.	21 years ago
H.J. Lu	cb712a9ecd	gas/ 2005-12-06 H.J. Lu <hongjiu.lu@intel.com> PR gas/1874 * config/tc-i386.c (match_template): Handle monitor. (process_suffix): Likewise. gas/testsuite/ 2005-12-06 H.J. Lu <hongjiu.lu@intel.com> PR gas/1874 * gas/i386/i386.exp: Add x86-64-prescott for 64bit. * gas/i386/prescott.s: Test address size override for monitor. * gas/i386/prescott.d: Updated. * gas/i386/x86-64-prescott.d: New file. * gas/i386/x86-64-prescott.s: Likewise. include/opcode/ 2005-12-06 H.J. Lu <hongjiu.lu@intel.com> PR gas/1874 * i386.h (i386_optab): Add 64bit support for monitor and mwait. opcodes/ 2005-12-06 H.J. Lu <hongjiu.lu@intel.com> PR gas/1874 * i386-dis.c (address_mode): New enum type. (address_mode): New variable. (mode_64bit): Removed. (ckprefix): Updated to check address_mode instead of mode_64bit. (prefix_name): Likewise. (print_insn): Likewise. (putop): Likewise. (print_operand_value): Likewise. (intel_operand_size): Likewise. (OP_E): Likewise. (OP_G): Likewise. (set_op): Likewise. (OP_REG): Likewise. (OP_I): Likewise. (OP_I64): Likewise. (OP_OFF): Likewise. (OP_OFF64): Likewise. (ptr_reg): Likewise. (OP_C): Likewise. (SVME_Fixup): Likewise. (print_insn): Set address_mode. (PNI_Fixup): Add 64bit and address size override support for monitor and mwait.	21 years ago
Hans-Peter Nilsson	cdedc9f07f	* cris-dis.c (bytes_to_skip): Handle new parameter prefix_matchedp. (print_with_operands): Check for prefix when [PC+] is seen.	21 years ago
Dave Brolley	3609e0feb6	2005-12-02 Dave Brolley <brolley@redhat.com> * configure.in (cgen_files): Add cgen-bitset.lo. (ta): Add cgen-bitset.lo when arch==bfd_cris_arch. * Makefile.am (CFILES): Add cgen-bitset.c. (ALL_MACHINES): Add cgen-bitset.lo. (cgen-bitset.lo): New target. * cgen-opc.c (cgen_bitset_create, cgen_bitset_init, cgen_bitset_clear) (cgen_bitset_add, cgen_bitset_set, cgen_bitset_contains) (cgen_bitset_compare, cgen_bitset_intersect_p, cgen_bitset_copy) (cgen_bitset_union): Moved from here ... * cgen-bitset.c: ... to here. New file. * Makefile.in: Regenerated. * configure: Regenerated.	21 years ago
Jim Wilson	aa2273ba99	Fix 32-bit host/target --enable-targets=all build failure from Doug Evans. * ia64-gen.c (_opcode_int64_low, _opcode_int64_high, opcode_fprintf_vma): New. (print_main_table): New opcode_fprintf_vma instead of fprintf_vma.	21 years ago
Alan Modra	ce7a772b48	* ppc-opc.c (powerpc_opcodes): Add frin,friz,frip,frim. Correct frsqrtes.	21 years ago
Thiemo Seufer	0499d65b9b	* mips.h: Assign 'm'/'M' codes to MIPS16e save/restore instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for save/restore encoding of the args field. * mips16-opc.c: Add MIPS16e save/restore opcodes. * mips-dis.c (print_mips16_insn_arg): Handle printing of 'm'/'M' codes for save/restore. * config/tc-mips.c (mips16_ip): Add handling of 'm' and 'M' codes for the MIPS16e save/restore instructions. * gas/mips/mips.exp: Run new save/restore tests. * gas/testsuite/gas/mips/mips16e-save.s: New test for generating different styles of save/restore instructions. * gas/testsuite/gas/mips/mips16e-save.d: New.	21 years ago
Andreas Schwab	dc82c973b3	* m68k-dis.c (print_insn_m68k): Only match FPU insns with coprocessor ID 1.	21 years ago
Nick Clifton	dbb33a874e	* m32c-desc.c: Regenerated.	21 years ago
Nathan Sidwell	6f84a2a649	bfd: Add ms2. * archures.c (bfd_mach_ms2): Define. * cpu-ms1.c (arch_info_struct): Add ms2 stanza. * elf32-ms1.c (elf32_ms1_machine): Add ms2 case. (ms1_elf_merge_private_bfd_data): Remove unused variables. Add correct merging logic, with workaround. (ms1_elf_print_private_bfd_data): Add ms2 case. * reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc. * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. cpu: Add ms2 * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and model. (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr, f-cb2incr, f-rc3): New fields. (LOOP): New instruction. (JAL-HAZARD): New hazard. (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr): New operands. (mul, muli, dbnz, iflush): Enable for ms2 (jal, reti): Has JAL-HAZARD. (ldctxt, ldfb, stfb): Only ms1. (fbcb): Only ms1,ms1-003. (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs, fbcbincrs, mfbcbincrs): Enable for ms2. (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns. * ms1.opc (parse_loopsize): New. (parse_imm16): hi16/lo16 relocs are applicable to IMM16L. (print_pcrel): New. gas: Add ms2. * config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1. (ms1_architectures): Add ms2. (md_parse_option): Add ms2. (md_show_usage): Add ms2. (md_assemble): Add JAL_HAZARD detection logic. (md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case. * doc/c-ms1.texi: New. * doc/all.texi: Add MS1. * doc/Makefile.am (CPU_DOCS): Add c-ms1.texi. * doc/Makefile.in: Rebuilt. * doc/Makefile: Rebuilt. gas/testsuite: Add ms2. * gas/ms1/allinsn.d: Adjust pcrel disassembly. * gas/ms1/errors.exp: Fix target triplet. * gas/ms1/ms1-16-003.d: Adjust pcrel disassembly. * gas/ms1/ms1-16-003.s: Tweak label. * gas/ms1/ms1.exp: Adjust target triplet. Add ms2 test. * gas/ms1/ms2.d, gas/ms1/ms2.s: New. * gas/ms1/relocs.d: Adjust expected machine name and pcrel disassembly. * gas/ms1/relocs.exp: Adjust target triplet. include: Add ms2. * elf/ms1.h (EF_MS1_CPU_MS2): New. opcodes: Add ms2. * ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h: Regenerated.	21 years ago
Steve Ellcey	a541e3cedd	* configure: Regenerate after modifying bfd/warning.m4.	21 years ago
Alan Modra	3e7d61b225	* i386-dis.c (ckprefix): Handle rex on fwait. Don't print ignored rex prefixes here. (print_insn): Instead, handle them similarly to fwait followed by non-fp insns.	21 years ago
H.J. Lu	a92e0d0a05	2005-11-02 H.J. Lu <hongjiu.lu@intel.com> * iq2000-desc.c: Regenerated. * iq2000-desc.h: Likewise. * iq2000-dis.c: Likewise. * iq2000-opc.c: Likewise.	21 years ago
Paul Brook	36b0c57df5	2005-11-02 Paul Brook <paul@codesourcery.com> * arm-dis.c (print_insn_thumb32): Word align blx target address.	21 years ago
Alan Modra	9a2ff3f50c	* arm-dis.c (print_insn): Warning fix.	21 years ago
H.J. Lu	9e5169a8fa	ld/ binutils/ opcodes/ 2005-10-30 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am: Run "make dep-am". * Makefile.in: Regenerated. * dep-in.sed: Replace " ./" with " ".	21 years ago
Dave Brolley	fb53f5a81a	2005-10-28 Dave Brolley <brolley@redhat.com> * All CGEN-generated sources: Regenerate. Contribute the following changes: 2005-09-19 Dave Brolley <brolley@redhat.com> * disassemble.c (disassemble_init_for_target): Add 'break' to case for bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for bfd_arch_m32c case. 2005-02-16 Dave Brolley <brolley@redhat.com> * cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename cgen_isa_mask_* to cgen_bitset_. cgen-opc.c: Likewise. 2003-11-28 Richard Sandiford <rsandifo@redhat.com> * cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas. * -dis.c: Regenerate. 2003-06-05 DJ Delorie <dj@redhat.com> cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign it, as it may point to a reused buffer. Set prev_isas when we change cpus. 2002-12-13 Dave Brolley <brolley@redhat.com> * cgen-opc.c (cgen_isa_mask_create): New support function for CGEN_ISA_MASK. (cgen_isa_mask_init): Ditto. (cgen_isa_mask_clear): Ditto. (cgen_isa_mask_add): Ditto. (cgen_isa_mask_set): Ditto. (cgen_isa_supported): Ditto. (cgen_isa_mask_compare): Ditto. (cgen_isa_mask_intersection): Ditto. (cgen_isa_mask_copy): Ditto. (cgen_isa_mask_combine): Ditto. * cgen-dis.in (libiberty.h): #include it. (isas): Renamed from 'isa' and now (CGEN_ISA_MASK ). (print_insn_@arch@): Use CGEN_ISA_MASK and support functions. Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm. * Makefile.in: Regenerated.	21 years ago
DJ Delorie	c6552317c1	* m32c.cpu (Imm-8-s4n, Imm-12-s4n): New. (arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn, arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which imm operand is needed. (adjnz, sbjnz): Pass the right operands. (unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach, unary-insn): Add -g variants for opcodes that need to support :G. (not.BW:G, push.BW:G): Call it. (stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb, stzx16-imm8-imm8-abs16): Fix operand typos. * m32c.opc (m32c_asm_hash): Support bnCND. (parse_signed4n, print_signed4n): New. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.	21 years ago
DJ Delorie	f75eb1c004	* m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New. (mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn, mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn): dsp8[sp] is signed. (mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff). (mov.BW:S r0,r1): Fix typo r1l->r1. (tst): Allow :G suffix. * m32c.opc (parse_signed24): New, for -0x800000..0xffffff. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.	21 years ago
Paul Brook	f1022c90ad	2005-10-26 Paul Brook <paul@codesourcery.com> gas/ * config/tc-arm.c (insns): Correct "sel" entry. gas/testsuite/ * gas/arm/archv6.d: Adjust expected output. opcodes/ * arm-dis.c (arm_opcodes): Correct "sel" entry.	21 years ago
Alan Modra	e277c00b2d	* m32r.opc (parse_hi16): Do not assume a 32-bit host word size.	21 years ago
DJ Delorie	92e0a9414c	* m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by making one a macro of the other. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.	21 years ago
Nick Clifton	3c9b82baee	Add support for the Z80 processor family	21 years ago

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906 Commits (ebdca51ad97f11dff355fb709a77403c8187be3f)