binutils-gdb

Commit Graph

Author	SHA1	Message	Date
H.J. Lu	5fb776a637	New Year - binutils ChangeLog rotation	12 years ago
Maciej W. Rozycki	b0b0c9fc49	* nds32-asm.c (parse_operand): Fix out-of-range integer constant.	12 years ago
Kuan-Lin Chen	6b9d3259c3	Add system register and embedded debug register support. Add two more as test files for user special and system register. Fix typo. 2013-12-17 Kuan-Lin Chen <kuanlinchentw@gmail.com> * gas/nds32/nds32.exp: Add system and user special register tests. * gas/nds32/sys-reg.s: New test. * gas/nds32/sys-reg.d: Likewise. * gas/nds32/usr-spe-reg.s: Likewise. * gas/nds32/usr-spe-reg.d: Likewise. * gas/nds32/alu-2.d: Delete the new blank line at EOF. * gas/nds32/br-1.d: Likewise. * gas/nds32/br-2.d: Likewise. * gas/nds32/ji-jr.d: Likewise. * gas/nds32/lsi.d: Likewise. * nds32-dis.c (sr_map): Add system register table for disassembling. (usr_map): Fix typo. * nds32-asm.c (keyword_sr): Add embedded debug registers.	13 years ago
Michael Zolotukhin	4a357820ad	Properly handle ljmp/lcall with invalid MODRM byte gas/testsuite/ 2013-12-17 Michael Zolotukhin <michael.v.zolotukhin@gmail.com> * gas/i386/disassem.s: New. * gas/i386/disassem.d: Likewise. * gas/i386/x86-64-disassem.s: Likewise. * gas/i386/x86-64-disassem.d: Likewise. * gas/i386/i386.exp: Run disassem and x86-64-disassem. opcodes/ 2013-12-17 Michael Zolotukhin <michael.v.zolotukhin@gmail.com> * i386-dis.c (MOD_FF_REG_3): New. (MOD_FF_REG_5): Likewise. (mod_table): Add MOD_FF_REG_3 and MOD_FF_REG_5. (reg_table): Use MOD_FF_REG_3 and MOD_FF_REG_5.	13 years ago
Andrew Bennett	dc76d75756	Add support to show the symbolic names of the MIPS CP1 registers. 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> gas/testsuite/gas/mips/ * mips.exp: Add CP1 register name tests. * cp1-names-mips32.d: New test. * cp1-names-mips32r2.d: New test. * cp1-names-mips64.d: New test. * cp1-names-mips64r2.d: New test. * cp1-names-numeric.d: New test. * cp1-names-r3000.d: New test. * cp1-names-r4000.d: New test. * cp1-names-sb1.d: New test. * cp1-names.s: New test. * micromips-insn32.d: Add the correct symbolic names for the CP1 registers. * micromips-noinsn32.d: Likewise. * micromips-trap.d: Likewise. * micromips.d: Likewise. opcodes/ * mips-dis.c: Add mips_cp1_names pointer. (mips_cp1_names_numeric): New array. (mips_cp1_names_mips3264): New array. (mips_arch_choice): Add cp1_names. (mips_arch_choices): Add relevant cp1 register name array to each of the elements. (set_default_mips_dis_options): Add support for setting up the mips_cp1_names pointer. (parse_mips_dis_option): Add support for the cp1-names command line variable. Also setup the mips_cp1_names pointer. (print_reg): Print out name of the cp1 register.	13 years ago
Andrew Bennett	e269fea784	Range of element index is too large on MIPS MSA element selection instructions. The element index range for the following MIPS MSA instructions: sldi, splati, copy_s, copy_u, insert and insve is 1 bit too large. This patch fixes this issue. ChangeLog: gas/testsuite/gas/mips/ * msa.s: Reduced maximum element index range for sldi, splati, copy_s, copy_u, insert and insve instructions. * msa64.s: Likewise. * micromips@msa.d: Likewise. * micromips@msa64.d: Likewise. * msa.d: Likewise. * msa64.d: Likewise. include/opcode/ * mips.h: Updated description of +o, +u, +v and +w for MIPS and microMIPS. opcodes/ * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u, +v and +w. (micromips_opcodes): Reduced element index range for sldi, splati, copy_s, copy_u, insert and insve instructions. * opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u, +v and +w. (mips_builtin_opcodes): Reduced element index range for sldi, splati, copy_s, copy_u, insert and insve instructions.	13 years ago
Jan-Benedict Glaw	1332de018c	2013-12-13 Jan-Benedict Glaw <jbglaw@lug-owl.de> * nds32-dis.c (mnemonic_96): Fix typo. [BR]: https://sourceware.org/ml/binutils/2013-12/msg00184.html	13 years ago
Kuan-Lin Chen	35c081572f	Add support for Andes NDS32: BFD: * Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Add nds32 files. * Makefile.in: Regenerate. * archures.c (bfd_nds32_arch): Add nds32 target. * bfd-in2.h: Regenerate. * config.bfd (nds32le--linux): Add bfd_elf32_nds32lelin_vec and bfd_elf32_nds32belin_vec. (nds32be--linux): Likewise. (nds32le--): Add bfd_elf32_nds32le_vec and bfd_elf32_nds32be_vec. (nds32be--): Likewise. configure.in (bfd_elf32_nds32be_vec): Add elf32-nds32.lo. (bfd_elf32_nds32le_vec): Likewise. (bfd_elf32_nds32belin_vec): Likewise. (bfd_elf32_nds32lelin_vec): Likewise. * configure: Regenerate. * cpu-nds32.c: New file for nds32. * elf-bfd.h: Add NDS32_ELF_DATA. * elf32-nds32.c: New file for nds32. * elf32-nds32.h: New file for nds32. * libbfd.h: Regenerate. * reloc.c: Add relocations for nds32. * targets.c (bfd_elf32_nds32be_vec): New declaration for nds32. (bfd_elf32_nds32le_vec): Likewise. (bfd_elf32_nds32belin_vec): Likewise. (bfd_elf32_nds32lelin_vec): Likewise. BINUTILS: * readelf.c: Include elf/nds32.h (guess_is_rela): Add case for EM_NDS32. (dump_relocations): Add case for EM_NDS32. (decode_NDS32_machine_flags): New. (get_machine_flags): Add case for EM_NDS32. (is_32bit_abs_reloc): Likewise. (is_16bit_abs_reloc): Likewise. (process_nds32_specific): New. (process_arch_specific): Add case for EM_NDS32. * NEWS: Announce Andes nds32 support. * MAINTAINERS: Add nds32 maintainers. TESTSUITE: * binutils-all/objdump.exp: Add NDS32 cpu. * binutils-all/readelf.r: Skip extra reloc created by NDS32. GAS: * Makefile.am (TARGET_CPU_CFILES): Add config/tc-nds32.c. (TARGET_CPU_HFILES): Add config/tc-nds32.h. * Makefile.in: Regenerate. * configure.in (nds32): Add nds32 target extension config support. * configure.tgt : Add case for nds32--elf and nds32--linux. * configure: Regenerate. * config/tc-nds32.c: New file for nds32. * config/tc-nds32.h: New file for nds32. * doc/Makefile.am (CPU_DOCS): Add c-nds32.texi. * doc/Makefile.in: Regenerate. * doc/as.texinfo: Add nds32 options. * doc/all.texi: Set NDS32. * doc/c-nds32.texi: New file dor nds32 document. * NEWS: Announce Andes nds32 support. TESTSUITE: * gas/all/gas.exp: Add expected failures for NDS32. * gas/elf/elf.exp: Likewise. * gas/lns/lns.exp: Use alternate test. * gas/macros/irp.d: Skip for NDS32. * gas/macros/macros.exp: Skip some tests for the NDS32. * gas/macros/rept.d: Skip for NDS32. * gas/macros/test3.d: Skip for NDS32. * gas/nds32: New directory. * gas/nds32/alu-1.s: New test. * gas/nds32/alu-1.d: Likewise. * gas/nds32/alu-2.s: Likewise. * gas/nds32/alu-2.d: Likewise. * gas/nds32/br-1.d: Likewise. * gas/nds32/br-1.s: Likewise. * gas/nds32/br-2.d: Likewise. * gas/nds32/br-2.s: Likewise. * gas/nds32/ji-jr.d: Likewise. * gas/nds32/ji-jr.s: Likewise. * gas/nds32/ls.d: Likewise. * gas/nds32/ls.s: Likewise. * gas/nds32/lsi.d: Likewise. * gas/nds32/lsi.s: Likewise. * gas/nds32/to-16bit-v1.d: Likewise. * gas/nds32/to-16bit-v1.s: Likewise. * gas/nds32/to-16bit-v2.d: Likewise. * gas/nds32/to-16bit-v2.s: Likewise. * gas/nds32/to-16bit-v3.d: Likewise. * gas/nds32/to-16bit-v3.s: Likewise. * gas/nds32/nds32.exp: New test driver. LD: * Makefile.am (ALL_EMULATION_SOURCES): Add nds32 target. * Makefile.in: Regenerate. * configure.tgt: Add case for nds32le--elf, nds32be--elf, nds32le--linux-gnu, and nds32be--linux-gnu. * emulparams/nds32belf.sh: New file for nds32. * emulparams/nds32belf_linux.sh: Likewise. * emulparams/nds32belf16m.sh: Likewise. * emulparams/nds32elf.sh: Likewise. * emulparams/nds32elf_linux.sh: Likewise. * emulparams/nds32elf16m.sh: Likewise. * emultempl/nds32elf.em: Likewise. * scripttempl/nds32elf.sc}: Likewise. * gen-doc.texi: Set NDS32. * ld.texinfo: Set NDS32. * NEWS: Announce Andes nds32 support. TESTSUITE: * lib/ld-lib.exp: Add NDS32 to list of targets that do not support shared library generation. * ld-nds32: New directory. * ld-nds32/branch.d: New test. * ld-nds32/branch.ld: New test. * ld-nds32/branch.s: New test. * ld-nds32/diff.d: New test. * ld-nds32/diff.ld: New test. * ld-nds32/diff.s: New test. * ld-nds32/gp.d: New test. * ld-nds32/gp.ld: New test. * ld-nds32/gp.s: New test. * ld-nds32/imm.d: New test. * ld-nds32/imm.ld: New test. * ld-nds32/imm.s: New test. * ld-nds32/imm_symbol.s: New test. * ld-nds32/relax_jmp.d: New test. * ld-nds32/relax_jmp.ld: New test. * ld-nds32/relax_jmp.s: New test. * ld-nds32/relax_load_store.d: New test. * ld-nds32/relax_load_store.ld: New test. * ld-nds32/relax_load_store.s: New test. * ld-nds32/nds32.exp: New file. OPCODES: * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c and nds32-dis.c. * Makefile.in: Regenerate. * configure.in: Add case for bfd_nds32_arch. * configure: Regenerate. * disassemble.c (ARCH_nds32): Define. * nds32-asm.c: New file for nds32. * nds32-asm.h: New file for nds32. * nds32-dis.c: New file for nds32. * nds32-opc.h: New file for nds32. INCLUDE: * dis-asm.h (print_insn_nds32): Add nds32 target. * elf/nds32.h: New file for nds32. * opcode/nds32.h: New file for nds32.	13 years ago
Nick Clifton	61d4014c3c	* s390-mkopc.c (dumpTable): Provide a format string to printf so that compiling with -Werror=format-security does not produce an error.	13 years ago
Yufeng Zhang	87b8eed7fb	gas/testsuite/ * gas/aarch64/msr.s: Add tests. * gas/aarch64/msr.d: Update. include/opcode * aarch64.h (aarch64_pstatefields): Change element type to aarch64_sys_reg. opcodes/ * aarch64-opc.c (aarch64_pstatefields): Update.	13 years ago
Catherine Moore	8f8c3854e0	2013-11-19 Catherine Moore <clm@codesourcery.com> * micromips-opc.c (LM): Define. (micromips_opcodes): Add LM to load instructions. * mips-opc.c (prefe): Add LM attribute.	13 years ago
Yufeng Zhang	a203d9b72f	Revert "Add support for AArch64 trace unit registers." This reverts commit `75468c93c1`.	13 years ago
Yufeng Zhang	75468c93c1	gas/ * config/tc-aarch64.c (set_other_error): New function. (parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set the variable to which it points with 'o'. (parse_operands): Update; check for write to read-only system registers or read from write-only ones. gas/testsuite/ * gas/aarch64/diagnostic.s: Add tests. * gas/aarch64/diagnostic.l: Update. * gas/aarch64/tracereg-illegal.d: New file. * gas/aarch64/tracereg-illegal.l: Ditto. * gas/aarch64/tracereg-illegal.s: Ditto. * gas/aarch64/tracereg.d: Ditto. * gas/aarch64/tracereg.s: Ditto. include/opcode * aarch64.h (aarch64_sys_reg_readonly_p): New declaration. (aarch64_sys_reg_writeonly_p): Ditto. opcodes/ * aarch64-opc.c (CPENT): New define. (F_READONLY, F_WRITEONLY): Likewise. (aarch64_sys_regs): Add trace unit registers. (aarch64_sys_reg_readonly_p): New function. (aarch64_sys_reg_writeonly_p): Ditto.	13 years ago
Maciej W. Rozycki	caeba11c83	MIPS/opcodes: Add MFCR and MTCR data dependencies * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and "mtcr".	13 years ago
Catherine Moore	b83a9376e9	Fix ChangeLog entries from earlier commit.	13 years ago
H.J. Lu	d56da83e58	Remove CpuNop from CPU_K6_2_FLAGS PR gas/16140 * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS. * i386-init.h: Regenerated.	13 years ago
Yufeng Zhang	49eec19300	gas/ * config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg; call aarch64_sys_reg_deprecated_p and warn about the deprecated system registers. gas/testsuite/ * gas/aarch64/deprecated.d: New file. * gas/aarch64/deprecated.l: New file. * gas/aarch64/deprecated.s: New file. * gas/aarch64/sysreg-1.s: Add tests. * gas/aarch64/sysreg-1.d: Add tests. include/opcode/ * aarch64.h (aarch64_sys_reg): New typedef. (aarch64_sys_regs): Change to define with the new type. (aarch64_sys_reg_deprecated_p): Declare. opcodes/ * aarch64-opc.c (F_DEPRECATED): New macro. (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with F_DEPRECATED. (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on AARCH64_OPND_SYSREG.	13 years ago
Yufeng Zhang	68a6428382	gas/ * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1. gas/testsuite/ * gas/aarch64/alias.s: Add tests. * gas/aarch64/alias.d: Update. * gas/aarch64/no-aliases.d: Update. * gas/aarch64/diagnostic.s: Add tests. * gas/aarch64/diagnostic.l: Update. * gas/aarch64/illegal.s: Add tests. * gas/aarch64/illegal.l: Update. include/opcode/ * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. (enum aarch64_opnd): Add AARCH64_OPND_COND1. opcodes/ * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'. (convert_from_csel): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1. (aarch64_print_operand): Handle AARCH64_OPND_COND1. * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of COND for cinc, cset, cinv, csetm and cneg. (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1. * aarch64-asm-2.c: Re-generated. * aarch64-dis-2.c: Ditto. * aarch64-opc-2.c: Ditto.	13 years ago
Yufeng Zhang	4e50d5f863	opcodes/ * aarch64-opc.c (set_syntax_error): New function. (operand_general_constraint_met_p): Replace set_other_error with set_syntax_error. gas/testsuite/ * gas/aarch64/diagnostic.s: Add tests of ldp/stp. * gas/aarch64/diagnostic.l: Update.	13 years ago
Andreas Arnez	7d4a7d107a	S/390: Disassemble 31-bit binaries with "zarch" opcode set by default Currently the disassembler for s390 (by default) assumes that a 31-bit binary was compiled in "ESA" mode -- and then only disassembles a limited opcode set. The change upgrades the default to the full "zarch" opcode set even for 31-bit binaries. opcodes/ * s390-dis.c (init_disasm): Default to full 'zarch' opcode availability even for 31-bit programs.	13 years ago
Ramana Radhakrishnan	8518117318	Fix neon vshll disassembly. opcodes/ 2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * arm-dis.c (neon_opcodes): Adjust print string for vshll. gas/testsuite/ 2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gas/arm/neon-cov.d: Adjust output.	13 years ago
Chao-ying Fu	4edbb8e35a	2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x, +~, +!, +@, +#, +$, +%, +^, +&, +, +\|. (MSA): New define. (MSA64): New define. (micromips_opcodes): Add MSA instructions. mips-dis.c (msa_control_names): New array. (mips_abi_choice): Add ASE_MSA to mips32r2. Remove ASE_MDMX from mips64r2. Add ASE_MSA and ASE_MSA64 to mips64r2. (parse_mips_dis_option): Handle -Mmsa. (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL. (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX. (print_mips_disassembler_options): Print -Mmsa. * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +\|. (MSA): New define. (MSA64): New define. (mips_builtin_op): Add MSA instructions.	13 years ago
Sandra Loosemore	ae335a4e26	2013-10-13 Sandra Loosemore <sandra@codesourcery.com> opcodes/ * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba" as the primary name of r30. gas/ * config/tc-nios2.c (nios2_consume_arg): Make the "ba" warning also test/refer to "sstatus". Reformat the warning message. gas/testsuite/ * gas/nios2/warn_nobreak.l: Update text of warning messages. * gas/nios2/registers.s: Use "sstatus" rather than "ba" as the primary name of r30. * gas/nios2/registers.d: Likewise.	13 years ago
H.J. Lu	6c75cc62a3	Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcn gas/testsuite/ * gas/i386/mpx.s: Remove bndcl/bndcu/bndcn tests with AX. * gas/i386/x86-64-mpx.s: Likwise. * gas/i386/mpx.d: Updated. * gas/i386/x86-64-mpx.d: Likewise. opcodes/ * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the default case. (OP_E_register): Move v_bnd_mode alongside m_mode. * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants. Drop Reg16 and Disp16. Add NoRex64. (bndmk, bndmov, bndldx, bndstx): Drop Disp16. * i386-tbl.h: Re-generate.	13 years ago
Sean Keys	0e1c243401	* Removed short_hand field from opcode table and refactored assembler/disassember accordingly. Testsuite checkout OK.	13 years ago
Roland McGrath	9ce09ba2d7	opcodes/ * i386-dis.c (oappend_maybe_intel): New function. (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it. (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise. (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.	13 years ago
Roland McGrath	2b4e983c39	opcodes/ * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress possible compiler warnings when the union's initializer is actually meant for the 'preg' enum typed member. * crx-opc.c (REG): Likewise.	13 years ago
Roland McGrath	7903e53098	opcodes/ * v850-dis.c (v850_cacheop_codes, v850_prefop_codes): Remove duplicate const qualifier.	13 years ago
Jan Beulich	79e0e31dc9	opcodes/ 2013-10-08 Jan Beulich <jbeulich@suse.com> * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified. (clflush): Use Anysize instead of Byte\|Unspecified. (prefetch): Likewise. i386-tbl.h: Re-generate.	13 years ago
Chao-ying Fu	45099dfad2	2013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com> * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.	13 years ago
H.J. Lu	916fae9135	Add Size64 to movq/vmovq with Reg64 operand * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand. * i386-init.h: Regenerated.	13 years ago
Saravanan Ekanathan	c7b0bd56ce	Add AMD bdver4 support. gas/ * config/tc-i386.c (cpu_arch): Add CPU_BDVER4_FLAGS. * doc/c-i386.texi: Add -march=bdver4 option. gas/testsuite/ * gas/i386/i386.exp: Run bdver4 test cases. * gas/i386/nops-1-bdver4.d: New. * gas/i386/arch-10-bdver4.d: New. * gas/i386/x86-64-nops-1-bdver4.d: New. * gas/i386/x86-64-arch-2-bdver4.d: New. opcodes/ * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS. * i386-init.h: Regenerated.	13 years ago
Alan Modra	cc9afea3e4	* libtool.m4 (_LT_ENABLE_LOCK <ld -m flags>): Remove non-canonical ppc host match. Support little-endian powerpc linux hosts. Regenerate binutils configure files.	13 years ago
Richard Sandiford	e3f9e85275	opcodes/ * s390-opc.txt (clih): Make the immediate unsigned. gas/testsuite/ * gas/s390/zarch-z196.s, gas/s390/zarch-z196.d: Test CLIH with 4000000000.	13 years ago
Nick Clifton	74db7efbe3	PR gas/15914 * config/tc-arm.c (T16_32_TAB): Add _udf. (do_t_udf): New function. (insns): Add "udf". * gas/arm/udf-bad.s: New file. * gas/arm/udf-bad.d: New file. * gas/arm/udf-bad.l: New file. * gas/arm/udf.s: New file. * gas/arm/udf.d: New file. * gas/arm/udf.l: New file. * arm-dis.c (arm_opcodes): Add udf. (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION. (thumb32_opcodes): Add udf.w. (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.	13 years ago
Andreas Krebbel	c8094e012c	2013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra. For the load fp integer instructions only the suppression flag was new with z196 version.	13 years ago
Nick Clifton	7e10503172	* aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the immediate is not suitable for the 32-bit ABI. * gas/aarch64/illegal.s: Add illegal constant for logical operation. * gas/aarch64/illegal.l: Add expected error message.	13 years ago
Maciej W. Rozycki	fb6f389526	opcodes/ * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps", replacing NODS. gas/testsuite/ * gas/testsuite/gas/mips/micromips-insn32.d: Adjust for delay slot scheduling of ALNV.PS. * gas/testsuite/gas/mips/micromips-noinsn32.d: Likewise. * gas/testsuite/gas/mips/micromips-trap.d: Likewise. * gas/testsuite/gas/mips/micromips.d: Likewise. * gas/testsuite/gas/mips/micromips@alnv_ps-swap.d: Likewise.	13 years ago
Nick Clifton	9aff4b7ac1	PR binutils/15834 Fix typos: --- bfd/bfdio.c \| 2 +- bfd/elf32-spu.c \| 2 +- bfd/elfnn-aarch64.c \| 2 +- binutils/od-xcoff.c \| 2 +- config/tcl.m4 \| 2 +- gas/config/tc-ia64.c \| 2 +- gas/config/tc-sparc.c \| 2 +- gas/config/tc-z80.c \| 12 ++++++------ gas/doc/c-i386.texi \| 6 +++--- gas/doc/c-m32r.texi \| 2 +- gas/testsuite/gas/d10v/instruction_packing.d \| 2 +- gas/testsuite/gas/z80/atend.d \| 2 +- gold/object.h \| 2 +- include/gdb/remote-sim.h \| 2 +- include/opcode/ChangeLog \| 2 +- include/opcode/i960.h \| 2 +- ld/testsuite/ld-mips-elf/mips16-pic-1.inc \| 2 +- opcodes/aarch64-asm.c \| 2 +- opcodes/aarch64-dis.c \| 2 +- opcodes/msp430-dis.c \| 2 +-	13 years ago
Richard Sandiford	5e0dc5bae9	include/opcode/ * mips.h (M_DEXT, M_DINS): Delete. opcodes/ * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases. Use +H rather than +C for the real "dext". * mips-opc.c (mips_builtin_opcodes): Likewise. gas/ * config/tc-mips.c (report_bad_range, report_bad_field): Delete. (macro): Remove M_DEXT and M_DINS handling. gas/testsuite/ * gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS error messages to have the same form as the EXT and INS ones. * gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d, gas/mips/micromips.d, gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect "dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".	13 years ago
Richard Sandiford	0f35dbc4d9	include/opcode/ * mips.h (OP_OPTIONAL_REG): New mips_operand_type. (mips_optional_operand_p): New function. opcodes/ * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros. * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG and OPTIONAL_MAPPED_REG. * mips-opc.c (decode_mips_operand): Likewise. * mips16-opc.c (decode_mips16_operand): Likewise. * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG. gas/ * config/tc-mips.c (operand_reg_mask, match_operand): Handle OP_OPTIONAL_REG. (mips_ip, mips16_ip): Use mips_optional_operand_p to check for optional operands.	13 years ago
H.J. Lu	79ceb7cb73	Remove PREFIX_EVEX_0F3A3E and PREFIX_EVEX_0F3A3F * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed. (PREFIX_EVEX_0F3A3F): Likewise. * i386-dis-evex.h (evex_table): Updated.	13 years ago
Richard Sandiford	ee5734f078	opcodes/ 2013-08-06 Jürgen Urban <JuergenUrban@gmx.de> * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of VCLIPW. gas/ 2013-08-06 Jürgen Urban <JuergenUrban@gmx.de> * config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel suffixes to be elided too. (mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here. (mips_ip): Assume .xyzw if no VU0 suffix is specified. Allow +N to be omitted too. gas/testsuite/ 2013-08-06 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l, gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d: Allow single-channel suffixes to be elided.	13 years ago
Eric Botcazou	d6787ef95c	gas/ * config/tc-sparc.c (sparc_arch_types): Add leon. (sparc_arch): Move sparc4 around and add leon. (sparc_target_format): Document -Aleon. * doc/c-sparc.texi: Likewise. include/ * opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON. opcodes/ * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for bfd_mach_sparc. * sparc-opc.c (MASK_LEON): Define. (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON. (letandleon): New macro. (v9andleon): Likewise. (sparc_opc): Add leon. (umac): Enable for letandleon. (smac): Likewise. (casa): Enable for v9andleon. (cas): Likewise. (casl): Likewise.	13 years ago
Richard Sandiford	14daeee3ae	include/opcode/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips.h: Document new VU0 operand characters. (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types. (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R) (OP_REG_R5900_ACC): New mips_reg_operand_types. (INSN2_VU0_CHANNEL_SUFFIX): New macro. (mips_vu0_channel_mask): Declare. opcodes/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (print_vu0_channel): New function. (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (print_insn_args): Handle '#'. (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX. * mips-opc.c (mips_vu0_channel_mask): New constant. (decode_mips_operand): Handle new VU0 operand types. (VU0, VU0CH): New macros. (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E" for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2. Use "+6" rather than "G" for QMFC2 and QMTC2. gas/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * config/tc-mips.c (MAX_OPERANDS): Bump to 6. (RWARN): Bump to 0x8000000. (RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R) (RTYPE_R5900_ACC): New register types. (RTYPE_MASK): Include them. (R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New macros. (reg_names): Include them. (mips_parse_register_1): New function, split out from... (mips_parse_register): ...here. Add a channels_ptr parameter. Look for VU0 channel suffixes when nonnull. (reg_lookup): Update the call to mips_parse_register. (mips_parse_vu0_channels): New function. (OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types. (mips_operand_token): Add a "channels" field to the union. Extend the comment above "ch" to OT_DOUBLE_CHAR. (mips_parse_base_start): Match -- and ++. Handle channel suffixes. (mips_parse_argument_token): Handle channel suffixes here too. (validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX. Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits. Handle '#' formats. (md_begin): Register $vfN and $vfI registers. (operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (match_vu0_suffix_operand): New function. (match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (macro): Use "+7" rather than "E" for LDQ2 and STQ2. (mips_lookup_insn): New function. (mips_ip): Use it. Allow "+K" operands to be elided at the end of an instruction. Handle '#' sequences. gas/testsuite/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric coprocessor registers. * gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d, gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d, gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests. * gas/mips/mips.exp: Run them.	13 years ago
Richard Sandiford	3ccad066ac	include/opcode/ * mips.h (mips_pcrel_operand): Inherit from mips_int_operand. (mips_int_operand_min, mips_int_operand_max): New functions. (mips_decode_pcrel_operand): Use mips_decode_int_operand. opcodes/ * mips-formats.h (PCREL): Reorder parameters and update the definition to match new mips_pcrel_operand layout. (JUMP, JALX, BRANCH): Update accordingly. * mips16-opc.c (decode_mips16_operand): Likewise. gas/ * config/tc-mips.c (match_int_operand): Use mips_int_operand_min and mips_int_operand_max. (mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED): Delete. (mips16_immed_operand, mips16_immed_in_range_p): New functions. (mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand instead of mips16_immed_operand.	13 years ago
Richard Sandiford	df34fbcce8	opcodes/ * micromips-opc.c (WR_s): Delete.	13 years ago
Richard Sandiford	fc76e73056	include/opcode/ * mips.h (mips_decode_reg_operand): New function. (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL) (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4) (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI): New macros. (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D) (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T) (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S) (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z) (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D) (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD) (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG) (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP) (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP) (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other macros to cover the gaps. (INSN2_MOD_SP): Replace with... (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros. (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z) (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y) (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z) (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X): Delete. opcodes/ * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): New macros. (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete. (mips_builtin_opcodes): Use the new position-based read-write flags instead of field-based ones. Use UDI for "udi..." instructions. * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete. (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags. (WR_SP, RD_16): New macros. (RD_SP): Redefine as an INSN2_* flag. (MOD_SP): Redefine in terms of RD_SP and WR_SP. (mips16_opcodes): Use the new position-based read-write flags instead of field-based ones. Use RD_16 for "nop". Move RD_SP to pinfo2 field. * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj) (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D) (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete. (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP. (micromips_opcodes): Use the new position-based read-write flags instead of field-based ones. * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand. (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead of field-based flags. gas/ * config/tc-mips.c (MAX_OPERANDS): New macro. (mips_operand_array): New structure. (mips_operands, mips16_operands, micromips_operands): New arrays. (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map) (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map) (micromips_to_32_reg_q_map): Delete. (insn_operands, insn_opno, insn_extract_operand): New functions. (validate_mips_insn): Take a mips_operand_array as argument and use it to build up a list of operands. Extend to handle INSN_MACRO and MIPS16. (validate_mips16_insn): New function. (validate_micromips_insn): Take a mips_operand_array as argument. Handle INSN_MACRO. (md_begin): Initialize mips_operands, mips16_operands and micromips_operands. Call validate_mips_insn and validate_micromips_insn for macro instructions too. Call validate_mips16_insn for MIPS16 instructions. (insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask): New functions. (gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use them. Handle INSN_UDI. (get_append_method): Use gpr_read_mask.	13 years ago
Richard Sandiford	265459441c	include/opcode/ * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31) (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH) (MIPS16_INSN_COND_BRANCH): Delete. opcodes/ * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags. (WR_SP): Replace with... (MOD_SP): ...this. (mips16_opcodes): Update accordingly. * mips-dis.c (print_insn_mips16): Likewise. gas/ * config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same flags for MIPS16 and non-MIPS16 instructions. (gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block. (gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too. (gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling. (can_swap_branch_p, get_append_method): Use the same flags for MIPS16 and non-MIPS16 instructions. Fix formatting.	13 years ago
Richard Sandiford	a8d92fc6c3	opcodes/ * mips16-opc.c (mips16_opcodes): Reformat.	13 years ago

1 Commits (e13e2ba45fe23ec4e6d7335b0834290e61605d4d)