binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Sudakshina Das	dad0c3bfb5	[Arm, 3/3] Add Execution and Data Prediction instructions for AArch32 This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) This patch adds the Execution and Data Prediction Restriction instructions (that is, cfprctx, dvprxtc, cpprctx). These are all aliases to MCR and are disassembled as such. This instruction is retrospectively made optional for all versions of the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a new +predres for older versions of the architecture. * include/ChangeLog * 2018-10-05 Sudakshina Das <sudi.das@arm.com> * opcode/arm.h (ARM_EXT2_PREDRES): New. (ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default. * gas/ChangeLog * 2018-10-05 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (arm_ext_predres): New. (insns): Add new cfprctx, dvprctx and cpprctx instructions. (arm_extensions): Add "predres". * doc/c-arm.texi: Document the above. * testsuite/gas/arm/predres-bad.d: New test. * testsuite/gas/arm/predres-bad.l: New test. * testsuite/gas/arm/predres.s: New test. * testsuite/gas/arm/predres1.d: New test. * testsuite/gas/arm/predres2.d: New test.	8 years ago
Sudakshina Das	7fadb25d6f	[Arm, 2/3] Add instruction SB for AArch32 This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) This patch adds the instruction SB. This instruction is retrospectively made optional for all versions of the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a new "+sb" for older archtectures. * include/ChangeLog * 2018-10-05 Sudakshina Das <sudi.das@arm.com> * opcode/arm.h (ARM_EXT2_SB): New. (ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default. * opcodes/ChangeLog * 2018-10-05 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (arm_opcodes): Add sb. (thumb32_opcodes): Likewise. * gas/ChangeLog * 2018-10-05 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (arm_ext_sb): New. (insns): Add new sb instruction. (arm_extensions): Add "sb". * doc/c-arm.texi: Document the above. * testsuite/gas/arm/sb-bad.d: New test. * testsuite/gas/arm/sb-bad.l: New test. * testsuite/gas/arm/sb-thumb1.d: New test. * testsuite/gas/arm/sb-thumb2.d: New test. * testsuite/gas/arm/sb.s: New test. * testsuite/gas/arm/sb1.d: New test. * testsuite/gas/arm/sb2.d: New test.	8 years ago
Sudakshina Das	23f233a595	[Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32 This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) This is the first of the patch series and adds -march=armv8.5-a and other internal feature marcos needed for it. * gas/ChangeLog * 2018-10-05 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (arm_archs): New entry for armv8.5-a. (cpu_arch_ver): Likewise. * doc/c-arm.texi: Add documentation for the same. * testsuite/gas/arm/attr-march-armv8_5-a.d: New. * include/ChnageLog * 2018-10-05 Sudakshina Das <sudi.das@arm.com> * opcode/arm.h (ARM_EXT2_V8_5A): New. (ARM_AEXT2_V8_5A, ARM_ARCH_V8_5A): New.	8 years ago
Stafford Horne	c8e98e3692	or1k: Add the l.adrp insn and supporting relocations This patch adds the new instruction and relocation as per proposal: https://openrisc.io/proposals/ladrp This is to be added to the spec in an upcoming revision. The new instruction l.adrp loads the page offset of the current instruction offset by a 21-bit immediate shifted left 13-bits. This is meant to be used with a 13-bit lower bit page offset. This allows us to free up the got register r16. l.adrp r3, foo l.ori r4, r3, po(foo) l.lbz r5, po(foo)(r3) l.sb po(foo)(r3), r6 The relocations we add are: - BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry asm: plta() implemented using l.ardp, meaning no need for r16 (the GOT reg) - BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address asm: got() - BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General asm: tlsgd() Dynamic calculation - BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local asm: tlsldm() dynamic calculation - BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial asm: gottp() Executable calculation - BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp instructions) - BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation asm: po() i.e. mem loads, addi etc - BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation asm: po() i.e. mem stores, with split immediate - BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs asm: gotpo() - BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs asm: tlsgdpo() - BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs asm: tlsldmpo() - BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs asm: gottppo() bfd/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * bfd-in2.h: Regenerated. * elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26. (or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13, BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26. (elf_or1k_link_hash_table): Add field saw_plta. (or1k_final_link_relocate): Add value calculations for new relocations. (or1k_elf_relocate_section): Add section relocations for new relocations. (or1k_write_plt_entry): New function. (or1k_elf_finish_dynamic_sections): Add support for PLTA relocations using new l.adrp instruction. Cleanup PLT relocation code generation. * libbfd.h: Regenerated. * reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13, BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_TLS_IE_LO13. cpu/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k.opc (parse_disp26): Add support for plta() relocations. (parse_disp21): New function. (or1k_rclass): New enum. (or1k_rtype): New enum. (or1k_imm16_relocs): Define new PO and SPO relocation mappings. (parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations. (parse_imm16): Add support for the new 21bit and 13bit relocations. * or1korbis.cpu (f-disp26): Don't assume SI. (f-disp21): New pc-relative 21-bit 13 shifted to right. (insn-opcode): Add ADRP. (l-adrp): New instruction. gas/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_TLS_IE_LO13. * testsuite/gas/or1k/allinsn.s: Add test for l.adrp. * testsuite/gas/or1k/allinsn.d: Add test results for new instructions. * testsuite/gas/or1k/reloc-1.s: Add tests to generate R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13 relocations. * testsuite/gas/or1k/reloc-1.d: Add relocation results for tests. * testsuite/gas/or1k/reloc-2.s: Add negative tests for store to gotpo(). * testsuite/gas/or1k/reloc-2.l: Add expected error test results. ld/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * testsuite/ld-or1k/or1k.exp: Add test cases for plt generation. * testsuite/ld-or1k/plt1.dd: New file. * testsuite/ld-or1k/plt1.s: New file. * testsuite/ld-or1k/plt1.x.dd: New file. * testsuite/ld-or1k/plta1.dd: New file. * testsuite/ld-or1k/plta1.s: New file. * testsuite/ld-or1k/pltlib.s: New file. include/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26. opcodes/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k-asm.c: Regenerated. * or1k-desc.c: Regenerated. * or1k-desc.h: Regenerated. * or1k-dis.c: Regenerated. * or1k-ibld.c: Regenerated. * or1k-opc.c: Regenerated. * or1k-opc.h: Regenerated. * or1k-opinst.c: Regenerated.	8 years ago
Richard Henderson	1c4f3780f7	or1k: Add relocations for high-signed and low-stores This patch adds the following target relocations: - BFD_RELOC_HI16_S High 16-bit relocation, for used with signed asm: ha() lower. - BFD_RELOC_HI16_S_GOTOFF High 16-bit GOT offset relocation for local asm: gotoffha() symbols, for use with signed lower. - BFD_RELOC_OR1K_TLS_IE_AHI16 High 16-bit TLS relocation with initial asm: gottpoffha() executable calculation, for use with signed lower. - BFD_RELOC_OR1K_TLS_LE_AHI16 High 16-bit TLS relocation for local executable asm: tpoffha() variables, for use with signed lower. - BFD_RELOC_OR1K_SLO16 Split lower 16-bit relocation, used with asm: lo() OpenRISC store instructions. - BFD_RELOC_OR1K_GOTOFF_SLO16 Split lower 16-bit GOT offset relocation for asm: gotofflo() local symbols, used with OpenRISC store instructions. - BFD_RELOC_OR1K_TLS_LE_SLO16 Split lower 16-bit relocation for TLS local asm: tpofflo() executable variables, used with OpenRISC store instructions. bfd/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> Stafford Horne <shorne@gmail.com> * bfd-in2.h: Regenerated. * elf32-or1k.c (N_ONES): New macro. (or1k_elf_howto_table): Fix R_OR1K_PLT26 to complain on overflow. Add definitions for R_OR1K_TLS_TPOFF, R_OR1K_TLS_DTPOFF, R_OR1K_TLS_DTPMOD, R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16. (or1k_reloc_map): Add entries for BFD_RELOC_HI16_S, BFD_RELOC_LO16_GOTOFF, BFD_RELOC_HI16_GOTOFF, BFD_RELOC_HI16_S_GOTOFF, BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16, BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_LE_SLO16. (or1k_reloc_type_lookup): Change search loop to start ad index 0 and also check results before returning. (or1k_reloc_name_lookup): Simplify loop to use R_OR1K_max as index limit. (or1k_final_link_relocate): New function. (or1k_elf_relocate_section): Add support for new AHI and SLO relocations. Use or1k_final_link_relocate instead of generic _bfd_final_link_relocate. (or1k_elf_check_relocs): Add support for new AHI and SLO relocations. * reloc.c: Add new enums for BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16, BFD_RELOC_OR1K_TLS_LE_SLO16. Remove unused BFD_RELOC_OR1K_GOTOFF_HI16 and BFD_RELOC_OR1K_GOTOFF_LO16. * libbfd.h: Regenerated. cpu/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k.opc: Add RTYPE_ enum. (INVALID_STORE_RELOC): New string. (or1k_imm16_relocs): New array array. (parse_reloc): New static function that just does the parsing. (parse_imm16): New static function for generic parsing. (parse_simm16): Change to just call parse_imm16. (parse_simm16_split): New function. (parse_uimm16): Change to call parse_imm16. (parse_uimm16_split): New function. * or1korbis.cpu (simm16-split): Change to use new simm16_split. (uimm16-split): Change to use new uimm16_split. gas/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * testsuite/gas/or1k/allinsn.d (l_ha): Add result for ha() relocation. * testsuite/gas/or1k/allinsn.s (l_ha): Add test for ha() relocations. * testsuite/gas/or1k/allinsn.exp: Renamed to or1k.exp. * testsuite/gas/or1k/or1k.exp: Add reloc-2 list test. * testsuite/gas/or1k/reloc-1.d: New file. * testsuite/gas/or1k/reloc-1.s: New file. * testsuite/gas/or1k/reloc-2.l: New file. * testsuite/gas/or1k/reloc-2.s: New file. include/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16. ld/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * testsuite/ld-or1k/offsets1.d: New file. * testsuite/ld-or1k/offsets1.s: New file. * testsuite/ld-or1k/or1k.exp: New file. opcodes/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k-asm.c: Regenerate.	8 years ago
Tamar Christina	a68f4cd235	AArch64: Add SVE constraints verifier. This patch adds the verification rules for move prefix constraints. The Arm SVE instruction MOVPRFX introduces[1] constraints on the instruction at PC+4. Particularly the following constraints are handled by this patch * MOVPRFX must be followed by an instruction. * MOVPRFX can only be followed by non-layout altering directives. * MOVPRFX destination register MUST be used as the destination register in the instruction at PC+4, and is not allowed to be used in any other position other than destructive input. This includes registers that architecturally overlap. e.g. x1 should be treated as z1. * MOVPRFX must be followed by a restricted set of SVE instructions. * The size of the destination register of MOVPRFX must be equal to that of the operation at PC+4. * The predicate register and operation of MOVPRFX must match that of the instruction at PC+4 * The predicated instruction at PC+4 must use the merging predicate. * Architectural aliases and pseudo-instructions need to be supported as well. * MOVPRFX cannot be the last instruction in a sequence Any failure to adhere to any of these constrains will emit an assembly warning and a disassembly note. [1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a include/ * opcode/aarch64.h (aarch64_inst): Remove. (enum err_type): Add ERR_VFI. (aarch64_is_destructive_by_operands): New. (init_insn_sequence): New. (aarch64_decode_insn): Remove param name. opcodes/ * aarch64-opc.c (init_insn_block): New. (verify_constraints, aarch64_is_destructive_by_operands): New. * aarch64-opc.h (verify_constraints): New. gas/ * config/tc-aarch64.c (output_operand_error_report): Order warnings.	8 years ago
Tamar Christina	755b748fd9	AArch64: Refactor verifiers to make more general. The current verifiers only take an instruction description and encoded value as arguments. This was enough when the verifiers only needed to do simple checking but it's insufficient for the purposes of validating instruction sequences. This patch adds the required arguments and also a flag to allow a verifier to distinguish between whether it's being run during encoding or decoding. It also allows for errors and warnings to be returned by a verifier instead of a simple pass/fail. include/ * opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take more arguments. opcodes/ * aarch64-dis.c (aarch64_opcode_decode): Update verifier call. * aarch64-opc.c (verify_ldpsw): Update arguments.	8 years ago
Tamar Christina	1d4823943d	AArch64: Refactor err_type. Previously the ERR_ values were defined as different constants, to make this a bit more type safe and so they can be more easily re-used I'm changing them into an actual enum and updating any usages. include/ * opcode/aarch64.h (enum err_type): New. (aarch64_decode_insn): Use it. opcodes/ * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove. (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.	8 years ago
Tamar Christina	7e84b55d8f	AArch64: Wire through instr_sequence This patch introduces aarch64_instr_sequence which is a structure similar to IT blocks on Arm in order to track instructions that introduce a constraint or dependency on instruction 1..N positions away from the instruction that opened the block. The struct is also wired through to the locations that require it. gas/ * config/tc-aarch64.c (now_instr_sequence): (insn_sequence, now_instr_sequence): New. (output_operand_error_record, do_encode): Add insn_sequence. (md_assemble): Update insn_sequence. (try_to_encode_as_unscaled_ldst, fix_mov_imm_insn, fix_insn): Pass insn_sequence. config/tc-aarch64.h (struct aarch64_segment_info_type): Add insn_sequence. include/ * opcode/aarch64.h (struct aarch64_instr_sequence): New. (aarch64_opcode_encode): Use it. opcodes/ * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence. * aarch64-dis.c (insn_sequence): New.	8 years ago
Tamar Christina	eae424aef0	AArch64: Mark sve instructions that require MOVPRFX constraints This patch series is to allow certain instructions such as the SVE MOVPRFX instruction to apply a constraint/dependency on the instruction at PC+4. This patch starts this off by marking which instructions impose the constraint and which instructions must adhere to the constraint. This is done in a generic way by extending the verifiers. * The constraint F_SCAN indicates that an instruction opens a sequence and imposes a constraint on an instructions following it. The length of the sequence depends on the instruction itself and it handled in the verifier code. * The C_SCAN_MOVPRFX flag is used to indicate which constrain the instruction is checked against. An instruction with both F_SCAN and C_SCAN_MOVPRFX starts a block for the C_SCAN_MOVPRFX instruction, and one with only C_SCAN_MOVPRFX must adhere to a previous block constraint is applicable. The SVE instructions in this list have been marked according to the SVE specification[1]. [1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a include/ * opcode/aarch64.h (struct aarch64_opcode): Add constraints, extend flags field size. (F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New. opcodes/ * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN, _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN, V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize constraints. (_SVE_INSNC): New. (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize constraints. (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and F_SCAN flags. (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf, sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech, sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb, sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd, uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub, uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add C_SCAN_MOVPRFX and C_MAX_ELEM constraints.	8 years ago
John Darrington	007d2fe43e	Make print_insn_s12z public. Gdb can use this function in its stack unwinder. * include/dis-asm.h (print_insn_s12z): Add declaration.	8 years ago
Palmer Dabbelt	64a336ac13	RISC-V: Add fence.tso instruction The RISC-V memory model has been ratified, and it includes an additional fence: "fence.tso". This pseudo instruction extends one of the previously reserved full fence patterns to be less restrictive, and therefor will execute correctly on all existing microarchitectures. Thus there is no reason to allow this instruction to be disabled (or unconverted to a full fence), so it's just unconditionally allowed. I've added a test case for GAS to check that "fence.tso" correctly assembles on rv32i-based targets. I checked to see that "fence.tso" appears in "gas.log", but that's the only testing I've done. gas/ChangeLog 2018-10-02 Palmer Dabbelt <palmer@sifive.com> * testsuite/gas/riscv/fence-tso.d: New file. * testsuite/gas/riscv/fence-tso.s: Likewise. include/ChangeLog 2018-10-02 Palmer Dabbelt <palmer@sifive.com> * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define. (MASK_FENCE_TSO): Likewise. opcodes/ChangeLog 2018-10-02 Palmer Dabbelt <palmer@sifive.com> * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.	8 years ago
Cupertino Miranda	eb528ad18b	[ARC] Entries to Changelog for previous commits.	8 years ago
H.J. Lu	95475e5d6b	ELF: Don't include zero size sections at start of PT_NOTE segment We shouldn't include zero size sections at start of PT_NOTE segment, similar to PT_DYNAMIC segment. PR binutils/23694 * include/elf/internal.h (ELF_SECTION_IN_SEGMENT_1): Don't include zero size sections at start of PT_NOTE segment.	8 years ago
Nick Clifton	fbaf61ad52	Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream! We have not only removed all unsupported and obsolete code, but also supported lost of new features, including better link-time relaxations and TLS implementations. Besides, the files generated by the newly assembler and linker usually get higher performance and more optimized code size. ld * emultempl/nds32elf.em (hyper_relax): New variable. (nds32_elf_create_output_section_statements): the parameters of bfd_elf32_nds32_set_target_option (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Add new option --mhyper-relax. * emultempl/nds32elf.em (nds32_elf_after_open): Updated. * emultempl/nds32elf.em (tls_desc_trampoline): New variable. * (nds32_elf_create_output_section_statements): Updated. * (nds32_elf_after_parse): Disable relaxations when PIC is enable. * (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Add new option --m[no-]tlsdesc-trampoline. include * elf/nds32.h: Remove the unused target features. * dis-asm.h (disassemble_init_nds32): Declared. * elf/nds32.h (E_NDS32_NULL): Removed. (E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New. * opcode/nds32.h: Ident. (N32_SUB6, INSN_LW): New macros. (enum n32_opcodes): Updated. * elf/nds32.h: Doc fixes. * elf/nds32.h: Add R_NDS32_LSI. * elf/nds32.h: Add new relocations for TLS. gas * config/tc-nds32.c: Remove the unused target features. (nds32_relax_relocs, md_pseudo_table, nds32_elf_record_fixup_exp, nds32_set_elf_flags_by_insn, nds32_insert_relax_entry, nds32_apply_fix): Likewise. (nds32_no_ex9_begin): Removed. * config/tc-nds32.c (add_mapping_symbol_for_align, make_mapping_symbol, add_mapping_symbol): New functions. * config/tc-nds32.h (enum mstate): New. (nds32_segment_info_type): Likewise. * configure.ac (--enable-dsp-ext, --enable-zol-ext): New options. * config.in: Regenerated. * configure: Regenerated. * config/tc-nds32.c (nds32_dx_regs): Set the value according to the configuration. (nds32_perf_ext, nds32_perf_ext2, nds32_string_ext, nds32_audio_ext): Likewise. (nds32_dsp_ext): New variable. Set the value according to the configuration. (nds32_zol_ext): Likewise. (asm_desc, nds32_pseudo_opcode_table): Make them static. (nds32_set_elf_flags_by_insn): Updated. (nds32_check_insn_available): Updated. (nds32_str_tolower): New function. * config/tc-nds32.c (relax_table): Updated. (md_begin): Updated. (md_assemble): Use XNEW macro to allocate space for `insn.info', and then remember to free it. (md_section_align): Cast (-1) to ValueT. (nds32_get_align): Cast (~0U) to addressT. (nds32_relax_branch_instructions): Updated. (md_convert_frag): Add new local variable `final_r_type'. (invalid_prev_frag): Add new bfd_boolean parameter `relax'. All callers changed. * config/tc-nds32.c (struct nds32_relocs_pattern): Add `insn' field. (struct nds32_hint_map): Add `option_list' field. (struct suffix_name, suffix_table): Remove the unused `pic' field. (do_pseudo_b, do_pseudo_bal): Remove the suffix checking. (do_pseudo_la_internal, do_pseudo_pushpopm): Indent. (relax_hint_bias, relax_hint_id_current): New static variables. (reset_bias, relax_hint_begin): New variables. (nds_itoa): New function. (CLEAN_REG, GET_OPCODE): New macros. (struct relax_hint_id): New. (nds32_relax_hint): For .relax_hint directive, we can use `begin' and `end' to mark the relax pattern without giving exactly id number. (nds32_elf_append_relax_relocs): Handle the case that the .relax_hint directives are attached to pseudo instruction. (nds32_elf_save_pseudo_pattern): Change the second parameter from instruction's opcode to byte code. (nds32_elf_build_relax_relation): Add new bfd_boolean parameter `pseudo_hint'. (nds32_lookup_pseudo_opcode): Fix the overflow issue. (enum nds32_insn_type): Add N32_RELAX_ALU1 and N32_RELAX_16BIT. (nds32_elf_record_fixup_exp, relax_ls_table, hint_map, nds32_find_reloc_table, nds32_match_hint_insn, nds32_parse_name): Updated. * config/tc-nds32.h (MAX_RELAX_NUM): Extend it to 6. (enum nds32_relax_hint_type): Merge NDS32_RELAX_HINT_LA and NDS32_RELAX_HINT_LS into NDS32_RELAX_HINT_LALS. Add NDS32_RELAX_HINT_LA_PLT, NDS32_RELAX_HINT_LA_GOT and NDS32_RELAX_HINT_LA_GOTOFF. * config/tc-nds32.h (relax_ls_table): Add floating load/store to gp relax pattern. (hint_map, nds32_find_reloc_table): Likewise. * configure.ac: Define NDS32_LINUX_TOOLCHAIN. * configure: Regenerated. * config.in: Regenerated. * config/tc-nds32.h (enum nds32_ramp): Updated. (enum nds32_relax_hint_type): Likewise. * config/tc-nds32.c: Include "errno.h" and "limits.h". (relax_ls_table): Add TLS relax patterns. (nds32_elf_append_relax_relocs): Attach BFD_RELOC_NDS32_GROUP on each instructions of TLS patterns. (nds32_elf_record_fixup_exp): Updated. (nds32_apply_fix): Likewise. (suffix_table): Add TLSDESC suffix. binutils* testsuite/binutils-all/objcopy.exp: Set the unsupported reloc number from 215 to 255 for NDS32. bfd * elf32-nds32.c (nds32_elf_relax_loadstore): Remove the unused target features. (bfd_elf32_nds32_set_target_option): Remove the unused parameters. (nds32_elf_relax_piclo12, nds32_elf_relax_letlslo12, nds32_elf_relax_letlsadd, nds32_elf_relax_letlsls, nds32_elf_relax_pltgot_suff, nds32_elf_relax_got_suff nds32_elf_relax_gotoff_suff, calculate_plt_memory_address, calculate_plt_offset, calculate_got_memory_address, nds32_elf_check_dup_relocs): Removed. All callers changed. * elf32-nds32.h: Remove the unused macros and defines. (elf_nds32_link_hash_table): Remove the unused variable. (bfd_elf32_nds32_set_target_option): Update prototype. (nds32_elf_ex9_init): Removed. * elf32-nds32.c (nds32_convert_32_to_16): Updated. * elf32-nds32.c (HOWTO2, HOWTO3): Define new HOWTO macros to initialize array nds32_elf_howto_table in any order without lots of EMPTY_HOWTO. (nds32_reloc_map): Updated. * reloc.c: Add BFD_RELOC_NDS32_LSI. * bfd-in2.h: Regenerated. * bfd/libbfd.h: Regenerated. * elf32-nds32.c (nds32_elf_relax_howto_table): Add R_NDS32_LSI. (nds32_reloc_map): Likewise. (nds32_elf_relax_flsi): New function. (nds32_elf_relax_section): Support floating load/store relaxation. * elf32-nds32.c (NDS32_GUARD_SEC_P, elf32_nds32_local_gp_offset): New macro. (struct elf_nds32_link_hash_entry): New `offset_to_gp' field. (struct elf_nds32_obj_tdata): New `offset_to_gp' and `hdr_size' fields. (elf32_nds32_allocate_local_sym_info, nds32_elf_relax_guard, nds32_elf_is_target_special_symbol, nds32_elf_maybe_function_sym): New functions. (nds32_info_to_howto_rel): Add BFD_ASSERT. (bfd_elf32_bfd_reloc_type_table_lookup, nds32_elf_link_hash_newfunc, nds32_elf_link_hash_table_create, nds32_elf_relocate_section, nds32_elf_relax_loadstore, nds32_elf_relax_lo12, nds32_relax_adjust_label, bfd_elf32_nds32_set_target_option, nds32_fag_mark_relax): Updated. (nds32_elf_final_sda_base): Improve it to find the better gp value. (insert_nds32_elf_blank): Must consider `len' when inserting blanks. * elf32-nds32.h (bfd_elf32_nds32_set_target_option): Update prototype. (struct elf_nds32_link_hash_table): Add new variable `hyper_relax'. * elf32-nds32.c (elf32_nds32_allocate_dynrelocs): New function. (create_got_section): Likewise. (allocate_dynrelocs, nds32_elf_size_dynamic_sections, nds32_elf_relocate_section, nds32_elf_finish_dynamic_symbol): Updated. (nds32_elf_check_relocs): Fix the issue that the shared library may has TEXTREL entry in the dynamic section. (nds32_elf_create_dynamic_sections): Enable to call readonly_dynrelocs since the TEXTREL issue is fixed in the nds32_elf_check_relocs. (nds32_elf_finish_dynamic_sections): Update and add DT_RELASZ dynamic entry. (calculate_offset): Remove the unused parameter `pic_ext_target' and related codes. All callers changed. (elf_backend_dtrel_excludes_plt): Disable it temporarily since it will cause some errors for our test cases. * elf32-nds32.c (nds32_elf_merge_private_bfd_data): Allow to link the generic object. * reloc.c: Add TLS relocations. * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * elf32-nds32.h (struct section_id_list_t): New. (elf32_nds32_lookup_section_id, elf32_nds32_check_relax_group, elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New prototypes. (elf32_nds32_compute_jump_table_size, elf32_nds32_local_tlsdesc_gotent): New macro. (nds32_insertion_sort, bfd_elf32_nds32_set_target_option, elf_nds32_link_hash_table): Updated. * elf32-nds32.c (enum elf_nds32_tls_type): New. (struct elf32_nds32_relax_group_t, struct relax_group_list_t): New. (elf32_nds32_add_dynreloc, patch_tls_desc_to_ie, get_tls_type, fls, ones32, list_insert, list_insert_sibling, dump_chain, elf32_nds32_check_relax_group, elf32_nds32_lookup_section_id, elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New functions. (elf_nds32_obj_tdata): Add new fields. (elf32_nds32_relax_group_ptr, nds32_elf_local_tlsdesc_gotent): New macros. (nds32_elf_howto_table): Add TLS relocations. (nds32_reloc_map): Likewise. (nds32_elf_copy_indirect_symbol, nds32_elf_size_dynamic_sections, nds32_elf_finish_dynamic_symbol, elf32_nds32_allocate_local_sym_info, nds32_elf_relocate_section, bfd_elf32_nds32_set_target_option, nds32_elf_check_relocs, allocate_dynrelocs): Updated. (nds32_elf_relax_section): Call nds32_elf_unify_tls_model. (dtpoff_base): Rename it to `gottpof' and then update it. opcodes * nds32-asm.c (operand_fields): Remove the unused fields. (nds32_opcodes): Remove the unused instructions. * nds32-dis.c (nds32_ex9_info): Removed. (nds32_parse_opcode): Updated. (print_insn_nds32): Likewise. * nds32-asm.c (config.h, stdlib.h, string.h): New includes. (LEX_SET_FIELD, LEX_GET_FIELD): Update defines. (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table, build_opcode_hash_table): New functions. (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table, nds32_opcode_table): New. (hw_ktabs): Declare it to a pointer rather than an array. (build_hash_table): Removed. * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT, SYN_ROPT and upadte HW_GPR and HW_INT. * nds32-dis.c (keywords): Remove const. (match_field): New function. (nds32_parse_opcode): Updated. * disassemble.c (disassemble_init_for_target): Add disassemble_init_nds32. * nds32-dis.c (eum map_type): New. (nds32_private_data): Likewise. (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid, nds32_add_opcode_hash_table, disassemble_init_nds32): New functions. (print_insn_nds32): Updated. * nds32-asm.c (parse_aext_reg): Add new parameter. (parse_re, parse_re2, parse_aext_reg): Only reduced registers are allowed to use. All callers changed. * nds32-asm.c (keyword_usr, keyword_sr): Updated. (operand_fields): Add new fields. (nds32_opcodes): Add new instructions. (keyword_aridxi_mx): New keyword. * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX and NASM_ATTR_ZOL. (ALU2_1, ALU2_2, ALU2_3): New macros. * nds32-dis.c (nds32_filter_unknown_insn): Updated.	8 years ago
Rainer Orth	3d282ac370	Handle missing Solaris auxv entries Currently, three tests FAIL on Solaris 11.4+ (amd64-pc-solaris2.11 and sparcv9-sun-solaris2.11): info auxv [...] 2009 AT_SUN_HWCAP Machine-dependent CPU capability hints 0x3f5ff7 2023 ??? 0x0 0 AT_NULL End of vector 0x0 (gdb) WARNING: Unrecognized tag value: 2023 ??? 0x0 FAIL: gdb.base/auxv.exp: info auxv on live process info auxv 4294969310 ??? 0x7fffbfffe410 9225589753816 ??? 0x7fffbfffe45c [...] WARNING: Unrecognized tag value: 4294969310 ??? 0x7fffbfffe410 WARNING: Unrecognized tag value: 9225589753816 ??? 0x7fffbfffe45c WARNING: Unrecognized tag value: 140733193388037 ??? 0x6 [...] 2009 AT_SUN_HWCAP Machine-dependent CPU capability hints 0x3f5ff7 2023 ??? 0x0 0 AT_NULL End of vector 0x0 (gdb) WARNING: Unrecognized tag value: 2023 ??? 0x0 UNRESOLVED: gdb.base/auxv.exp: info auxv on native core dump info auxv [...] 2009 AT_SUN_HWCAP Machine-dependent CPU capability hints 0x3f5ff7 2023 ??? 0x0 0 AT_NULL End of vector 0x0 (gdb) WARNING: Unrecognized tag value: 2023 ??? 0x0 FAIL: gdb.base/auxv.exp: info auxv on gcore-created dump The following patch fixes this by introducing the missing AT_SUN_* values from Solaris 11.4+ <sys/auxv.h>. This lets the live and gcore-created dump tests PASS. I don't know yet what's the reason for those weird 'Unrecognized tag value' warnings with native core dumps is; elfdump -n certainly doesn't show them. However, native core dumps still need quite some work (mostly in bfd) in this and other areas. Tested on amd64-pc-solaris2.11. gdb: * auxv.c (default_print_auxv_entry): Reflect AT_SUN_CAP_HW1 renaming. Handle AT_SUN_EMULATOR, AT_SUN_BRANDNAME, AT_SUN_BRAND_AUX1, AT_SUN_BRAND_AUX2, AT_SUN_BRAND_AUX3, AT_SUN_CAP_HW2. include: * elf/common.h (AT_SUN_HWCAP): Rename to ... (AT_SUN_CAP_HW1): ... this. Retain old name for backward compatibility. (AT_SUN_EMULATOR, AT_SUN_BRANDNAME, AT_SUN_BRAND_AUX1) (AT_SUN_BRAND_AUX2, AT_SUN_BRAND_AUX3, AT_SUN_CAP_HW2): Define.	8 years ago
Simon Marchi	af39b1c216	Disable -Wformat-nonliteral in parts of printcmd.c commit `3322c5d9a1` ("Remove unneeded explicit .o targets") broke the build with clang, because -Wno-format-nonliteral was in fact needed. This patch fixes the problem by introducing DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL and using it in printcmd.c. This seems preferable to reverting the patch because now the warning suppression is more targeted. gdb/ChangeLog 2018-09-05 Simon Marchi <simon.marchi@ericsson.com> * printcmd.c (printf_c_string): Use DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL. (printf_wide_c_string, printf_pointer, ui_printf): Likewise. include/ChangeLog 2018-09-05 Simon Marchi <simon.marchi@ericsson.com> * diagnostics.h (DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL): New macro.	8 years ago
Alan Modra	4a9699735b	PowerPC64 higher REL16 relocations There are occasions where someone might want to build a 64-bit pc-relative offset from 16-bit pieces. This adds the necessary REL16 relocs corresponding to existing ADDR16 relocs that can be used to build 64-bit absolute values. include/ * elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA), (R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA), (R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define. (R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value. bfd/ * reloc.c (BFD_RELOC_PPC64_REL16_HIGH, BFD_RELOC_PPC64_REL16_HIGHA), (BFD_RELOC_PPC64_REL16_HIGHER, BFD_RELOC_PPC64_REL16_HIGHERA), (BFD_RELOC_PPC64_REL16_HIGHEST, BFD_RELOC_PPC64_REL16_HIGHESTA): Define. * elf64-ppc.c (ppc64_elf_howto_raw): Add new REL16 howtos. (ppc64_elf_reloc_type_lookup): Translate new REL16 relocs. (ppc64_elf_check_relocs, ppc64_elf_relocate_section): Handle them. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Allow ADDR16 HIGH, HIGHA, HIGHER, HIGHERA, HIGHEST, and HIGHESTA relocs. Group 16-bit relocs. * config/tc-ppc.c (md_apply_fix): Translate those ADDR16 relocs to REL16 when pcrel. Sort relocs.	8 years ago
Jim Wilson	43135d3b15	RISC-V: Allow instruction require more than one extension 2018-08-29 Kito Cheng <kito@andestech.com> gas/ * config/tc-riscv.c (riscv_subset_supports): New argument: xlen_required. (riscv_multi_subset_supports): New function, able to check more than one extension. (riscv_ip): Use riscv_multi_subset_supports instead of riscv_subset_supports. (riscv_set_arch): Update call-site for riscv_subset_supports. (riscv_after_parse_args): Likewise. include/ opcode/riscv.h (MAX_SUBSET_NUM): New. (riscv_opcode): Add xlen_requirement field and change type of subset. opcodes/ riscv-dis.c (riscv_disassemble_insn): Check XLEN by riscv_opcode.xlen_requirement. * riscv-opc.c (riscv_opcodes): Update for struct change.	8 years ago
Chenghua Xu	9108bc33b1	[MIPS] Add Loongson 2K1000 proccessor support. bfd/ * archures.c (bfd_architecture): New machine bfd_mach_mips_gs264e. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_GS264E. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Map bfd_mach_mips_gs264e to bfd_mach_mips_gs464e extension. binutils/ * NEWS: Mention Loongson 2K1000 proccessor support. * readelf.c (get_machine_flags): Handle gs264e. elfcpp/ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E. (mips_cpu_info_table): Add gs264e descriptors. * doc/as.texi (march table): Add gs264e. include/ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E. * opcode/mips.h (CPU_XXX): New CPU_GS264E. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination gs264e and gs464e. opcodes/ * mips-dis.c (mips_arch_choices): Add gs264e descriptors.	8 years ago
Chenghua Xu	bd782c07b9	[MIPS] Add Loongson 3A2000/3A3000 proccessor support. bfd/ * archures.c (bfd_architecture): New machine bfd_mach_mips_gs464e. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_GS464E. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Map bfd_mach_mips_gs464e to bfd_mach_mips_gs464 extension. binutils/ * NEWS: Mention Loongson 3A2000/3A3000 proccessor support. * readelf.c (get_machine_flags): Handle gs464e. elfcpp/ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E. (mips_cpu_info_table): Add gs464e descriptors. * doc/as.texi (march table): Add gs464e. include/ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E. * opcode/mips.h (CPU_XXX): New CPU_GS464E. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination gs464e and gs464. opcodes/ * mips-dis.c (mips_arch_choices): Add gs464e descriptors.	8 years ago
Chenghua Xu	ac8cb70f36	[MIPS] Add Loongson 3A1000 proccessor support. bfd/ * archures.c (bfd_architecture): Rename bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Likewise. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Likewise. (bfd_mips_isa_ext_mach): Likewise. (bfd_mips_isa_ext): Likewise. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. binutils/ * NEWS: Mention Loongson 3A1000 proccessor support. * readelf.c (get_machine_flags): Rename loongson-3a to gs464. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. elfcpp/ * mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename CPU_LOONGSON_3A to CPU_GS464. (mips_cpu_info_table): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * doc/as.texi (march table): Rename loongson3a to gs464. * testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension" flag to None. gold/ * mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach): Rename loongson3a to gs464. (mips_isa_ext_mach, mips_isa_ext): Delete loongson3a. (infer_abiflags): Use ases instead of isa_ext for infer ABI flags. (elf_mips_mach_name): Rename loongson3a to gs464. include/ * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A. * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A. (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464. * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a to gs464. opcodes/ * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * mips-opc.c (mips_opcodes): Change Comments.	8 years ago
Chenghua Xu	a693765e23	[MIPS/GAS] Add Loongson EXT2 Instructions support. bfd/ * elfxx-mips.c (print_mips_ases): Add Loongson EXT2 extension. binutils/ * readelf.c (print_mips_ases): Add Loongson EXT2 extension. gas/ * NEWS: Mention Loongson EXTensions R2 (EXT2) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT2 and OPTION_NO_LOONGSON_EXT2. (md_longopts): Likewise. (mips_ases): Define availability for EXT. (mips_convert_ase_flags): Map ASE_LOONGSON_EXT2 to AFL_ASE_LOONGSON_EXT2. (md_show_usage): Add help for -mloongson-ext2 and -mno-loongson-ext2. * doc/as.texi: Document -mloongson-ext2, -mno-loongson-ext2. * doc/c-mips.texi: Document -mloongson-ext2, -mno-loongson-ext2, .set loongson-ext2 and .set noloongson-ext2. * testsuite/gas/mips/loongson-ext2.d: New test. * testsuite/gas/mips/loongson-ext2.s: New test. * testsuite/gas/mips/mips.exp: Run loongson-ext2 test. include/ * elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2. * opcode/mips.h (ASE_LOONGSON_EXT2): New macro. opcodes/ * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext option. (print_mips_disassembler_options): Document -M loongson-ext. * mips-opc.c (LEXT2): New macro. (mips_opcodes): Add cto, ctz, dcto, dctz instructions.	8 years ago
Chenghua Xu	bdc6c06e3b	[MIPS/GAS] Split Loongson EXT Instructions from loongson3a. bfd/ * elfxx-mips.c (infer_mips_abiflags): Use ases instead of isa_ext for infer ABI flags. (print_mips_ases): Add Loongson EXT extension. binutils/ * readelf.c (print_mips_ases): Add Loongson EXT extension. elfcpp/ * mips.h (AFL_ASE_LOONGSON_EXT): New enum. gas/ * NEWS: Mention Loongson EXTensions (EXT) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and OPTION_NO_LOONGSON_EXT. (md_longopts): Likewise. (mips_ases): Define availability for EXT. (mips_convert_ase_flags): Map ASE_LOONGSON_EXT to AFL_ASE_LOONGSON_EXT. (mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a. (md_show_usage): Add help for -mloongson-ext and -mno-loongson-ext. * doc/as.texi: Document -mloongson-ext, -mno-loongson-ext. * doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext, .set loongson-ext and .set noloongson-ext. * testsuite/gas/mips/loongson-mmi.d: Add ASE flag. include/ * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT. * opcode/mips.h (ASE_LOONGSON_EXT): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add EXT to loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-ext option. (print_mips_disassembler_options): Document -M loongson-ext. * mips-opc.c (IL3A): Delete. * mips-opc.c (LEXT): New macro. (mips_opcodes): Replace IL2F\|IL3A marking with LEXT for EXT instructions.	8 years ago
Chenghua Xu	716c08de28	[MIPS/GAS] Split Loongson CAM Instructions from loongson3a bfd/ * elfxx-mips.c (print_mips_ases): Add CAM extension. binutils/ * readelf.c (print_mips_ases): Add CAM extension. gas/ * NEWS: Mention Loongson Content Address Memory (CAM) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and OPTION_NO_LOONGSON_CAM. (md_longopts): Likewise. (mips_ases): Define availability for CAM. (mips_convert_ase_flags): Map ASE_LOONGSON_CAM to AFL_ASE_LOONGSON_CAM. (mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a. (md_show_usage): Add help for -mloongson-cam and -mno-loongson-cam. * doc/as.texi: Document -mloongson-cam, -mno-loongson-cam. * doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam, .set loongson-cam and .set noloongson-cam. * testsuite/gas/mips/loongson-3a-2.d: Move cam test to ... * testsuite/gas/mips/loongson-cam.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-3a-2.s: Move cam test to ... * testsuite/gas/mips/loongson-cam.s: Here. * testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag. * testsuite/gas/mips/mips.exp: Run loongson-cam test. include/ * elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM. * opcode/mips.h (ASE_LOONGSON_CAM): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add CAM to loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-cam option. (print_mips_disassembler_options): Document -M loongson-cam. * mips-opc.c (LCAM): New macro. (mips_opcodes): Replace IL2F\|IL3A marking with LCAM for CAM instructions.	8 years ago
H.J. Lu	a9eafb08b3	x86: Update GNU_PROPERTY_X86_XXX macros This patch updates GNU_PROPERTY_X86_XXX macros: 1. GNU_PROPERTY_X86_UINT32_AND_XXX: A 4-byte unsigned integer property. A bit is set if it is set in all relocatable inputs: #define GNU_PROPERTY_X86_UINT32_AND_LO 0xc0000002 #define GNU_PROPERTY_X86_UINT32_AND_HI 0xc0007fff 2. GNU_PROPERTY_X86_UINT32_OR_XXX: A 4-byte unsigned integer property. A bit is set if it is set in any relocatable inputs: #define GNU_PROPERTY_X86_UINT32_OR_LO 0xc0008000 #define GNU_PROPERTY_X86_UINT32_OR_HI 0xc000ffff 3. GNU_PROPERTY_X86_UINT32_OR_AND_XXX: A 4-byte unsigned integer property. A bit is set if it is set in any relocatable inputs and the property is present in all relocatable inputs: #define GNU_PROPERTY_X86_UINT32_OR_AND_LO 0xc0010000 #define GNU_PROPERTY_X86_UINT32_OR_AND_HI 0xc0017fff 4. GNU_PROPERTY_X86_FEATURE_2_NEEDED, GNU_PROPERTY_X86_FEATURE_2_USED and GNU_PROPERTY_X86_FEATURE_2_XXX bits. GNU_PROPERTY_X86_FEATURE_1_AND is unchanged. GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED are updated to better support targeted processors since GNU_PROPERTY_X86_ISA_1_?86 aren't isn't very useful. A new set of GNU_PROPERTY_X86_ISA_1_XXX bits are defined. The previous GNU_PROPERTY_X86_ISA_1_XXX macros are deprecated and renamed to GNU_PROPERTY_X86_COMPAT_ISA_1_XXX. bfd/ * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Handle X86_COMPAT_ISA_1_USED, X86_COMPAT_ISA_1_NEEDED, X86_UINT32_AND_LO, X86_UINT32_AND_HI, X86_UINT32_OR_LO, X86_UINT32_OR_HI, X86_UINT32_OR_AND_LO and X86_UINT32_OR_AND_HI instead of X86_ISA_1_USED, X86_ISA_1_NEEDED and X86_FEATURE_1_AND. (_bfd_x86_elf_merge_gnu_properties): Likewise. (_bfd_x86_elf_link_setup_gnu_properties): Add X86_FEATURE_2_NEEDED instead of X86_ISA_1_NEEDED. (_bfd_x86_elf_link_fixup_gnu_properties): Handle X86_COMPAT_ISA_1_USED, X86_COMPAT_ISA_1_NEEDED, X86_UINT32_AND_LO, X86_UINT32_AND_HI, X86_UINT32_OR_LO, X86_UINT32_OR_HI, X86_UINT32_OR_AND_LO and X86_UINT32_OR_AND_HI instead of X86_ISA_1_USED, X86_ISA_1_NEEDED and X86_FEATURE_1_AND. binutils/ * readelf.c (decode_x86_compat_isa): New function. (decode_x86_feature_2): Likewise. (decode_x86_isa): Updated for new X86_ISA_1_XXX bits. (decode_x86_feature): Renamed to ... (decode_x86_feature_1): This. Remove the type argument. (print_gnu_property_note): Handle X86_COMPAT_ISA_1_USED, X86_COMPAT_ISA_1_NEEDED, X86_UINT32_AND_LO, X86_UINT32_AND_HI, X86_UINT32_OR_LO, X86_UINT32_OR_HI, X86_UINT32_OR_AND_LO and X86_UINT32_OR_AND_HI instead of X86_ISA_1_USED, X86_ISA_1_NEEDED and X86_FEATURE_1_AND. * testsuite/binutils-all/i386/pr21231b.s: Updated to the current GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED values. * testsuite/binutils-all/x86-64/pr21231b.s: Likewise. * testsuite/binutils-all/x86-64/pr23494a.s: Likewise. * testsuite/binutils-all/x86-64/pr23494b.s: Likewise. * testsuite/binutils-all/x86-64/pr23494c.s: Likewise. * testsuite/binutils-all/i386/pr21231b.d: Updated. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e.d: Likewise. include/ * elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ... (GNU_PROPERTY_X86_COMPAT_ISA_1_USED): This. (GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ... (GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED): This. (GNU_PROPERTY_X86_ISA_1_XXX): Renamed to ... (GNU_PROPERTY_X86_COMPAT_ISA_1_XXX): This. (GNU_PROPERTY_X86_UINT32_AND_LO): New. (GNU_PROPERTY_X86_UINT32_AND_HI): Likewise. (GNU_PROPERTY_X86_UINT32_OR_LO): Likewise. (GNU_PROPERTY_X86_UINT32_OR_HI): Likewise. (GNU_PROPERTY_X86_UINT32_OR_AND_LO): Likewise. (GNU_PROPERTY_X86_UINT32_OR_AND_HI): Likewise. (GNU_PROPERTY_X86_ISA_1_CMOV): Likewise. (GNU_PROPERTY_X86_ISA_1_SSE): Likewise. (GNU_PROPERTY_X86_ISA_1_SSE2): Likewise. (GNU_PROPERTY_X86_ISA_1_SSE3): Likewise. (GNU_PROPERTY_X86_ISA_1_SSSE3): Likewise. (GNU_PROPERTY_X86_ISA_1_SSE4_1): Likewise. (GNU_PROPERTY_X86_ISA_1_SSE4_2): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX2): Likewise. (GNU_PROPERTY_X86_ISA_1_FMA): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512F): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512CD): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512ER): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512PF): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512VL): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512DQ): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512BW): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_BITALG): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_IFMA): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_VBMI): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_VNNI): Likewise. (GNU_PROPERTY_X86_FEATURE_2_X86): Likewise. (GNU_PROPERTY_X86_FEATURE_2_X87): Likewise. (GNU_PROPERTY_X86_FEATURE_2_MMX): Likewise. (GNU_PROPERTY_X86_FEATURE_2_XMM): Likewise. (GNU_PROPERTY_X86_FEATURE_2_YMM): Likewise. (GNU_PROPERTY_X86_FEATURE_2_ZMM): Likewise. (GNU_PROPERTY_X86_FEATURE_2_FXSR): Likewise. (GNU_PROPERTY_X86_FEATURE_2_XSAVE): Likewise. (GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT): Likewise. (GNU_PROPERTY_X86_FEATURE_2_XSAVEC): Likewise. (GNU_PROPERTY_X86_FEATURE_1_AND): Updated to (GNU_PROPERTY_X86_UINT32_AND_LO + 0). (GNU_PROPERTY_X86_ISA_1_NEEDED): Defined to (GNU_PROPERTY_X86_UINT32_OR_LO + 0). (GNU_PROPERTY_X86_FEATURE_2_NEEDED): New. Defined to (GNU_PROPERTY_X86_UINT32_OR_LO + 1). (GNU_PROPERTY_X86_ISA_1_USED): Defined to (GNU_PROPERTY_X86_UINT32_OR_AND_LO + 0). (GNU_PROPERTY_X86_FEATURE_2_USED): New. Defined to (GNU_PROPERTY_X86_UINT32_OR_AND_LO + 1). ld/ * testsuite/ld-i386/i386.exp: Run pr23372c, pr23372d, pr23486c and pr23486d. * testsuite/ld-i386/pr23372a.s: Update comments. * testsuite/ld-i386/pr23372b.s: Likewise. * testsuite/ld-i386/pr23372c.s: Likewise. * testsuite/ld-x86-64/pr23372a.s: Likewise. * testsuite/ld-x86-64/pr23372b.s: Likewise. * testsuite/ld-x86-64/pr23372c.s: Likewise. * testsuite/ld-x86-64/pr23486a.s: Likewise. * testsuite/ld-x86-64/pr23486b.s: Likewise. * testsuite/ld-i386/pr23372c.d: New file. * testsuite/ld-i386/pr23372d.d: Likewise. * testsuite/ld-i386/pr23486c.d: Likewise. * testsuite/ld-i386/pr23486d.d: Likewise. * testsuite/ld-x86-64/pr23372c-x32.d: Likewise. * testsuite/ld-x86-64/pr23372c.d: Likewise. * testsuite/ld-x86-64/pr23372d-x32.d: Likewise. * testsuite/ld-x86-64/pr23372d.d: Likewise. * testsuite/ld-x86-64/pr23372d.s: Likewise. * testsuite/ld-x86-64/pr23372e.s: Likewise. * testsuite/ld-x86-64/pr23372f.s: Likewise. * testsuite/ld-x86-64/pr23486c-x32.d: Likewise. * testsuite/ld-x86-64/pr23486c.d: Likewise. * testsuite/ld-x86-64/pr23486c.s: Likewise. * testsuite/ld-x86-64/pr23486d-x32.d: Likewise. * testsuite/ld-x86-64/pr23486d.d: Likewise. * testsuite/ld-x86-64/pr23486d.s: Likewise. * testsuite/ld-i386/property-3.r: Updated. * testsuite/ld-i386/property-4.r: Likewise. * testsuite/ld-i386/property-5.r: Likewise. * testsuite/ld-i386/property-x86-3.d: Likewise. * testsuite/ld-i386/property-x86-ibt3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3b.d: Likewise. * testsuite/ld-x86-64/property-3.r: Likewise. * testsuite/ld-x86-64/property-4.r: Likewise. * testsuite/ld-x86-64/property-5.r: Likewise. * testsuite/ld-x86-64/property-x86-3-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-3.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise. * testsuite/ld-i386/property-x86-1.S: Updated to the current GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED values. * testsuite/ld-i386/property-x86-2.S: Likewise. * testsuite/ld-i386/property-x86-3.s: Likewise. * testsuite/ld-x86-64/property-x86-1.S: Likewise. * testsuite/ld-x86-64/property-x86-2.S: Likewise. * testsuite/ld-x86-64/property-x86-3.s: Likewise. * ld/testsuite/ld-x86-64/x86-64.exp: Run pr23372c, pr23372c-x32, pr23372d, pr23372d-x32, pr23486c, pr23486c-x32, pr23486d and pr23486d-x32.	8 years ago
H.J. Lu	aa7bca9b2e	x86: Add GNU_PROPERTY_X86_UINT32_VALID The older linker treats .note.gnu.property section as a generic note and just concatenates all .note.gnu.property sections from the input to the output. On CET-enabled OS, the output of the older linker is marked as CET enabled, but in fact, it is not CET enabled and it crashes on CET-enabled machines. This patch defines GNU_PROPERTY_X86_UINT32_VALID. Linker is updated to set the GNU_PROPERTY_X86_UINT32_VALID bit in GNU property note for non-relocatable output to differentiate outputs from the older linker. bfd/ * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Mask out the GNU_PROPERTY_X86_UINT32_VALID bit. (_bfd_x86_elf_link_fixup_gnu_properties): Set the GNU_PROPERTY_X86_UINT32_VALID bit for non-relocatable output. binutils/ * readelf.c (print_gnu_property_note): Check the GNU_PROPERTY_X86_UINT32_VALID bit for invalid GNU property note. include/ * elf/common.h (GNU_PROPERTY_X86_UINT32_VALID): New.	8 years ago
Alan Modra	ebf983a444	Fix changelog entries	8 years ago
John Darrington	4e57b45639	S12Z: Rename reloc R_S12Z_UKNWN_3 to R_S12Z_EXT18 and implement according to recently inferred information about this reloc. * bfd/elf32-s12z.c: (opru18_reloc): New function. * bfd/elf32-s12z.c: (elf_s12z_howto_table): Adjust Howto according to new knowledge. * include/elf/s12z.h: Rename R_S12Z_UKNWN_3 to R_S12Z_EXT18.	8 years ago
Alan Modra	9cf7e5687f	Use operand->extract to provide defaults for optional PowerPC operands Most optional operands to powerpc instructions use a default value of zero, but there are a few exceptions. Those have been handled by PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table for the default value, smuggled in the shift field. This patch changes that to using the operand extract function to provide non-zero defaults. I've also moved the code determining whether optional operands are provided or omitted, to the point the first optional operand is seen, and allowed for the possibility of optional base register operands in a future patch. The patch does change the error you get on invalid assembly like ld 3,4 You'll now see "missing operand" rather than "syntax error; end of line, expected `('". gas/ * config/tc-ppc.c (md_assemble): Delay counting of optional operands until one is encountered. Allow for the possibility of optional base regs, ie. PPC_OPERAND_PARENS. Call ppc_optional_operand_value with extra args. include/ * opcode/ppc.h (struct powerpc_operand): Correct "insert" comment. Mention use of "extract" function to provide default value. (PPC_OPERAND_OPTIONAL_VALUE): Delete. (ppc_optional_operand_value): Rewrite to use extract function. opcodes/ * ppc-dis.c (operand_value_powerpc): Init "invalid". (skip_optional_operands): Count optional operands, and update ppc_optional_operand_value call. * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg. (extract_vlensi): Likewise. (extract_fxm): Return default value for missing optional operand. (extract_ls, extract_raq, extract_tbr): Likewise. (insert_sxl, extract_sxl): New functions. (insert_esync, extract_esync): Remove Power9 handling and simplify. (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE flag and extra entry. (powerpc_operands <SXL>): Likewise, and use insert_sxl and extract_sxl.	8 years ago
Alan Modra	08a8fe2ffd	Fix s12z test regexps Fixes ERROR: tcl error sourcing .../gas/testsuite/gas/s12z/s12z.exp. ERROR: couldn't compile regular expression pattern: quantifier operand invalid run_dump_test expected output lines are regexps. * testsuite/gas/s12z/bit-manip-invalid.d: Correct regexps.	8 years ago
Alan Modra	d203b41ac7	Tidy bit twiddling * sh-opc.h (MASK): Simplify.	8 years ago
John Darrington	7ba3ba91a3	S12Z: Move opcode header to public include directory. opcodes/ * s12z.h: Delete. * s12z-dis.c: Adjust path of included file. include/ * opcode/s12z.h: New file. gas/ * config/tc-s12z.c: Adjust path of included file.	8 years ago
Richard Earnshaw	57285adece	arm - Add some comments about the versions of ARM ELF that define various e_flags values This patch adds a few comments to include/elf/arm.h to clarify which versions of the ARM ELF specification defined which headers. Given that the EABI is pretty ubiquitous these days, I've marked anything not based on that as deprecated. There are no plans to remove any deprecated definitions at this time, but any new development shouldn't be building upon support for deprecated definitions remaining in the long term. * elf/arm.h: Updated comments for e_flags definitions.	8 years ago
claziss	db1e1b45b4	[ARC] Add Tag_ARC_ATR_version. Add a new tag (Tag_ARC_ATR_version) used to indicate if current attributes are interpreted in GNU way. This attribute is used by Synopsys custom compiler to correctly identify and interpret the object attributes section as generated by GNU tools. gas/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_set_public_attributes): Add Tag_ARC_ATR_version. (arc_convert_symbolic_attribute): Likewise. * testsuite/gas/arc/attr-arc600.d: Update test. * testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc600_norm.d: Likewise. * testsuite/gas/arc/attr-arc601.d: Likewise. * testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc601_mul64.d: Likewise. * testsuite/gas/arc/attr-arc601_norm.d: Likewise. * testsuite/gas/arc/attr-arc700.d: Likewise. * testsuite/gas/arc/attr-arcem.d: Likewise. * testsuite/gas/arc/attr-archs.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.d: Likewise. * testsuite/gas/arc/attr-cpu-a601.d: Likewise. * testsuite/gas/arc/attr-cpu-a700.d: Likewise. * testsuite/gas/arc/attr-cpu-em.d: Likewise. * testsuite/gas/arc/attr-cpu-hs.d: Likewise. * testsuite/gas/arc/attr-em.d: Likewise. * testsuite/gas/arc/attr-em4.d: Likewise. * testsuite/gas/arc/attr-em4_dmips.d: Likewise. * testsuite/gas/arc/attr-em4_fpuda.d: Likewise. * testsuite/gas/arc/attr-em4_fpus.d: Likewise. * testsuite/gas/arc/attr-hs.d: Likewise. * testsuite/gas/arc/attr-hs34.d: Likewise. * testsuite/gas/arc/attr-hs38.d: Likewise. * testsuite/gas/arc/attr-hs38_linux.d: Likewise. * testsuite/gas/arc/attr-mul64.d: Likewise. * testsuite/gas/arc/attr-name.d: Likewise. * testsuite/gas/arc/attr-nps400.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.d: Likewise. * testsuite/gas/arc/attr-quarkse_em.d: Likewise. bfd/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * elf32-arc.c (arc_elf_merge_attributes): Handle Tag_ARC_ATR_version. binutils/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (display_arc_attribute): Print Tag_ARC_ATR_version. include/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * elf/arc.h (Tag_ARC_ATR_version): New tag. ld/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/attr-merge-0.d: Update test. * testsuite/ld-arc/attr-merge-1.d: Likewise. * testsuite/ld-arc/attr-merge-2.d: Likewise. * testsuite/ld-arc/attr-merge-3.d: Likewise. * testsuite/ld-arc/attr-merge-5.d: Likewise.	8 years ago
claziss	b6523c37fb	[ARC] Update handling AUX-registers. Update aux-registers data-base, and accept aux-registers names with upper/lowercase names. opcode/ 2017-07-18 Claudiu Zissulescu <claziss@synopsys.com> * arc-regs.h: Update aux-registers. gas/ 2017-07-18 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (find_opcode_match): Accept uppercase aux-regs names. * testsuite/gas/arc/ld2.d: Update test. * testsuite/gas/arc/taux.d: Likewise. * testsuite/gas/arc/taux.s: Likewise. include/ 2017-07-18 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (ARC_OPCODE_ARCV1): Define.	8 years ago
marxin	50320b1d4a	Copy from GCC: Add linker_output as prefix for LTO temps (PR lto/86548). 2018-07-26 Martin Liska <mliska@suse.cz> PR lto/86548 * libiberty.h (make_temp_file_with_prefix): New function. 2018-07-26 Martin Liska <mliska@suse.cz> PR lto/86548 * make-temp-file.c (TEMP_FILE): Remove leading 'cc'. (make_temp_file): Call make_temp_file_with_prefix with first argument set to NULL. (make_temp_file_with_prefix): Support also prefix. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@262999 138bc75d-0d04-0410-961f-82ee72b054a4	8 years ago
Jim Wilson	eb41b24898	RISC-V: Set insn info fields correctly when disassembling. include/ * opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR) (INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE) (INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size fields. * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.	8 years ago
Andrew Jenner	b8891f8d62	Add support for the C_SKY series of processors. This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc. This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about. bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY. (BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise. * Makefile.in: Regenerated. * archures.c (enum bfd_architecture): Add bfd_arch_csky and related bfd_mach defines. (bfd_csky_arch): Declare. (bfd_archures_list): Add C-SKY. * bfd-in.h (elf32_csky_build_stubs): Declare. (elf32_csky_size_stubs): Declare. (elf32_csky_next_input_section: Declare. (elf32_csky_setup_section_lists): Declare. * bfd-in2.h: Regenerated. * config.bfd: Add C-SKY. * configure.ac: Likewise. * configure: Regenerated. * cpu-csky.c: New file. * elf-bfd.h (enum elf_target_id): Add C-SKY. * elf32-csky.c: New file. * libbfd.h: Regenerated. * reloc.c: Add C-SKY relocations. * targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare. (_bfd_target_vector): Add C-SKY target vector entries. binutils* readelf.c: Include elf/csky.h. (guess_is_rela): Handle EM_CSKY. (dump_relocations): Likewise. (get_machine_name): Likewise. (is_32bit_abs_reloc): Likewise. include * dis-asm.h (csky_symbol_is_valid): Declare. * opcode/csky.h: New file. opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c. * Makefile.in: Regenerated. * configure.ac: Add C-SKY. * configure: Regenerated. * csky-dis.c: New file. * csky-opc.h: New file. * disassemble.c (ARCH_csky): Define. (disassembler, disassemble_init_for_target): Add case for ARCH_csky. * disassemble.h (print_insn_csky, csky_get_disassembler): Declare. gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY. (TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise. * Makefile.in: Regenerated. * config/tc-csky.c: New file. * config/tc-csky.h: New file. * config/te-csky_abiv1.h: New file. * config/te-csky_abiv1_linux.h: New file. * config/te-csky_abiv2.h: New file. * config/te-csky_abiv2_linux.h: New file. * configure.tgt: Add C-SKY. * doc/Makefile.am (CPU_DOCS): Add entry for C-SKY. * doc/Makefile.in: Regenerated. * doc/all.texi: Set CSKY feature. * doc/as.texi (Overview): Add C-SKY options. (Machine Dependencies): Likewise. * doc/c-csky.texi: New file. * testsuite/gas/csky/: New test cases. ld Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations. (ecskyelf.c, ecskyelf_linux.c): New rules. * Makefile.in: Regenerated. * configure.tgt: Add C-SKY. * emulparams/cskyelf.sh: New file. * emulparams/cskyelf_linux.sh: New file. * emultempl/cskyelf.em: New file. * gen-doc.texi: Add C-SKY. * ld.texi: Likewise. (Options specific to C-SKY targets): New section. * testsuite/ld-csky/*: New tests.	8 years ago
Chenghua Xu	2bb9bbe2e8	MIPS/GAS: Correct the AFL_ASE_MASK macro Fix an issue with commit `8095d2f70e` ("MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a"), AFL_ASE_MASK should be 0x0006ffff instead of 0x0004ffff. 2018-07-27 Chenghua Xu <paul.hua.gm@gmail.com> Maciej W. Rozycki <macro@linux-mips.org> include/ * elf/mips.h (AFL_ASE_MASK): Correct typo.	8 years ago
Alex Chadwick	fa758a7046	PowerPC Improve support for Gekko & Broadway This is a relatively straightforward patch to improve support for the IBM Gekko and IBM Broadway processors. Broadway is functionally equivalent to the IBM 750CL, while Gekko's functionality is a subset of theirs. The patch simplifies this reality and adds -mgekko and -mbroadway as aliases for -m750cl. I didn't feel it was worth wasting a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of simplified mnemonics for special purpose register access. Notably, Broadway adds 4 additional IBAT and DBAT registers but these are not assigned sequential SPR numbers. gas/ * config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway. * doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * testsuite/gas/ppc/broadway.d, * testsuite/gas/ppc/broadway.s: New test for broadway. * testsuite/gas/ppc/ppc.exp: Run new test. include/ * opcode/ppc.h (PPC_OPCODE_750): Adjust comment. opcodes/ * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. (powerpc_init_dialect): Handle bfd_mach_ppc_750. * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to support disjointed BAT. (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. (XSPRGQR_MASK, GEKKO, BROADWAY): Define. (powerpc_opcodes): Add 750cl extended mnemonics for spr access.	8 years ago
Alan Modra	33cb30a1f9	Implement PowerPC64 .localentry for value 1 This adds support for ".localentry 1", a new st_other STO_PPC64_LOCAL_MASK encoding that signifies a function with a single entry point like ".localentry 0", but unlike a ".localentry 0" function does not preserve r2. include/ * elf/ppc64.h: Specify byte offset to local entry for values of two to six in STO_PPC64_LOCAL_MASK. Clarify r2 return value for such functions when entering via global entry point. Specify meaning of a value of one in STO_PPC64_LOCAL_MASK. bfd/ * elf64-ppc.c (ppc64_elf_size_stubs): Use a ppc_stub_long_branch_r2off for calls to symbols with STO_PPC64_LOCAL_MASK bits set to 1. gas/ * config/tc-ppc.c (ppc_elf_localentry): Allow .localentry values of 1 and 7 to directly set value into STO_PPC64_LOCAL_MASK bits. ld/testsuite/ * ld-powerpc/elfv2.s: Add .localentry f5,1 testcase. * ld-powerpc/elfv2exe.d: Update. * ld-powerpc/elfv2so.d: Update.	8 years ago
Alan Modra	67ce483baa	PR23430, Indices misspelled PR 23430 include/ * elf/common.h (SHT_SYMTAB_SHNDX): Fix comment typo. bfd/ * dwarf2.c (dwarf_debug_section_enum): Fix comment typo. * elf.c (bfd_section_from_shdr, elf_sort_sections): Likewise. binutils/ * elfcomm.h (struct archive_info): Rename uses_64bit_indicies to uses_64bit_indices. * elfcomm.c (setup_archive): Update uses of above. * readelf.c (process_archive): Likewise. (get_section_type_name): Rename indicies to indices. (get_32bit_elf_symbols, get_64bit_elf_symbols): Likewise. (process_section_groups): Likewise. cpu/ * or1kcommon.cpu (spr-reg-indices): Fix description typo. opcodes/ * or1k-desc.h: Regenerate.	8 years ago
Chenghua Xu	8095d2f70e	MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a The MMI instruction set has been implemented in many Loongson processors. There is a lot of software optimized for MMI. This patch splits MMI from loongson2f/3a, and adds GAS and disassembler options for MMI instructions. 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com> Maciej W. Rozycki <macro@mips.com> bfd/ * elfxx-mips.c (print_mips_ases): Add MMI extension. binutils/ * readelf.c (print_mips_ases): Add MMI extension. gas/ * NEWS: Mention MultiMedia extensions Instructions (MMI) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and OPTION_NO_LOONGSON_MMI. (md_longopts): Likewise. (mips_ases): Define availability for MMI. (mips_convert_ase_flags): Map ASE_LOONGSON_MMI to AFL_ASE_LOONGSON_MMI. (mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a. (md_show_usage): Add help for -mloongson-mmi and -mno-loongson-mmi. * doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi. * doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi, .set loongson-mmi and .set noloongson-mmi. * testsuite/gas/mips/loongson-2f.d: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-2f.s: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.s: Here. * testsuite/gas/mips/loongson-3a.d: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-3a.s: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.s: Here. * testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and loongson-3a-mmi tests. include/ * elf/mips.h (AFL_ASE_MMI): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI. * opcode/mips.h (ASE_LOONGSON_MMI): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-mmi option. (print_mips_disassembler_options): Document -M loongson-mmi. * mips-opc.c (LMMI): New macro. (mips_opcodes): Replace IL2F\|IL3A marking with LMMI for MMI instructions.	8 years ago
Maciej W. Rozycki	d5c928c053	LD: Export relative-from-absolute symbol marking to BFD It is usually possible to tell absolute and ordinary symbols apart in BFD throughout the link, by checking whether the section that owns the symbol is absolute or not. That however does not work for ordinary symbols defined in a linker script outside an output section statement. Initially such symbols are entered into to the link hash as absolute symbols, owned by the absolute section. A flag is set in the internal linker expression defining such symbols to tell the linker to convert them to section-relative ones in the final phase of the link. That flag is however not accessible to BFD linker code, including BFD target code in particular. Add a flag to the link hash then to copy the information held in the linker expression. Define a macro, `bfd_is_abs_symbol', for BFD code to use where determining whether a symbol is absolute or ordinary is required before the final link phase. This macro will correctly identify the special `__ehdr_start' symbol as ordinary throughout link, for example, even though early on it will be assigned to the absolute section. Of course this does not let BFD code identify what the symbol's ultimate section will be before the final link phase has converted this symbol (in `update_definedness'). include/ * bfdlink.h (bfd_link_hash_entry): Add `rel_from_abs' member. bfd/ * linker.c (bfd_is_abs_symbol): New macro. * bfd-in2.h: Regenerate. ld/ * ldexp.c (exp_fold_tree_1) <etree_assign, etree_provide> <etree_provided>: Copy expression's `rel_from_abs' flag to the link hash.	8 years ago
Alan Modra	fe75810f8e	Fix diagnostic errors Fixes a number of build errors like the following .../elf32-arm.c: In function 'elf32_arm_nabi_write_core_note': .../elf32-arm.c:2177: error: #pragma GCC diagnostic not allowed inside functions .../elf32-arm.c:2186: error: #pragma GCC diagnostic not allowed inside functions See the comment in diagnostics.h. include/ * diagnostics.h: Comment on macro usage. bfd/ * elf32-arm.c (elf32_arm_nabi_write_core_note): Don't use DIAGNOTIC_PUSH and DIAGNOSTIC_POP unconditionally. * elf32-ppc.c (ppc_elf_write_core_note): Likewise. * elf32-s390.c (elf_s390_write_core_note): Likewise. * elf64-ppc.c (ppc64_elf_write_core_note): Likewise. * elf64-s390.c (elf_s390_write_core_note): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_write_core_note): Likewise.	8 years ago
Simon Marchi	6821842f15	darwin: Silence syscall deprecated declaration warning This patch silences this warning: /Users/simark/src/binutils-gdb/gdb/darwin-nat.c:839:10: error: 'syscall' is deprecated: first deprecated in macOS 10.12 - syscall(2) is unsupported; please switch to a supported interface. For SYS_kdebug_trace use kdebug_signpost(). [-Werror,-Wdeprecated-declarations] res = syscall (SYS___pthread_kill, thread->gdb_port, nsignal); ^ /usr/include/unistd.h:745:6: note: 'syscall' has been explicitly marked deprecated here int syscall(int, ...); ^ The comment of the new pthread_kill function explains why we use the syscall function directly. include/ChangeLog: * diagnostics.h (DIAGNOSTIC_IGNORE_DEPRECATED_DECLARATIONS): Define for clang. gdb/ChangeLog: * darwin-nat.c (darwin_pthread_kill): New function. (darwin_resume_thread): Use darwin_pthread_kill.	8 years ago
Maciej W. Rozycki	471b9d1507	GDB PR tdep/8282: MIPS: Wire in `set disassembler-options' Implement MIPS target support for passing options to the disassembler, complementing commit `65b48a8140` ("GDB: Add support for the new set/show disassembler-options commands."). This includes options that expect an argument, so adjust the generic code and data structures used so as to handle such options. So as to give backends syntax flexibility no specific delimiter has been defined to separate options from their respective arguments, so it has to be included as the last character of the option name. Completion code however has not been adjusted and consequently option arguments cannot be completed at this time. Also the MIPS target has non-empty defaults for the options, so that ABI names for the general-purpose registers respect our `set mips abi ...' setting rather than always being determined from the ELF headers of the binary file selected. Handle these defaults as implicit options, never shown to the user and always prepended to the user-specified options, so that the latters can override the defaults. The resulting output for the MIPS target is as follows: (gdb) show disassembler-options The current disassembler options are '' The following disassembler options are supported for use with the 'set disassembler-options <option>[,<option>...]' command: no-aliases Use canonical instruction forms. msa Recognize MSA instructions. virt Recognize the virtualization ASE instructions. xpa Recognize the eXtended Physical Address (XPA) ASE instructions. ginv Recognize the Global INValidate (GINV) ASE instructions. gpr-names=ABI Print GPR names according to specified ABI. Default: based on binary being disassembled. fpr-names=ABI Print FPR names according to specified ABI. Default: numeric. cp0-names=ARCH Print CP0 register names according to specified architecture. Default: based on binary being disassembled. hwr-names=ARCH Print HWR names according to specified architecture. Default: based on binary being disassembled. reg-names=ABI Print GPR and FPR names according to specified ABI. reg-names=ARCH Print CP0 register and HWR names according to specified architecture. For the options above, the following values are supported for "ABI": numeric 32 n32 64 For the options above, the following values are supported for "ARCH": numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600 r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000 r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64 mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp (gdb) which corresponds to what `objdump --help' used to print for the MIPS target, with minor formatting changes, most notably option argument lists being wrapped, but also the amount of white space separating options from the respective descriptions. The relevant part the new code is now also used by `objdump --help', which means these formatting changes apply to both outputs, except for argument list wrapping, which is GDB-specific. This also adds a separating new line between the heading and option lists where descriptions are provided, hence: (gdb) set architecture s390:31-bit (gdb) show disassembler-options The current disassembler options are '' The following disassembler options are supported for use with the 'set disassembler-options <option>[,<option>...]' command: esa Disassemble in ESA architecture mode zarch Disassemble in z/Architecture mode insnlength Print unknown instructions according to length from first two bits (gdb) but: (gdb) set architecture powerpc:common (gdb) show disassembler-options The current disassembler options are '' The following disassembler options are supported for use with the 'set disassembler-options <option>[,<option>...]' command: 403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl, 821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300, e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5, power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge, ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe, spe2, titan, vle, vsx (gdb) Existing affected target backends have been adjusted accordingly. This has been verified manually with: (gdb) set architecture arm (gdb) set architecture powerpc:common (gdb) set architecture s390:31-bit to cause no issues with the `show disassembler-options' and `set disassembler-options' commands. A test case for the MIPS target has also been provided, covering the default settings with ABI overrides as well as disassembler option overrides. 2018-07-02 Maciej W. Rozycki <macro@mips.com> Simon Marchi <simon.marchi@polymtl.ca> include/ PR tdep/8282 * dis-asm.h (disasm_option_arg_t): New typedef. (disasm_options_and_args_t): Likewise. (disasm_options_t): Add `arg' member, document members. (disassembler_options_mips): New prototype. (disassembler_options_arm, disassembler_options_powerpc) (disassembler_options_s390): Update prototypes. opcodes/ PR tdep/8282 * mips-dis.c (mips_option_arg_t): New enumeration. (mips_options): New variable. (disassembler_options_mips): New function. (print_mips_disassembler_options): Reimplement in terms of `disassembler_options_mips'. * arm-dis.c (disassembler_options_arm): Adapt to using the `disasm_options_and_args_t' structure. * ppc-dis.c (disassembler_options_powerpc): Likewise. * s390-dis.c (disassembler_options_s390): Likewise. gdb/ PR tdep/8282 * disasm.h (gdb_disassembler): Add `m_disassembler_options_holder'. member * disasm.c (get_all_disassembler_options): New function. (gdb_disassembler::gdb_disassembler): Use it. (gdb_buffered_insn_length_init_dis): Likewise. (gdb_buffered_insn_length): Adjust accordingly. (set_disassembler_options): Handle options with arguments. (show_disassembler_options_sfunc): Likewise. Add a leading new line if showing options with descriptions. (disassembler_options_completer): Adapt to using the `disasm_options_and_args_t' structure. * mips-tdep.c (mips_disassembler_options): New variable. (mips_disassembler_options_o32): Likewise. (mips_disassembler_options_n32): Likewise. (mips_disassembler_options_n64): Likewise. (gdb_print_insn_mips): Don't set `disassembler_options'. (gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove functions. (mips_gdbarch_init): Always set `gdbarch_print_insn' to `gdb_print_insn_mips'. Set `gdbarch_disassembler_options', `gdbarch_disassembler_options_implicit' and `gdbarch_valid_disassembler_options'. * arm-tdep.c (_initialize_arm_tdep): Adapt to using the `disasm_options_and_args_t' structure. * gdbarch.sh (disassembler_options_implicit): New `gdbarch' method. (valid_disassembler_options): Switch from `disasm_options_t' to the `disasm_options_and_args_t' structure. * NEWS: Document `set disassembler-options' support for the MIPS target. * gdbarch.h: Regenerate. * gdbarch.c: Regenerate. gdb/doc/ PR tdep/8282 * gdb.texinfo (Source and Machine Code): Document `set disassembler-options' support for the MIPS target. gdb/testsuite/ PR tdep/8282 * gdb.arch/mips-disassembler-options.exp: New test. * gdb.arch/mips-disassembler-options.s: New test source.	8 years ago
Tamar Christina	369c9167d4	Fix AArch64 encodings for by element instructions. Some instructions in Armv8-a place a limitation on FP16 registers that can be used as the register from which to select an element from. e.g. fmla restricts Rm to 4 bits when using an FP16 register. This restriction does not apply for all instructions, e.g. fcmla does not have this restriction as it gets an extra bit from the M field. Unfortunately, this restriction to S_H was added for all _Em operands before, meaning for a large number of instructions you couldn't use the full register file. This fixes the issue by introducing a new operand _Em16 which applies this restriction only when paired with S_H and leaves the _Em and the other qualifiers for _Em16 unbounded (i.e. using the full 5 bit range). Also the patch updates all instructions that should be affected by this. opcodes/ PR binutils/23192 * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. * aarch64-opc.c (operand_general_constraint_met_p, aarch64_print_operand): Likewise. * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, fmlal2, fmlsl2. (AARCH64_OPERANDS): Add Em2. gas/ PR binutils/23192 * config/tc-aarch64.c (process_omitted_operand, parse_operands): Add AARCH64_OPND_Em16 * testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper 16 registers. * testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise. * testsuite/gas/aarch64/advsimd-compnum.s: Likewise. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise. * testsuite/gas/aarch64/sve.d: Likewise. include/ PR binutils/23192 *opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.	8 years ago
Alan Modra	2393a7e3e6	Revert "Use offsets instead of addresses in ELF_SECTION_IN_SEGMENT for non SHT_NOBITS" This reverts commit `57c0d77c2c`.	8 years ago

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1051 Commits (dad0c3bfb5e32ff3f2a03830dc189fe207c7ae00)