binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Andreas Krebbel	c8fa16ed5a	2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * config/tc-s390.c (md_gather_operands): Fix check for floating register pair operands. 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * opcode/s390.h: Replace S390_OPERAND_REG_EVEN with S390_OPERAND_REG_PAIR. 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.c: Replace S390_OPERAND_REG_EVEN with S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type. * s390-opc.txt: Fix cxr instruction type. 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/esa-g5.d: Fix fp register pair operands. * gas/s390/esa-g5.s: Likewise. * gas/s390/zarch-z196.d: Likewise. * gas/s390/zarch-z196.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z9-ec.d: Likewise. * gas/s390/zarch-z9-ec.s: Likewise.	15 years ago
Andreas Krebbel	5e4b319cdc	2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * config/tc-s390.c (md_gather_operands): Emit an error for odd numbered registers used as register pair operand. 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * opcode/s390.h: Add S390_OPCODE_REG_EVEN flag. 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.c: Add new instruction types marking register pair operands. * s390-opc.txt: Match instructions having register pair operands to the new instruction types. 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/esa-g5.d: Fix register pair operands. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z196.d: Likewise. * gas/s390/zarch-z196.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z900.d: Likewise. * gas/s390/zarch-z900.s: Likewise. * gas/s390/zarch-z990.d: Likewise. * gas/s390/zarch-z990.s: Likewise.	15 years ago
Nick Clifton	fda544a25c	* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2 operands.	15 years ago
Quentin Neill	4cab4add34	2011-05-10 Quentin Neill <quentin.neill@amd.com> gas/ * config/tc-i386.c (cpu_arch): Add bdver2 and rename PROCESSOR_BDVER1 to PROCESSOR_BDVER. (i386_align_code): Rename PROCESSOR_BDVER1. (processor_type): Ditto. * doc/c-i386.texi: Add bdver2. opcodes/ * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS. * i386-init.h: Regenerated. gas/testsuite/ * gas/i386/i386.exp: Add new bdver2 test cases. * gas/i386/nops-1-bdver2.d: New. * gas/i386/x86-64-nops-1-bdver2.d: New.	15 years ago
Nick Clifton	b4e7b88557	Updated Danish, Esperanto and French translations.	15 years ago
Alan Modra	2f7f771012	* ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.	15 years ago
DJ Delorie	9887672fa6	* rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs. * rx-decode.c: Regenerate.	15 years ago
H.J. Lu	3251b3756a	Regenerate i386-init.h. 2011-04-20 H.J. Lu <hongjiu.lu@intel.com> * i386-init.h: Regenerated.	15 years ago
Quentin Neill	b13a3ca683	* i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits from bdver1 flags.	15 years ago
Nick Clifton	00bbc0bdc6	* config/tc-arm.c (v7m_psrs): Revert previous delta. * gas/arm/mrs-msr-thumb-v7e-m.s: Restore name of basepri_max register. * gas/arm/mrs-msr-thumb-v7e-m.d: Likewise. * gas/arm/arch7.d: Likewise. * gas/arm/arch7.s: Likewise. * arm-dis.c: Revert previous reversion.	15 years ago
Nick Clifton	ac7f631be1	* gas/arm/arch7.s: Fix typo basepri_max should be basepri_mask. * gas/arm/mrs-msr-thumb-v7e-m.s: Likewise. * gas/arm/arch7.d: Update expected disassembly. * gas/arm/attr-march-armv7.d: Remove Microcontroller tag. * gas/arm/blx-bad.d: Only run for ELF based targets. * gas/arm/mrs-msr-thumb-v6t2.d: Likewise. * gas/arm/vldm-arm.d: Likewise. * gas/arm/mrs-msr-thumb-v7-m.d: Likewise. Remove qualifiers from PSR and IAPSR regsiter names. * gas/arm/mrs-msr-thumb-v7e-m.d: Likewise. * gas/arm/thumb2_bcond.d: Update expected disassembly to allow for relaxing of branch insns. * gas/arm/thumb32.d: Fix whitespace problems in disassembly. * config/tc-arm.c (parse_psr): Use selected_cpu not cpu_variant to detect M-profile targets. (do_t_swi): Exclude v7 and higher variants from arm_ext_os test. (v7m_psrs): Fix typo: basepri_max should be basepri_mask. * arm-dis.c (psr_name): Revert previous delta. * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.	15 years ago
Nick Clifton	7d063384af	* v850-dis.c (disassemble): Always print a closing square brace if an opening square brace was printed.	15 years ago
Nick Clifton	32a946987b	PR binutils/12534 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn patterns. (print_insn_thumb32): Handle %L. * gas/arm/thumb32.s: Add PC relative LDRD and STRD insns. * gas/arm/thumb32.l: Update expected output. * gas/arm/thumb32.d: Update expected disassembly.	15 years ago
Julian Brown	d2cd120565	gas/ * config/tc-arm.c (parse_psr): Add LHS argument. Improve support for APSR bitmasks. (operand_parse_code): Replace OP_PSR with OP_wPSR and OP_rPSR. Remove OP_RVC_PSR. (parse_operands): Likewise. (do_mrs): Tweak error message for constraint. (do_t_mrs): Update constraints for changes to APSR support. (do_t_msr): Likewise. Don't set PSR_f flag here. (psrs): Remove "g", "nzcvq", "nzcvqg". (insns): Tweak entries for msr and mrs instructions. opcodes/ arm-dis.c (psr_name): Fix typo for BASEPRI_MAX. (print_insn_thumb32): Add APSR bitmask support. gas/testsuite/ * gas/arm/mrs-msr-thumb-v7-m.s: New. * gas/arm/mrs-msr-thumb-v7-m.d: New. * gas/arm/mrs-msr-thumb-v7-m-bad.d: New. * gas/arm/mrs-msr-thumb-v7-m-bad.l: New. * gas/arm/mrs-msr-thumb-v7-m-bad.s: New. * gas/arm/mrs-msr-thumb-v7e-m.d: New. * gas/arm/mrs-msr-thumb-v7e-m.s: New. * gas/arm/mrs-msr-arm-v7-a-bad.d: New. * gas/arm/mrs-msr-arm-v7-a-bad.l: New. * gas/arm/mrs-msr-arm-v7-a-bad.s: New. * gas/arm/mrs-msr-arm-v7-a.d: New. * gas/arm/mrs-msr-arm-v7-a.s: New. * gas/arm/mrs-msr-arm-v6.d: New. * gas/arm/mrs-msr-arm-v6.s: New. * gas/arm/mrs-msr-thumb-v6t2.d: New. * gas/arm/mrs-msr-thumb-v6t2.s: New. * gas/arm/arch7.d: Fix typo in disassembly for BASEPRI_MAX, bitmasks for IAPSR etc. * gas/arm/arch7.s: Specify bitmask for APSR writes. * gas/arm/archv6m.s: Likewise. * msr-imm-bad.l: Tweak expected disassembly in error message. * msr-reg-bad.l: Likewise. * msr-imm.d: Tweak expected disassembly. * msr-reg.d: Likewise. * msr-reg-thumb.d: Likewise. * msr-imm.s: Specify bitmask on APSR writes. * msr-reg.s: Add comment about deprecated usage.	15 years ago
Paul Brook	1fbaefec00	2011-04-07 Paul Carroll<pcarroll@codesourcery.com> opcodes/ * arm-dis.c (print_insn): init vars moved into private_data structure. binutils/testsuite/ * binutils-all/arm/simple.s: Demo issue with objdump with multiple input files * binutils-all/arm/objdump.exp: added new ARM test case code	15 years ago
Mike Frysinger	67171547aa	opcodes: blackfin: ignore (M) on MAC0-only dsp mac funcs If the MAC1 part of the insn is disabled, then the (M) flag is ignored. Rather than include it in the decode, move the MM clearing to the MAC0 portion of the code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Eric B. Weddington	8cc66334fa	/bfd: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * archures.c: Add AVR XMEGA architecture information. * cpu-avr.c (arch_info_struct): Likewise. * elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise. (elf32_avr_object_p): Likewise. /gas: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (struct avr_opcodes_s): Add opcode field. (AVR_INSN): Change definition to match. (avr_opcodes): Likewise, change to match. (mcu_types): Add XMEGA architecture names and new XMEGA device names. (md_show_usage): Add XMEGA architecture names. (avr_operand): Add 'E' constraint for DES instruction of XMEGA devices. Add support for SPM Z+ instruction. * doc/c-avr.texi: Add documentation for XMEGA architectures and devices. /include/opcode: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA): New instruction set flags. (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA. /ld: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures. (eavrxmega?.c): Likewise. * configure.tgt (targ_extra_emuls): Likewise. * emulparams/avrxmega1.sh: New file. * emulparams/avrxmega2.sh: Likewise. * emulparams/avrxmega3.sh: Likewise. * emulparams/avrxmega4.sh: Likewise. * emulparams/avrxmega5.sh: Likewise. * emulparams/avrxmega6.sh: Likewise. * emulparams/avrxmega7.sh: Likewise. * emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation): Add avrxmega6, avrxmega7 to list of architectures for no stubs. /opcodes: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * avr-dis.c (avr_operand): Add opcode_str parameter. Check for post-increment to support LPM Z+ instruction. Add support for 'E' constraint for DES instruction. (print_insn_avr): Adjust calls to avr_operand. Rename variable.	15 years ago
Richard Sandiford	34e77a920a	include/elf/ * arm.h (R_ARM_IRELATIVE): New relocation. bfd/ * reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation. * bfd-in2.h: Regenerate. * elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE entry. (elf32_arm_howto_from_type): Update accordingly. (elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE. (elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3. (arm_plt_info): New structure, split out from elf32_arm_link_hash_entry with an extra noncall_refcount field. (arm_local_iplt_info): New structure. (elf_arm_obj_tdata): Add local_iplt. (elf32_arm_local_iplt): New accessor macro. (elf32_arm_link_hash_entry): Replace plt_thumb_refcount, plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info. Change tls_type to a bitfield and add is_iplt. (elf32_arm_link_hash_newfunc): Update accordingly. (elf32_arm_allocate_local_sym_info): New function. (elf32_arm_create_local_iplt): Likewise. (elf32_arm_get_plt_info): Likewise. (elf32_arm_plt_needs_thumb_stub_p): Likewise. (elf32_arm_get_local_dynreloc_list): Likewise. (create_ifunc_sections): Likewise. (elf32_arm_copy_indirect_symbol): Update after the changes to elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set. (arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info to get PLT information. Assert that all STT_GNU_IFUNC references are turned into PLT references. (arm_build_one_stub): Pass the symbol type to elf32_arm_final_link_relocate. (elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub. (elf32_arm_allocate_irelocs): New function. (elf32_arm_add_dynreloc): In static objects, use .rel.iplt for all R_ARM_IRELATIVE. (elf32_arm_allocate_plt_entry): New function. (elf32_arm_populate_plt_entry): Likewise. (elf32_arm_final_link_relocate): Add an st_type parameter. Set srelgot to null for static objects. Use separate variables to record which st_value and st_type should be used when generating a dynamic relocation. Use elf32_arm_get_plt_info to find the symbol's PLT information, setting has_iplt_entry, splt, plt_offset and gotplt_offset accordingly. Check whether STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change the relocation target accordingly. Broaden assert to include .iplts. Don't set sreloc for static relocations. Assert that we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32 and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC symbol. Pass the symbol type to arm_type_of_stub. Conditionally resolve GOT references to the .igot.plt entry. (elf32_arm_relocate_section): Update the call to elf32_arm_final_link_relocate. (elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call relocations in shared libraries and relocatable executables. Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list to get the list of dynamic relocations for a local symbol. (elf32_arm_check_relocs): Always create ifunc sections. Set isym at the same time as setting h. Use elf32_arm_allocate_local_sym_info to allocate local symbol information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call relocations in shared libraries and relocatable executables. Record PLT information for local STT_GNU_IFUNC functions as well as global functions. Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list to get the list of dynamic relocations for a local symbol. (elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols. Don't remove STT_GNU_IFUNC PLTs unless all references have been removed. Update after the changes to elf32_arm_link_hash_entry. (allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT entries should live in .plt or .iplt. Check whether the .igot.plt and .got entries can be combined. Use elf32_arm_allocate_plt_entry to allocate .plt and .(i)got.plt entries. Detect which .got entries will need R_ARM_IRELATIVE relocations and use elf32_arm_allocate_irelocs to allocate them. Likewise other non-.got dynamic relocations. (elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt and dynamic relocations for local STT_GNU_IFUNC symbols. Check whether the .igot.plt and .got entries can be combined. Detect which .got entries will need R_ARM_IRELATIVE relocations and use elf32_arm_allocate_irelocs to allocate them. Use stashed section pointers intead of strcmp checks. Handle iplt and igotplt. (elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry to fill in .plt, .got.plt and .rel(a).plt entries. Point STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations resolve to it. (elf32_arm_output_plt_map_1): New function, split out from elf32_arm_output_plt_map. Handle .iplt entries. Use elf32_arm_plt_needs_thumb_stub_p. (elf32_arm_output_plt_map): Call it. (elf32_arm_output_arch_local_syms): Add mapping symbols for local .iplt entries. (elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols. (elf32_arm_swap_symbol_out): Likewise. (elf32_arm_add_symbol_hook): New function. (elf_backend_add_symbol_hook): Define for all targets. opcodes/ * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code. gas/ * config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to determine whether a relocation is needed. (md_apply_fix, arm_apply_sym_value): Likewise. ld/testsuite/ * ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd, ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd, ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s, ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd, ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd, ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd, ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s, ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd, ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd, ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd, ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s, ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd, ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd, ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd, ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s, ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd, ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd, ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd, ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s, ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd, ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd, ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld, ld-arm/ifunc-static.ld: New tests. * ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d, ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update for new stub hashes. * ld-arm/arm-elf.exp: Run them.	15 years ago
Richard Sandiford	35fc36a8d6	include/elf/ * internal.h (elf_internal_sym): Add st_target_internal. * arm.h (arm_st_branch_type): New enum. (ARM_SYM_BRANCH_TYPE): New macro. bfd/ * elf-bfd.h (elf_link_hash_entry): Add target_internal. * elf.c (swap_out_syms): Set st_target_internal for each Elf_Internal_Sym. * elfcode.h (elf_swap_symbol_in): Likewise. * elf32-i370.c (i370_elf_finish_dynamic_sections): Likewise. * elf32-sh-symbian.c (sh_symbian_relocate_section): Likewise. * elf64-sparc.c (elf64_sparc_output_arch_syms): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise. * elflink.c (elf_link_output_extsym): Likewise. (bfd_elf_final_link): Likewise. (elf_link_add_object_symbols): Copy st_target_internal to the hash table if we see a definition. (_bfd_elf_copy_link_hash_symbol_type): Copy target_internal. * elf32-arm.c (elf32_arm_stub_hash_entry): Replace st_type with a branch_type field. (a8_erratum_fix, a8_erratum_reloc): Likewise. (arm_type_of_stub): Replace actual_st_type with an actual_branch_type parameter. (arm_build_one_stub): Use branch types rather than st_types to determine the type of branch. (cortex_a8_erratum_scan): Likewise. (elf32_arm_size_stubs): Likewise. (bfd_elf32_arm_process_before_allocation): Likewise. (allocate_dynrelocs_for_symbol): Likewise. (elf32_arm_finish_dynamic_sections): Likewise. (elf32_arm_final_link_relocate): Replace sym_flags parameter with a branch_type parameter. (elf32_arm_relocate_section): Update call accordingly. (elf32_arm_adjust_dynamic_symbol): Don't check STT_ARM_TFUNC. (elf32_arm_output_map_sym): Initialize st_target_internal. (elf32_arm_output_stub_sym): Likewise. (elf32_arm_symbol_processing): Delete. (elf32_arm_swap_symbol_in): Convert STT_ARM_TFUNCs into STT_FUNCs. Use st_target_internal to record the branch type. (elf32_arm_swap_symbol_out): Use st_target_internal to test for Thumb functions. (elf32_arm_is_function_type): Delete. (elf_backend_symbol_processing): Likewise. (elf_backend_is_function_type): Likewise. gas/ * config/tc-arm.c (arm_adjust_symtab): Set the branch type for Thumb symbols. ld/ * emultempl/armelf.em (gld${EMULATION_NAME}_finish): Check eh->target_internal. opcodes/ * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC. Use branch types instead. (print_insn): Likewise.	15 years ago
Maciej W. Rozycki	0067d8fc73	opcodes/ * mips-opc.c (mips_builtin_opcodes): Correct register use annotation of "alnv.ps". gas/testsuite/ * gas/mips/alnv_ps-swap.d: New test for ALNV.PS instruction branch swapping. * gas/mips/alnv_ps-swap.s: Source for the new test. * gas/mips/mips.exp: Run the new test.	15 years ago
Maciej W. Rozycki	3eebd5eb03	gas/ * config/tc-mips.c (macro): Handle M_PREF_AB. include/opcode/ * mips.h (M_PREF_AB): New enum value. opcodes/ * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.	15 years ago
Maciej W. Rozycki	89c0d58cff	Swap ChangeLog entries.	15 years ago
Mike Frysinger	500cccad3b	opcodes: blackfin: drop null/nul checks in OUTS Parts of the disassembler rely on the disasm info never being NULL (such as being able to read memory to disassemble in the first place). So drop useless null checks in the OUTS helper. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Mike Frysinger	f5caf9f434	opcodes: blackfin: use OUTS helper We have an OUTS helper to handle outf fprintf_func logic, so conver the few places not using it over. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Mike Frysinger	e5bc42655d	opcodes: blackfin: clean up saved_state Mark the state static, punt unused members, unify indexable register lookups, and abort when there is a register lookup failure. Otherwise we return NULL and the calling code assumes a valid pointer is returned. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Mike Frysinger	602427c4af	opcodes: blackfin: fix style Non-functional thrashing to the GNU style. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Mike Frysinger	298c1ec2a0	opcodes: blackfin: catch invalid loopsetup insns The LoopSetup insn is only valid when the reg field is 0-7, so don't go decoding it incorrectly when reg is 8-15. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Ralf Wildenhues	822ce8ee21	Remove freebsd1 from libtool.m4 macros and config.rpath. /: Import from Libtool and gnulib: 2011-01-27 Gerald Pfeifer <gerald@pfeifer.com> Prepare for supporting FreeBSD 10. * config.rpath: Remove handling of freebsd1* which soon would match FreeBSD 10.0. 2011-01-20 Gerald Pfeifer <gerald@pfeifer.com> (tiny change) Remove support for FreeBSD 1.x. * libtool.m4 (_LT_LINKER_SHLIBS) (_LT_SYS_DYNAMIC_LINKER): Remove handling of freebsd1* which soon would incorrectly match FreeBSD 10.0. bfd/: * configure: Regenerate. gas/: * configure: Regenerate. ld/: * configure: Regenerate. opcodes/: * configure: Regenerate. binutils/: * configure: Regenerate. gprof/: * configure: Regenerate.	15 years ago
Mike Frysinger	13c02f06ff	opcodes: blackfin: fix decoding of ABS The single cycle dual mac ABS insn was incorrectly decoding the mac1 part of the insn. Once we fix the decode, update the gas tests to have the correct output. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Mike Frysinger	4db6639409	opcodes: blackfin: fix decoding of dsp mult insns When assigning to a register half, the mac0 part of the mult insn was not decoding properly. It would always show a full dreg instead of the dreg low half. Once we fix the disassembler, we have to update a few of the gas tests as their previous expected output was incorrect. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Mike Frysinger	36f446111a	gas/opcodes: blackfin: punt BYTEOP2M insn support The BYTEOP2M insn was part of the initial Blackfin designs, but never made it into any actual silicon. So punt support for it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Mike Frysinger	9805c0a5b6	opcodes: blackfin: add missing space after PRNT insn Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Mike Frysinger	43a6aa65fe	opcodes: blackfin: drop "GP" register There never was a "GP" register, so punt it from the decode map. It's a hold over from a very old processor definition and never made it into actual silicon. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Mike Frysinger	26bb3ddd50	gas/opcodes: blackfin: move dsp mac func defines to common header The mmod field is decoded in a few places (gas/opcodes/sim), so move it to a common place to avoid duplication. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Mike Frysinger	69b8ea4abd	opcodes: blackfin: constify register names Constify the array itself since it need not be writable. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	15 years ago
Michael Snyder	42d5f9c6ef	2011-02-09 Michael Snyder <msnyder@vmware.com> * i386-dis.c (OP_J): Parenthesize expression to prevent truncated addresses. (print_insn): Fix indentation off-by-one.	15 years ago
Nick Clifton	4be0c94123	Updated Danish translation.	15 years ago
Alan Modra	6b069ee70d	* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.	15 years ago
H.J. Lu	e3949f17f3	Properly sign-extend byte. gas/testsuite/ 2011-01-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/intel.d: Updated. * gas/i386/opcode-intel.d: Likewise. * gas/i386/opcode-suffix.d: Likewise. * gas/i386/opcode.d: Likewise. opcodes/ 2011-01-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (sIbT): New. (b_T_mode): Likewise. (dis386): Replace sIb with sIbT on "pushT". (x86_64_table): Replace sIb with Ib on "aam" and "aad". (OP_sI): Handle b_T_mode. Properly sign-extend byte.	15 years ago
Jan Kratochvil	752573b292	opcodes/ * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.	15 years ago
Quentin Neill	2a2a0f38e7	Add support for TBM instructions. gas/ 2011-01-17 Quentin Neill <quentin.neill@amd.com> * config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS. * doc/c-i386.texi (i386-TBM): New section. opcodes/ 2011-01-17 Quentin Neill <quentin.neill@amd.com> * i386-dis.c (REG_XOP_TBM_01): New. (REG_XOP_TBM_02): New. (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables. (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02 entries, and add bextr instruction. * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM. (cpu_flags): Add CpuTBM. * i386-opc.h (CpuTBM) New. (i386_cpu_flags): Add bit cputbm. * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk, blcs, blsfill, blsic, t1mskc, and tzmsk. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated gas/testsuite 2011-01-17 Quentin Neill <quentin.neill@amd.com> * gas/i386/tbm.s: New. * gas/i386/tbm.d: New. * gas/i386/tbm-intel.d: New. * gas/i386/x86-64-tbm.s: New. * gas/i386/x86-64-tbm.d: New. * gas/i386/x86-64-tbm-intel.d: New. * gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern. * gas/i386/arch-10.s: Add a TBM instruction. * gas/i386/arch-10-1.l: Add TBM instruction pattern. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-arch-2.d: Likewise.	15 years ago
DJ Delorie	90d6ff629e	* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.	15 years ago
Mingjie Xing	c95354ed13	Take unadjusted offset for loongson3a specific instructions.	15 years ago
Nick Clifton	f74656046a	* po/da.po: Updated Danish translation.	15 years ago
Nathan Sidwell	639e30d297	gas/testsuite/ * gas/arm/blx-bad.s: New. * gas/arm/blx-bad.d: New. opcodes/ * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.	15 years ago
H.J. Lu	f12dc42220	Implement BMI instructions.	15 years ago
H.J. Lu	cb21baef77	Add VexGdq. 2011-01-04 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (VexGdq): New. (OP_VEX): Handle dq_mode.	15 years ago
H.J. Lu	4fb3aee212	Update copyright in comments to 2011.	15 years ago
H.J. Lu	0db46eb403	Update copyright to 2011. binutils/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * version.c (print_version): Update copyright to 2011. gas/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * gas.c (parse_args): Update copyright to 2011. gold/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * version.cc (print_version): Update copyright to 2011. ld/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * ldver.c (ldversion): Update copyright to 2011. opcodes/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (process_copyright): Update copyright to 2011.	15 years ago
H.J. Lu	9e9e082043	Rotate binutils ChangeLogs.	15 years ago

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1811 Commits (d8b344530cba74a754ec101ccdd8869b3a48ec90)