binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Alan Modra	3f2a9fb79d	* hppa.h (completer_chars): #if 0 out.	24 years ago
Alan Modra	9bd1915f75	* ns32k.h (struct ns32k_opcode): Constify "name", "operands" and "default_args". (struct not_wot): Constify "args". (struct not): Constify "name". (numopcodes): Delete. (endop): Delete.	24 years ago
Alan Modra	0e073f4ce8	* pj.h (pj_opc_info_t): Add union. * pj-dis.c (print_insn_pj): Adjust for pj_opc_info_t change. * config/tc-pj.c (little, big, parse_exp_save_ilp): Prototype. (c_to_r, ipush_code, fake_opcode, alias): Likewise. (fake_opcode): Adjust for pj_opc_int_t change. (md_begin): Likewise. (md_assemble): Likewise. (ipush_code): Correct parse_exp_save_ilp call. Test pending_reloc instead of non-existent third arg of parse_exp_save_ilp. (md_parse_option): Correct "little" and "big" calls.	24 years ago
Jim Wilson	c10d9d8fc3	Patch to update IA-64 port to SDM 2.1. bfd/ChangeLog * cpu-ia64-opc.c: Add operand constant "ar.csd". gas/ChangeLog * config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint" instruction. (emit_one_bundle): Handle "hint" instruction. (operand_match): Match IA64_OPND_AR_CSD. gas/testsuite/ChangeLog * gas/ia64/opc-b.d: Update for instructions added by SDM2.1. * gas/ia64/opc-b.s: Ditto. * gas/ia64/opc-f.d: Ditto. * gas/ia64/opc-f.s: Ditto. * gas/ia64/opc-i.d: Ditto. * gas/ia64/opc-i.s: Ditto. * gas/ia64/opc-m.d: Ditto. * gas/ia64/opc-m.s: Ditto. * gas/ia64/opc-x.d: Ditto. * gas/ia64/opc-x.s: Ditto. include/opcode/ChangeLog * ia64.h: Fix copyright message. (IA64_OPND_AR_CSD): New operand kind. opcodes/ChangeLog * ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction. * ia64-opc-b.c: Add "hint.b" instruction. * ia64-opc-f.c: Add "hint.f" instruction. * ia64-opc-i.c: Add "hint.i" instruction. * ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and "cmp8xchg16" instructions. * ia64-opc-x.c: Add "hint.x" instruction. * ia64-opc.h (AR_CSD): New macro. * ia64-ic.tbl: Update according to SDM2.1. * ia64-raw.tbl: Ditto. * ia64-waw.tbl: Ditto. * ia64-gen.c (in_iclass): Handle "hint" like "nop". (lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD], AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR]. * ia64-asmtab.c: Regenerate.	24 years ago
Richard Henderson	a823923bf6	include/opcode/ * ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV. bfd/ * cpu-ia64-opc.c (elf64_ia64_operands): Add ldxmov entry. opcodes/ * ia64-opc-m.c: Add ld8.mov. * ia64-asmtab.c: Regenerate. gas/ * config/tc-ia64.c (operand_match): Add IA64_OPND_LDXMOV case. gas/testsuite/ * gas/ia64/ldxmov-1.[ds]: New. * gas/ia64/ldxmov-2.[ls]: New. * gas/ia64/ia64.exp: Run them.	24 years ago
Alan Modra	4fdf0a751a	* cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union. Constify "leaf" and "multi".	24 years ago
Klee Dienes	53cc279128	2002-11-19 Klee Dienes <kdienes@apple.com> * h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size' fields. (h8_opcodes). Modify initializer and initializer macros to no longer initialize the removed fields.	24 years ago
Svein Seldal	5dec918223	Fixed LDHI constraint	24 years ago
Klee Dienes	a3e64b75ca	2002-11-11 Klee Dienes <kdienes@apple.com> * h8300.h (h8_opcode): Remove 'length' field. (h8_opcodes): Mark as 'const' (both the declaration and definition). Modify initializer and initializer macros to no longer initialize the length field. 2002-11-11 Klee Dienes <kdienes@apple.com> * h8300-dis.c: Include libiberty.h (for xmalloc). (struct h8_instruction): New type, used to wrap h8_opcodes with a length field (computed at run-time). (h8_instructions): New variable. (bfd_h8_disassemble_init): Allocate the storage for h8_instructions. Fill h8_instructions with pointers to the appropriate opcode and the correct value for the length field. (bfd_h8_disassemble): Iterate through h8_instructions instead of h8_opcodes.	24 years ago
Klee Dienes	84037f8c66	2002-11-18 Klee Dienes <kdienes@apple.com> * arc.h (arc_ext_opcodes): Declare as extern. (arc_ext_operands): Declare as extern. * i860.h (i860_opcodes): Declare as const. 2002-11-18 Klee Dienes <kdienes@apple.com> * arc-opc.c (arc_ext_opcodes): Define. (arc_ext_operands): Define. * i386-dis.c (Suffix3DNow): Declare as const. * arm-opc.h (arm_opcodes): Declare as const. (thumb_opcodes): Declare as const. * h8500-opc.h (h8500_table): Declare as const. (h8500_table): Use a NULL for the opcode in the terminator, so that code testing (opcode->name) behaves correctly. * mcore-opc.h (mcore_table): Declare as const. * sh-opc.h (sh_table): Declare as const. * w65-opc.h (optable): Declare as const. * z8k-opc.h (z8k_table): Declare as const.	24 years ago
Svein Seldal	eb1284494b	Fixups in ChangeLog entries which has been filed in the wrong place.	24 years ago
Svein Seldal	9c87d6c7e4	* gas/config/tc-tic4x.c: Fixed proper commandline	24 years ago
Klee Dienes	5934e39b3d	2002-11-16 Klee Dienes <kdienes@apple.com> * opcode/m88k.h (INSTAB): Remove 'next' field. (instruction): Remove definition; replace with extern declaration and mark as const. W	24 years ago
Svein Seldal	44287f6039	* gas/config/tc-tic4x.c: Remove c4x_pseudo_ignore function.	24 years ago
Svein Seldal	247b1fe610	gas tic4x target enhancements (long list - see gas/ChangeLog and	24 years ago
Alan Modra	ea6a213a6f	* cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE.	24 years ago
Richard Sandiford	701b80cd66	Fix date in last commit.	24 years ago
Richard Sandiford	9752cf1b67	[include/opcode/] * mips.h: Update comment for new opcodes. (OP_MASK_VECBYTE, OP_SH_VECBYTE): New. (OP_MASK_VECALIGN, OP_SH_VECALIGN): New. (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New. (CPU_VR4120, CPU_VR5400, CPU_VR5500): New. (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags. Don't match CPU_R4111 with INSN_4100. [opcodes/] * mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'. (mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400 and bfd_mach_mips5500. * mips-opc.c (V1): Include INSN_4111 and INSN_4120. (N411, N412, N5, N54, N55): New convenience defines. (mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes. Change dmadd16 and madd16 from V1 to N411.	24 years ago
Nick Clifton	026df7c5e6	Add TMS320C4x support	24 years ago
Elena Zannoni	0449635dbd	2002-08-19 Elena Zannoni <ezannoni@redhat.com> From matthew green <mrg@redhat.com> * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500 instructions. (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR, PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the e500x2 Integer select, branch locking, performance monitor, cache locking and machine check APUs, respectively. (PPC_OPCODE_EFS): New opcode type for efs* instructions. (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.	24 years ago
Stephane Carrez	030ad53bf6	* m68hc11.h (M6812_OP_PAGE): Define to identify call operand. (M68HC12_BANK_VIRT, M68HC12_BANK_MASK, M68HC12_BANK_BASE, M68HC12_BANK_SHIFT, M68HC12_BANK_PAGE_MASK): Define for 68HC12 memory banks. (M6811_OC1M5, M6811_OC1M4, M6811_MODF): Fix value.	24 years ago
Richard Sandiford	2061187ab5	* opcode/mips.h (CPU_R2000): Remove.	24 years ago
Thiemo Seufer	aec421e08b	* config/tc-mips.c (macro_build): Handle MIPS16 insns. (mips_ip): Likewise. * mips.h (INSN_MIPS16): New define. * mips-dis.c (mips_isa_type): Add MIPS16 insn handling. * mips-opc.c (I16): New define. (mips_builtin_opcodes): Make jalx an I16 insn.	24 years ago
Alan Modra	cd61ebfe13	gas/ChangeLog * config/tc-i386.c (process_suffix): Remove intel mode movsx and movzx fudges. (md_assemble): Instead, zap the suffix here. include/opcode/ChangeLog * i386.h: Remove IgnoreSize from movsx and movzx.	24 years ago
Alan Modra	92007e403c	* a29k.h: Replace CONST with const. (CONST): Don't define. * convex.h: Replace CONST with const. (CONST): Don't define. * dlx.h: Replace CONST with const. * or32.h (CONST): Don't define.	25 years ago
Chris Demetriou	deec17343c	[ gas/ChangeLog ] 2002-05-30 Chris G. Demetriou <cgd@broadcom.com> Ed Satterthwaite <ehs@broadcom.com> * config/tc-mips.c (mips_set_options): New "ase_mdmx" member. (mips_opts): Initialize "ase_mdmx" member. (file_ase_mdmx): New variable. (CPU_HAS_MDMX): New macro. (md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx based on command line options and configuration defaults. (macro_build): Note in comment that use of MDMX in macros is not currently allowed. (validate_mips_insn): Add support for the "O", "Q", "X", "Y", and "Z" MDMX operand types. (mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set, and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand types. (OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option): Add support for "-mdmx" and "-no-mdmx" options. (OPTION_ELF_BASE): Move to accomodate new options. (s_mipsset): Support ".set mdmx" and ".set nomdmx". (mips_elf_final_processing): Set MDMX ASE ELF header flag if file_ase_mdmx was set. * doc/as.texinfo: Document -mdmx and -no-mdmx options. * doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set nomdmx" directives. [ gas/testsuite/ChangeLog ] 2002-05-30 Chris G. Demetriou <cgd@broadcom.com> * gas/mips/mips64-mdmx.s: New file. * gas/mips/mips64-mdmx.d: Likewise. * gas/mips/mips.exp: Run new "mips64-mdmx" test. [ include/opcode/ChangeLog ] 2002-05-30 Chris G. Demetriou <cgd@broadcom.com> * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL) (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH) (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC) (INSN_MDMX): New constants, for MDMX support. (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX. [ opcodes/ChangeLog ] 2002-05-30 Chris G. Demetriou <cgd@broadcom.com> Ed Satterthwaite <ehs@broadcom.com> * mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y', and 'Z' formats, for MDMX. (mips_isa_type): Add MDMX instructions to the ISA bit mask for bfd_mach_mipsisa64. * mips-opc.c: Add support for MDMX instructions. (MX): New definition. * mips-dis.c: Update copyright years to include 2002.	25 years ago
Nick Clifton	d172d4ba03	Add DLX target	25 years ago
Alan Modra	b3f7d5fdb0	* ia64.h: Use #include "" instead of <> for local header files. * sparc.h: Likewise.	25 years ago
Thiemo Seufer	771c7ce4bc	? gas/testsuite/gas/mips/rol64.d ? gas/testsuite/gas/mips/rol64.s Index: gas/ChangeLog =================================================================== RCS file: /cvs/src/src/gas/ChangeLog,v retrieving revision 1.1334 diff -u -p -r1.1334 ChangeLog --- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334 +++ gas/ChangeLog 21 May 2002 23:32:51 -0000 @@ -1,3 +1,8 @@ +2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * config/tc-mips.c (macro2): Add 64 bit drol, dror macros. + Optimize the rotate by zero case. + 2002-05-21 Nick Clifton <nickc@cambridge.redhat.com> * configure.in: Remove accidental enabling of bfd_gas=yes for Index: gas/config/tc-mips.c =================================================================== RCS file: /cvs/src/src/gas/config/tc-mips.c,v retrieving revision 1.123 diff -u -p -r1.123 tc-mips.c --- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123 +++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000 @@ -6686,6 +6686,17 @@ macro2 (ip) --mips_opts.noreorder; break; + case M_DROL: + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "dsubu", + "d,v,t", AT, 0, treg); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "dsrlv", + "d,t,s", AT, sreg, AT); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "dsllv", + "d,t,s", dreg, sreg, treg); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", + "d,v,t", dreg, dreg, AT); + break; + case M_ROL: macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "subu", "d,v,t", AT, 0, treg); @@ -6697,15 +6708,55 @@ macro2 (ip) "d,v,t", dreg, dreg, AT); break; + case M_DROL_I: + { + unsigned int rot; + char l, r; + + if (imm_expr.X_op != O_constant) + as_bad (_("rotate count too large")); + rot = imm_expr.X_add_number & 0x3f; + if (! rot) + break; + l = (rot < 0x20) ? "dsll" : "dsll32"; + r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; + rot &= 0x1f; + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, l, + "d,w,<", AT, sreg, rot); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, r, + "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", + "d,v,t", dreg, dreg, AT); + } + break; + case M_ROL_I: - if (imm_expr.X_op != O_constant) - as_bad (_("rotate count too large")); - macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "sll", "d,w,<", - AT, sreg, (int) (imm_expr.X_add_number & 0x1f)); - macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "srl", "d,w,<", - dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f)); - macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", "d,v,t", - dreg, dreg, AT); + { + unsigned int rot; + + if (imm_expr.X_op != O_constant) + as_bad (_("rotate count too large")); + rot = imm_expr.X_add_number & 0x1f; + if (! rot) + break; + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "sll", + "d,w,<", AT, sreg, rot); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "srl", + "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", + "d,v,t", dreg, dreg, AT); + } + break; + + case M_DROR: + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "dsubu", + "d,v,t", AT, 0, treg); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "dsllv", + "d,t,s", AT, sreg, AT); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "dsrlv", + "d,t,s", dreg, sreg, treg); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", + "d,v,t", dreg, dreg, AT); break; case M_ROR: @@ -6719,15 +6770,44 @@ macro2 (ip) "d,v,t", dreg, dreg, AT); break; + case M_DROR_I: + { + unsigned int rot; + char l, r; + + if (imm_expr.X_op != O_constant) + as_bad (_("rotate count too large")); + rot = imm_expr.X_add_number & 0x3f; + if (! rot) + break; + r = (rot < 0x20) ? "dsrl" : "dsrl32"; + l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; + rot &= 0x1f; + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, r, + "d,w,<", AT, sreg, rot); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, l, + "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", + "d,v,t", dreg, dreg, AT); + } + break; + case M_ROR_I: - if (imm_expr.X_op != O_constant) - as_bad (_("rotate count too large")); - macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "srl", "d,w,<", - AT, sreg, (int) (imm_expr.X_add_number & 0x1f)); - macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "sll", "d,w,<", - dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f)); - macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", "d,v,t", - dreg, dreg, AT); + { + unsigned int rot; + + if (imm_expr.X_op != O_constant) + as_bad (_("rotate count too large")); + rot = imm_expr.X_add_number & 0x1f; + if (! rot) + break; + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "srl", + "d,w,<", AT, sreg, rot); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "sll", + "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", + "d,v,t", dreg, dreg, AT); + } break; case M_S_DOB: Index: gas/testsuite/ChangeLog =================================================================== RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v retrieving revision 1.315 diff -u -p -r1.315 ChangeLog --- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315 +++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000 @@ -1,3 +1,9 @@ +2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * gas/mips/rol64.s: New file, test of drol, dror macros. + * gas/mips/rol64.d: Likewise. + * gas/mips/mips.exp: Add new test. + 2002-05-20 Nick Clifton <nickc@cambridge.redhat.com> * gas/arm/arm.exp: Replace deprecated command line switches Index: gas/testsuite/gas/mips/mips.exp =================================================================== RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v retrieving revision 1.32 diff -u -p -r1.32 mips.exp --- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32 +++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000 @@ -122,6 +122,7 @@ if { [istarget mips--] } then { run_dump_test "mul" } run_dump_test "rol" + run_dump_test "rol64" if !$aout { run_dump_test "sb" } run_dump_test "trunc" if !$aout { run_dump_test "ulh" } Index: include/opcode/ChangeLog =================================================================== RCS file: /cvs/src/src/include/opcode/ChangeLog,v retrieving revision 1.167 diff -u -p -r1.167 ChangeLog --- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167 +++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000 @@ -1,3 +1,7 @@ +2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases. + 2002-05-17 Andrey Volkov <avolkov@sources.redhat.com> * h8300.h: Corrected defs of all control regs Index: include/opcode/mips.h =================================================================== RCS file: /cvs/src/src/include/opcode/mips.h,v retrieving revision 1.24 diff -u -p -r1.24 mips.h --- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24 +++ include/opcode/mips.h 21 May 2002 23:32:57 -0000 @@ -526,9 +526,13 @@ enum M_REM_3I, M_REMU_3, M_REMU_3I, + M_DROL, M_ROL, + M_DROL_I, M_ROL_I, + M_DROR, M_ROR, + M_DROR_I, M_ROR_I, M_S_DA, M_S_DOB, Index: opcodes/ChangeLog =================================================================== RCS file: /cvs/src/src/opcodes/ChangeLog,v retrieving revision 1.447 diff -u -p -r1.447 ChangeLog --- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447 +++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000 @@ -1,3 +1,7 @@ +2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros. + Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com> * disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh. Index: opcodes/mips-opc.c =================================================================== RCS file: /cvs/src/src/opcodes/mips-opc.c,v retrieving revision 1.32 diff -u -p -r1.32 mips-opc.c --- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32 +++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000 @@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s\|RD_t\|WR_HILO, I3 }, {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 }, {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 }, +{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 }, +{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 }, +{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 }, +{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 }, {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d\|RD_t\|RD_s, I3 }, {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d\|RD_t, I3 }, {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d\|RD_t\|RD_s, I3 }, /* dsllv */	25 years ago
Andrey Volkov	b9c9142c40	* h8300.h: Corrected defs of all control regs and eepmov instr.	25 years ago
Alan Modra	b9612d142d	reorder cmpsd, movsd	25 years ago
Alan Modra	cd47f4f16f	* i386.h: Add intel mode cmpsd and movsd.	25 years ago
Chris Demetriou	1f25f5d300	[ gas/ChangeLog ] 2002-03-15 Chris G. Demetriou <cgd@broadcom.com> * config/tc-mips.c (mips_set_options): New "ase_mips3d" member. (mips_opts): Initialize "ase_mips3d" member. (file_ase_mips3d): New variable. (CPU_HAS_MIPS3D): New macro. (md_begin): Initialize mips_opts.ase_mips3d and file_ase_mips3d based on command line options and configuration defaults. (macro_build, mips_ip): Accept MIPS-3D instructions if mips_opts.ase_mips3d is set. (OPTION_MIPS3D, OPTION_NO_MIPS3D, md_longopts, md_parse_option): Add support for "-mips3d" and "-no-mips3d" options. (OPTION_ELF_BASE): Move to accomodate new options. (s_mipsset): Support ".set mips3d" and ".set nomips3d". (mips_elf_final_processing): Add a comment indicating that a MIPS-3D ASE ELF header flag should be set, when one exists. * doc/as.texinfo: Document -mips3d and -no-mips3d options. * doc/c-mips.texi: Likewise, and document ".set mips3d" and ".set nomips3d" directives. [ gas/testsuite/ChangeLog ] 2002-03-15 Chris G. Demetriou <cgd@broadcom.com> * gas/mips/mips64-mips3d.s: New file. * gas/mips/mips64-mips3d.d: Likewise. * gas/mips/mips.exp: Run new "mips64-mips3d" test. [ include/opcode/ChangeLog ] 2002-03-15 Chris G. Demetriou <cgd@broadcom.com> * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D instructions. (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks may be passed along with the ISA bitmask. [ opcodes/ChangeLog ] 2002-03-15 Chris G. Demetriou <cgd@broadcom.com> * mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64. Add comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that indicate that they should dissassemble all applicable MIPS-specified ASEs. * mips-opc.c: Add support for MIPS-3D instructions. (M3D): New definition. * mips-opc.c: Update copyright years.	25 years ago
Alan Modra	e4b29ec6bd	* pdp11.h: Add format codes for float instruction formats.	25 years ago
Alan Modra	eea5c83f2f	missdit	25 years ago
Alan Modra	fc1e712166	* ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define.	25 years ago
Jan Hubicka	5a8b245cb6	* i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands.	25 years ago
Jan Hubicka	85a33fe281	* i386.h (push,pop): Allow 16bit operands in 64bit mode. (xchg): Fix. (in, out): Disable 64bit operands. (call, jmp): Avoid REX prefixes. (jcxz): Prohibit in 64bit mode (jrcxz, loop): Add 64bit variants. (movq): Fix patterns. (movmskps, pextrw, pinstrw): Add 64bit variants.	25 years ago
Nick Clifton	3b16e843f2	Add support for OpenRISC 32-bit embedded processor	25 years ago
David O'Brien	569719c11a	2002-01-27 David O'Brien <obrien@FreeBSD.org> * cgen.h (BFD_VERSION): Use BFD_VERSION_DATE instead. Approved by: Nick Clifton <nickc@cambridge.redhat.com> <m3k7u2g5uc.fsf@north-pole.nickc.cambridge.redhat.com>	25 years ago
Graydon Hoare	9a2e995d8a	[ include/opcode/ChangeLog ] 2002-01-22 Graydon Hoare <graydon@redhat.com> * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure. (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field. [ opcodes/ChangeLog ] 2002-01-22 Graydon Hoare <graydon@redhat.com> * fr30-asm.c: Regenerate. * fr30-desc.c: Likewise. * fr30-desc.h: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * fr30-opc.c: Likewise. * fr30-opc.h: Likewise. * m32r-asm.c: Likewise. * m32r-desc.c: Likewise. * m32r-desc.h: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * m32r-opc.c: Likewise. * m32r-opc.h: Likewise. * m32r-opinst.c: Likewise. * openrisc-asm.c: Likewise. * openrisc-desc.c: Likewise. * openrisc-desc.h: Likewise. * openrisc-dis.c: Likewise. * openrisc-ibld.c: Likewise. * openrisc-opc.c: Likewise. * openrisc-opc.h: Likewise. * xstormy16-desc.c: Likewise. [ cgen/ChangeLog ] 2002-01-22 Graydon Hoare <graydon@redhat.com> * desc-cpu.scm (ifld-number-cache): Add. (ifld-number): Add. (gen-maybe-multi-ifld-of-op): Add. (gen-maybe-multi-ifld): Add. (gen-multi-ifield-nodes): Add. (cgen-desc.c): Add call to gen-multi-ifield-nodes.	25 years ago
Alan Modra	7b45c6e1da	comment typo fixes	25 years ago
Matthew Green	a09cf9bd77	[gas/ChangeLog] * config/tc-ppc.c (md_parse_option): BookE is not Motorola specific. [include/opcode/ChangeLog] * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific. (PPC_OPCODE_BOOKE64): Likewise.	25 years ago
Jeff Law	1befefea7e	* hppa.h (call, ret): Move to end of table. (addb, addib): PA2.0 variants should have been PA2.0W. (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler happy. (fldw, fldd, fstw, fstd, bb): Likewise. (short loads/stores): Tweak format specifier slightly to keep disassembler happy. (indexed loads/stores): Likewise. (absolute loads/stores): Likewise.	25 years ago
Alexandre Oliva	124ddbb22f	* d10v.h (OPERAND_NOSP): New macro.	25 years ago
Alexandre Oliva	bf9043c5c7	Copyright 2001	25 years ago
Alexandre Oliva	9b21d49b4a	* d10v.h (OPERAND_SP): New macro.	25 years ago
Alan Modra	802a735ed9	binutils/ChangeLog * doc/binutils.texi (objdump): Document ppc -M options. gas/ChangeLog * config/tc-ppc.c (ppc_insert_operand): Pass (ppc_cpu \| ppc_size) to operand->insert. (md_assemble): Likewise. gas/testsuite/ChangeLog * gas/ppc/booke.d: Modify reloc and target matches for powerpc64. include/opcode/ChangeLog * ppc.h (struct powerpc_operand <insert, extract>): Add dialect param. opcodes/ChangeLog * ppc-opc.c (PPC64): Revert 2001-10-12. Do include PPC_OPCODE_PPC. (insert_bat, extract_bat, insert_bba, extract_bba, insert_bd, extract_bd, insert_bdm, extract_bdm, insert_bdp, extract_bdp, valid_bo, insert_bo, extract_bo, insert_boe, extract_boe, insert_ds, extract_ds, insert_de, extract_de, insert_des, extract_des, insert_li, extract_li, insert_mbe, extract_mbe, insert_mb6, extract_mb6, insert_nb, extract_nb, insert_nsi, extract_nsi, insert_ral, insert_ram, insert_ras, insert_rbs, extract_rbs, insert_sh6, extract_sh6, insert_spr, extract_spr, insert_tbr, extract_tbr): Add dialect param. (extract_bd, extract_bdm, extract_bdp, extract_ds, extract_des, extract_li, extract_nsi): Implement sign extension without conditional. (insert_bdm, extract_bdm, insert_bdp, extract_bdp, valid_bo): Handle 64 bit branch hints. (extract_bdm, extract_bdp): Correct 32 bit validation. (AT1_MASK, AT2_MASK): Define. (BBOAT_MASK): Define. (BBOATCB_MASK, BBOAT2CB_MASK, BBOATBI_MASK): Define. (BOFM64, BOFP64, BOTM64, BOTP64): Define. (BODNZM64, BODNZP64, BODZM64, BODZP64): Define. (PPCCOM32, PPCCOM64): Define. (powerpc_opcodes): Modify existing 32 bit insns with branch hints and add new patterns to implement 64 bit branches with hints. Move booke instructions so they match before ppc64. * ppc-dis.c (powerpc_dialect): Set PPC_OPCODE_64 in dialect for 64 bit default targets, and parse "32" and "64" in options. Formatting fixes. (print_insn_powerpc): Pass dialect to operand->extract.	25 years ago
Timothy Wall	6e91790347	Fix tic54x testsuite failures and Lmem disassembly bugs.	25 years ago
Alan Modra	e5470cdc92	* i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to accept WordReg. * i386-dis.c (grps): Change "sldt", "str", and "smsw" entries to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand category instead of Ew.	25 years ago

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211 Commits (d0fe2f7e746923b38bffd2578fa58e7ea8468461)