binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Alan Modra	a2c5833233	Update year range in copyright notice of binutils files The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out /po/.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.	4 years ago
Alan Modra	250d07de5c	Update year range in copyright notice of binutils files	5 years ago
Alan Modra	b3adc24a07	Update year range in copyright notice of binutils files	6 years ago
Alan Modra	827041555a	Update year range in copyright notice of binutils files	7 years ago
Alan Modra	219d1afa89	Update year range in copyright notice of binutils files	8 years ago
Jose E. Marchesi	6451799480	binutils: support for the SPARC M8 processor This patch adds support for the new SPARC M8 processor (implementing OSA 2017) to binutils. New instructions: - Dictionary Unpack + dictunpack - Partitioned Compare with shifted result + Signed variants: fpcmp{le,gt,eq,ne}{8,16,32}shl + Unsigned variants: fpcmpu{le,gt}{8,16,32}shl - Partitioned Dual-Equal compared, with shifted result + fpcmpde{8,16,32}shl - Partitioned Unsigned Range Compare, with shifted result + fpcmpur{8,16,32}shl - 64-bit shifts on Floating-Point registers + fps{ll,ra,rl}64x - Misaligned loads and stores + ldm{sh,uh,sw,uw,x,ux} + ldm{sh,uh,sw,uw,x,ux}a + ldmf{s,d} + ldmf{s,d}a + stm{h,w,x} + stm{h,w,x}a + stmf{s,d} + stmf{s,d}a - Oracle Numbers + on{add,sub,mul,div} - Reverse Bytes/Bits + revbitsb + revbytes{h,w,x} - Run-Length instructions + rle_burst + rle_length - New crypto instructions + sha3 - Instruction to read the new register %entropy + rd %entropy New Alternate Address Identifiers: - 0x24, #ASI_CORE_COMMIT_COUNT - 0x24, #ASI_CORE_SELECT_COUNT - 0x48, #ASI_ARF_ECC_REG - 0x53, #ASI_ITLB_PROBE - 0x58, #ASI_DSFAR - 0x5a, #ASI_DTLB_PROBE_PRIMARY - 0x5b, #ASI_DTLB_PROBE_REAL - 0x64, #ASI_CORE_SELECT_COMMIT_NHT The new assembler command-line options for selecting the M8 architecture are: -Av9m8 or -Asparc6 for 64-bit binaries. -Av8plusm8 for 32-bit (v8+) binaries. The corresponding disassembler command-line options are: -msparc:v9m8 for 64-bit binaries. -msparc:v8plusm8 for 32-bit (v8+) binaries. Tested for regressions in the following targets: sparc-aout sparc-linux sparc-vxworks sparc64-linux bfd/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * archures.c (bfd_mach_sparc_v9m8): Define. (bfd_mach_sparc_v8plusm8): Likewise. (bfd_mach_sparc_v9_p): Adjust to M8. (bfd_mach_sparc_64bit_p): Likewise. * aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and bfd_mach_sparc_v8plusm8. * bfd-in2.h: Regenerated. * cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and sparc:v8plusm8. * elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and SHA3. * elf32-sparc.c (elf32_sparc_final_write_processing): Handle bfd_mach_sparc_v8plusm8. binutils/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * NEWS: Mention the SPARC M8 support. gas/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_arch_table): Entries for `sparc6', `v9m8' and `v8plusm8'. (sparc_md_end): Handle SPARC_OPCODE_ARCH_M8. (get_hwcap_name): Support the M8 hardware capabilities. (sparc_ip): Handle new operand types. * doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and -Asparc6, and the corresponding -xarch aliases. * testsuite/gas/sparc/sparc6.s: New file. * testsuite/gas/sparc/sparc6.d: Likewise. * testsuite/gas/sparc/sparc6-diag.s: Likewise. * testsuite/gas/sparc/sparc6-diag.l: Likewise. * testsuite/gas/sparc/fpcmpshl.s: Likewise. * testsuite/gas/sparc/fpcmpshl.d: Likewise. * testsuite/gas/sparc/fpcmpshl-diag.s: Likewise. * testsuite/gas/sparc/fpcmpshl-diag.l: Likewise. * testsuite/gas/sparc/ldm-stm.s: Likewise. * testsuite/gas/sparc/ldm-stm.d: Likewise. * testsuite/gas/sparc/ldm-stm-diag.s: Likewise. * testsuite/gas/sparc/ldm-stm-diag.l: Likewise. * testsuite/gas/sparc/ldmf-stmf.s: Likewise. * testsuite/gas/sparc/ldmf-stmf.d: Likewise. * testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise. * testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise. * testsuite/gas/sparc/on.s: Likewise. * testsuite/gas/sparc/on.d: Likewise. * testsuite/gas/sparc/on-diag.s: Likewise. * testsuite/gas/sparc/on-diag.l: Likewise. * testsuite/gas/sparc/rle.s: Likewise. * testsuite/gas/sparc/rle.d: Likewise. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests. * testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY. * testsuite/gas/sparc/rdasr.d: Likewise. include/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define. (ELF_SPARC_HWCAP2_ONADDSUB): Likewise. (ELF_SPARC_HWCAP2_ONMUL): Likewise. (ELF_SPARC_HWCAP2_ONDIV): Likewise. (ELF_SPARC_HWCAP2_DICTUNP): Likewise. (ELF_SPARC_HWCAP2_FPCMPSHL): Likewise. (ELF_SPARC_HWCAP2_RLE): Likewise. (ELF_SPARC_HWCAP2_SHA3): Likewise. * opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8 and adjust SPARC_OPCODE_ARCH_MAX. (HWCAP2_SPARC6): Define. (HWCAP2_ONADDSUB): Likewise. (HWCAP2_ONMUL): Likewise. (HWCAP2_ONDIV): Likewise. (HWCAP2_DICTUNP): Likewise. (HWCAP2_FPCMPSHL): Likewise. (HWCAP2_RLE): Likewise. (HWCAP2_SHA3): Likewise. (OPM): Likewise. (OPMI): Likewise. (ONFCN): Likewise. (REVFCN): Likewise. (SIMM10): Likewise. opcodes/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8. (X_IMM2): Define. (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8. (print_insn_sparc): Handle new operand types. * sparc-opc.c (MASK_M8): Define. (v6): Add MASK_M8. (v6notlet): Likewise. (v7): Likewise. (v8): Likewise. (v9): Likewise. (v9a): Likewise. (v9b): Likewise. (v9c): Likewise. (v9d): Likewise. (v9e): Likewise. (v9v): Likewise. (v9m): Likewise. (v9andleon): Likewise. (m8): Define. (HWS_VM8): Define. (HWS2_VM8): Likewise. (sparc_opcode_archs): Add entry for "m8". (sparc_opcodes): Add OSA2017 and M8 instructions dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl, fpx{ll,ra,rl}64x, ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d}, ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb, revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x}, stm{h,w,x}a, stmf{s,d}, stmf{s,d}a. (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT, ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR, ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL, ASI_CORE_SELECT_COMMIT_NHT.	9 years ago
Sheldon Lobo	1e9d41d49f	opcodes,gas: associate SPARC ASIs with an architecture level. With this change an architecture level bump due to assembly ASIs will show up as a warning/error depending on options passed to gas. Tested with sparc64-linux-gnu, and it does not introduce any regressions. gas/ChangeLog: Add support for associating SPARC ASIs with an architecture level. * config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs. opcodes/ChangeLog: Add support for associating SPARC ASIs with an architecture level. * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ decoding of SPARC ASIs.	9 years ago
Alan Modra	2571583aed	Update year range in copyright notice of all files.	9 years ago
Jose E. Marchesi	6884417a0f	gas,opcodes: fix hardware capabilities bumping in the sparc assembler. When the assembler finds an instruction which is part of a higher opcode architecture it bumps the current opcode architecture. For example: $ echo "mwait" \| as -bump {standard input}: Assembler messages: {standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait" However, when two instructions pertaining to the same opcode architecture but associated to different SPARC hardware capabilities are found in the input stream, and no GAS architecture is specified in the command line, the assembler bangs: $ echo "mwait; wr %g0,%g1,%mcdper" \| as -bump {standard input}: Assembler messages: {standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait" {standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr". ... and it should'nt, as WRMCDPER pertains to the same architecture level than MWAIT. This patch fixes this by extending the definition of sparc opcode architectures to contain a set of hardware capabilities and making the assembler to take these capabilities into account when updating the set of allowed hwcaps when an architecture bump is triggered by some instruction. This way, hwcaps associated to architecture levels are maintained in opcodes, while the assembler keeps the flexibiity of defining GAS architectures including additional hwcaps (like -Asparcfmaf or the v8plus* variants). A test covering this failure case is included. gas/ChangeLog: 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c: Move HWS_* and HWS2_* definitions to opcodes/sparc-opc.c. (sparc_arch): Clarify the new role of the hwcap_allowed and hwcap2_allowed fields. (sparc_arch_table): Remove HWS_* and HWS2_* instances from hwcap_allowed and hwcap2_allowed respectively. (md_parse_option): Include the opcode arch hwcaps when processing -A. (sparc_ip): Use the current opcode arch hwcaps to update hwcap_allowed, as well of the hwcaps of the instruction triggering the bump. * testsuite/gas/sparc/hwcaps-bump.s: New file. * testsuite/gas/sparc/hwcaps-bump.l: Likewise. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in hwcaps-bump. include/ChangeLog: 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and hwcaps2. opcodes/ChangeLog: 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (HWS_V8): Definition moved from gas/config/tc-sparc.c. (HWS_V9): Likewise. (HWS_VA): Likewise. (HWS_VB): Likewise. (HWS_VC): Likewise. (HWS_VD): Likewise. (HWS_VE): Likewise. (HWS_VV): Likewise. (HWS_VM): Likewise. (HWS2_VM): Likewise. (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of existing entries.	10 years ago
Trevor Saunders	042c94de56	sparc: make SPARC_OPCODE_ARCH_MAX part of its enum include/ChangeLog: 2016-06-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * opcode/sparc.h (enum sparc_opcode_arch_val): Move SPARC_OPCODE_ARCH_MAX into the enum.	10 years ago
Jose E. Marchesi	4f26fb3a1b	bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers. This patch adds support for the opcode architectures SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}. Note that for arches up to v9b (UltraSPARC III), the detection of the BFD machine type was based on the bits in the e_machine field of the ELF header. However, there are no more available bits in that field, so this patch takes the approach of using the hardware capabilities stored in the object attributes HWCAPS/HWCAPS2 in order to characterize the machine the object was built for. bfd/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * archures.c (bfd_mach_sparc_v8plusc): Define. (bfd_mach_sparc_v9c): Likewise. (bfd_mach_sparc_v8plusd): Likewise. (bfd_mach_sparc_v9d): Likewise. (bfd_mach_sparc_v8pluse): Likewise. (bfd_mach_sparc_v9e): Likewise. (bfd_mach_sparc_v8plusv): Likewise (bfd_mach_sparc_v9v): Likewise. (bfd_mach_sparc_v8plusm): Likewise. (bfd_mach_sparc_v9m): Likewise. (bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m. (bfd_mach_sparc_64bit_p): Likewise. * bfd-in2.h: Regenerate. * cpu-sparc.c (arch_info_struct): Add entries for bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}. * aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}. * elf32-sparc.c (elf32_sparc_final_write_processing): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise. include/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D, SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and SPARC_OPCODE_ARCH_V9M. opcodes/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}. (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}. * sparc-opc.c (MASK_V9C): Define. (MASK_V9D): Likewise. (MASK_V9E): Likewise. (MASK_V9V): Likewise. (MASK_V9M): Likewise. (v6): Add MASK_V9{C,D,E,V,M}. (v6notlet): Likewise. (v7): Likewise. (v8): Likewise. (v9): Likewise. (v9andleon): Likewise. (v9a): Likewise. (v9b): Likewise. (v9c): Define. (v9d): Likewise. (v9e): Likewise. (v9v): Likewise. (v9m): Likewise. (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.	10 years ago
Jose E. Marchesi	337c570c5f	sparc: add missing comment about hyperprivileged register operands include/ChangeLog: 2016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/sparc.h: Add missing documentation for hyperprivileged registers in rd (%) and rs1 ($).	10 years ago
Trevor Saunders	1fe0971e41	add more extern C opcodes/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * nds32-asm.h: Add extern "C". * sh-opc.h: Likewise. bfd/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * elf32-hppa.h: Add extern "C". * elf32-nds32.h: Likewise. * elf32-tic6x.h: Likewise. include/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * elf/mips.h: Likewise. * elf/sh.h: Likewise. * opcode/d10v.h: Likewise. * opcode/d30v.h: Likewise. * opcode/ia64.h: Likewise. * opcode/mips.h: Likewise. * opcode/ppc.h: Likewise. * opcode/sparc.h: Likewise. * opcode/tic6x.h: Likewise. * opcode/v850.h: Likewise.	10 years ago
Alan Modra	6f2750feaf	Copyright update for binutils	10 years ago
Alan Modra	b90efa5b79	ChangeLog rotatation and copyright year update	11 years ago
Jose E. Marchesi	0b6be41550	opcodes, elf: annotate instructions with HWCAP2_VIS3B. This patch annotates the following SPARC instructions as VIS3B instructions: ldx , %efsr, fpadd64, fpsub64, fpcmpule8, fpcmpune8, fpcmpugt8, fpcmpueq8. It also improves the documentation of the VIS3B capability in several headers. Tested in sparc64-unknown-linux-gnu and sparc-unknown-linux-gnu. No visible regressions. opcodes/ChangeLog: 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com> sparc-opc.c (sparc-opcodes): Annotate several instructions with the HWCAP2_VIS3B hwcap. include/opcodes/ChangeLog: 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc.h (HWCAP2_VIS3B): Documentation improved. include/elf/ChangeLog: 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc.h (ELF_SPARC_HWCAP2_VIS3B): Documentation improved.	12 years ago
Jose E. Marchesi	3d68f91c0f	This is a series of patches that add support for the SPARC M7 cpu to binutils. They were discussed and approved here: https://sourceware.org/ml/binutils/2014-10/msg00038.html	12 years ago
Alan Modra	4b95cf5c0c	Update copyright years	12 years ago
Eric Botcazou	d6787ef95c	gas/ * config/tc-sparc.c (sparc_arch_types): Add leon. (sparc_arch): Move sparc4 around and add leon. (sparc_target_format): Document -Aleon. * doc/c-sparc.texi: Likewise. include/ * opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON. opcodes/ * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for bfd_mach_sparc. * sparc-opc.c (MASK_LEON): Define. (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON. (letandleon): New macro. (v9andleon): Likewise. (sparc_opc): Add leon. (umac): Enable for letandleon. (smac): Likewise. (casa): Enable for v9andleon. (cas): Likewise. (casl): Likewise.	13 years ago
David S. Miller	0afd121540	Increase the accuracy of sparc instruction aliases. Make current with UA2011 specification. Add an F_PREFERRED opcode flag that indicates a preferred alias when multiple aliases for the same opcode exists. For 'lzd': Add 'lzcnt' as primary instruction, and make 'lzd' an alias. Add 'ldtw', 'ldtwa', 'sttw', 'sttwa': The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on integer registers. Mark the latter now as aliases. For 'flush': Support "[address]" syntax as well as plain "address". Rework 'mov' aliases for 'wr': Eliminate bogus three operand moves, and encode the instructions properly for the "mov REG, %ASR" cases, specifically we should encode the register in rs2 not rs1 as per The SPARC V8 Architecture Manual. Add missing cbcond aliases: c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu Add 'd' suffix VIS logical ops: The primary opcode for 'fzero' is now 'fzerod' (compare with 'fzeros'), for example. And thus 'fzero' is now an alias. Add modern opcodes for condition code setting edge instructions: They are now edgeN{,l}cc instead of plain edgeN{,l}. Add modern opcodes for VIS comparisons: All VIS comparisons now start with prefix "fp", retain the older variants as aliases. The signed variants for equal and not-equal have "u" aliases to show that these comparisons are equally suited for unsigned compares. Update existing test cases as needed, and add several new ones. include/opcode/ * sparc.h (F_PREFERRED): Define. (F_PREF_ALIAS): Define. opcodes/ * sparc-dis.c (compare_opcodes): When encountering multiple aliases of an opcode, prefer the one with F_PREFERRED set. * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa, lzcnt, flush with '[address]' syntax, and missing cbcond pseudo ops. Make 64-bit VIS logical ops have "d" suffix in their names, mark existing mnenomics as aliases. Add "cc" suffix to edge instructions generating condition codes, mark existing mnenomics as aliases. Add "fp" prefix to VIS compare instructions, mark existing mnenomics as aliases. gas/testsuite/ * gas/sparc/cbcond.s: Add tests for new opcode aliases. * gas/sparc/cbcond.d: Updated. * gas/sparc/hpcvis3.s: Add tests for new opcode aliases. * gas/sparc/hpcvis3.d: Updated. * gas/sparc/v8-movwr-imm.d: Fix expected disassembly. * gas/sparc/edge.s: New test. * gas/sparc/edge.d: Expected disassembly. * gas/sparc/flush.s: New test. * gas/sparc/flush.d: Expected disassembly. * gas/sparc/ldd_std.s: New test. * gas/sparc/ldd_std.d: Expected disassembly. * gas/sparc/ldtw_sttw.s: New test. * gas/sparc/ldtw_sttw.d: Expected disassembly. * gas/sparc/sparc.exp: Run new tests.	13 years ago
David S. Miller	2c63854f55	Fix sparc opcode encoding for 4-arg crypto instructions. include/opcode * sparc.h (F3F4): New macro. opcodes * sparc-opc.c (4-argument crypto instructions): Fix encoding using F3F4 macro. gas/testsuite * gas/sparc/crypto.d: Fix opcodes for 4-arg crypto instructions.	14 years ago
David S. Miller	6cda13266f	Add support for SPARC T4 crypto instructions. include/opcode/ * sparc.h: Document new arg code' )' for crypto RS3 immediates. opcodes/ * sparc-dis.c (print_insn_sparc): Handle ')'. * sparc-opc.c (sparc_opcodes): Add crypto instructions. gas/ * config/tc-sparc.c (sparc_ip): Likewise. Accept instruction names containing "_". (sparc_arch_table): Add sparc4, v8pluse, and v9e. Add crypto hwcap masks to v8plusv and v9v. gas/testsuite/ * gas/sparc/crypto.s: New file. * gas/sparc/crypto.d: New file. * gas/sparc/sparc.exp: Run crypto test.	14 years ago
David S. Miller	ec668d69b9	Move sparc opcode hwcaps out of sparc_opcode flags field. include/opcode/ * sparc.h (struct sparc_opcode): New field 'hwcaps'. F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete. (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC, HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF, HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU, HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES, HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1, HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE, HWCAP_CBCOND, HWCAP_CRC32): New defines. opcodes/ * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values into new struct sparc_opcode 'hwcaps' field instead of 'flags'. gas/ * config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_* masks. (sparc_md_end): No longer need to translate hwcap_seen values into ELF hwcap bits, they now match exactly. (get_hwcap_name): Use HWCAP_* and handle new values. (sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.	14 years ago
David S. Miller	2615994e91	Support R_SPARC_WDISP10 and R_SPARC_H34. include/ * elf/sparc.h (R_SPARC_WDISP10): New reloc. * opcode/sparc.h: Define '=' as generating R_SPARC_WDISP10. opcodes/ * sparc-dis.c (X_DISP10): Define. (print_insn_sparc): Handle '='. bfd/ * reloc.c (BFD_RELOC_SPARC_H34, BFD_RELOC_SPARC_SIZE32, BFD_RELOC_SPARC_SIZE64, BFD_RELOC_SPARC_WDISP10): New relocs. * libbfd.h: Regenerate. * bfd-in2.h: Likewise. * elfxx-sparc.c (sparc_elf_wdisp10_reloc): New function. (_bfd_sparc_elf_howto_table): Add entries for R_SPARC_H34, R_SPARC_SIZE32, R_SPARC_64, and R_SPARC_WDISP10. (_bfd_sparc_elf_reloc_type_lookup): Handle new relocs. (_bfd_sparc_elf_check_relocs): Likewise. (_bfd_sparc_elf_gc_sweep_hook): Likewise. (_bfd_sparc_elf_relocate_section): Likewise. gas/ * config/tc-sparc.c (sparc_ip): Handle '=', "%h34", "%l34", and BFD_RELOC_SPARC_H34. (md_apply_fix): Handle BFD_RELOC_SPARC_WDISP10 and BFD_RELOC_SPARC_H34. (tc_gen_reloc): Likewise. gas/testsuite/ * gas/sparc/reloc64.s: Add abs34 code model tests. * gas/sparc/reloc64.d: Update. elfcpp/ * sparc.h (R_SPARC_WDISP10): New relocation. gold/ * sparc.cc (Reloc::wdisp10): New relocation method. (Reloc::h34): Likewise. (Target_sparc::Scan::check_non_pic): Handle R_SPARC_H34. (Target_sparc::Scan::get_reference_flags): Handle R_SPARC_H34 and R_SPARC_WDISP10. (Target_sparc::Scan::local): Likewise. (Target_sparc::Scan::global): Likewise. (Target_sparc::Relocate::relocate): Likewise.	14 years ago
David S. Miller	9e8c70f96b	Annotate sparc objects with cpu hardware capabilities used. bfd/ * elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): New. * elfxx-sparc.h: Declare it. * elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Call it. * elf64-sparc.c (elf64_sparc_merge_private_bfd_data): Likewise. binutils/ * readelf.c (display_sparc_hwcaps): New. (display_sparc_gnu_attribute): New. (process_sparc_specific): New. (process_arch_specific): When EM_SPARC, EM_SPARC32PLUS, or EM_SPARCV9 invoke process_sparc_specific. gas/ * config/tc-sparc.c (hwcap_seen): New bitmask, defined when not TE_SOLARIS. (sparc_ip): When not TE_SOLARIS, accumulate hwcap bits from sparc_opcode->flags of instruction into hwcap_seen. (sparc_md_end): Create Tag_GNU_Sparc_HWCAPS attribute if hwcap_seen is non-zero and not TE_SOLARIS. gas/testsuite/ * gas/sparc/hpcvis3.s: Update for fixed fchksum16 mnemonic. * gas/sparc/hpcvis3.d: Likewise. include/elf/ * sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute. (ELF_SPARC_HWCAP_): New HWCAPS bitmask values. include/opcode/ sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int. (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. opcodes/ * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag bits. Fix "fchksm16" mnemonic.	15 years ago
David S. Miller	ea783ef3a0	include/opcode/ * sparc.h: Document new format codes '4', '5', and '('. (OPF_LOW4, RS3): New macros. opcodes/ * sparc-dis.c (v9a_ast_reg_names): Add "cps". (X_RS3): New macro. (print_insn_sparc): Handle '4', '5', and '(' format codes. Accept %asr numbers below 28. * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3 instructions. gas/ * config/tc-sparc.c (v9a_asr_table): Add "cps". (sparc_ip): Handle '4', '5' and '(' format codes. gas/testsuite * gas/sparc/hpcvis3.d: New test. * gas/sparc/hpcvis3.s: New test source. * gas/sparc/sparc.exp: Run new test.	15 years ago
Nick Clifton	e4e42b45d5	Upgrade header files to use GPLv3	16 years ago
Nick Clifton	47b0e7ad8c	Update function declarations to ISO C90 formatting	21 years ago
Nick Clifton	e172dbf8aa	Update the address and phone number of the FSF organization	21 years ago
Alan Modra	8cf3f35467	Convert to C90.	23 years ago
Alan Modra	b3f7d5fdb0	* ia64.h: Use #include "" instead of <> for local header files. * sparc.h: Likewise.	24 years ago
Nick Clifton	4f1d9bd8e2	Fix typos in ChangeLogs; add coff/external.h; fix copyright dates	25 years ago
Jakub Jelinek	19f7b01094	gas/ * config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p instructions to loose any special insn->architecture mask. * config/tc-sparc.c (v9a_asr_table): Add v9b ASRs. (sparc_md_end, sparc_arch_types, sparc_arch, sparc_elf_final_processing): Handle v8plusb and v9b architectures. (sparc_ip): Handle siam mode operands. Support v9b ASRs (and request v9b architecture if they are used). bfd/ * elf32-sparc.c (elf32_sparc_merge_private_bfd_data, elf32_sparc_object_p, elf32_sparc_final_write_processing): Support v8plusb. * elf64-sparc.c (sparc64_elf_merge_private_bfd_data, sparc64_elf_object_p): Support v9b. * archures.c: Declare v8plusb and v9b machines. * bfd-in2.h: Ditto. * cpu-sparc.c: Ditto. include/opcode/ * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. Note that '3' is used for siam operand. opcodes/ * sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs. (compute_arch_mask): Add v8plusb and v9b machines. (print_insn_sparc): siam mode decoding, accept ASRs up to 25. * opcodes/sparc-opc.c: Support for Cheetah instruction set. (prefetch_table): Add #invalidate.	26 years ago
Richard Henderson	252b5132c7	19990502 sourceware import	27 years ago
Stan Shebs	071ea11e85	Initial creation of sourceware repository	27 years ago
Ian Lance Taylor	5583be2433	* sparc.h: Include <ansidecl.h>. Update function declarations to use prototypes, and to use const when appropriate.	30 years ago
Ian Lance Taylor	b21efdbe64	* sparc.h (F_FLOAT, F_FBR): Define. PR 355.	30 years ago
David Edelsohn	4be1b31325	* sparc.h (SPARC_OPCODE_ARCH_MASK): New macro.	30 years ago
David Edelsohn	8c3f315e6a	* sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare. Mark operand letters uU as in use.	31 years ago
Jeff Law	803108ab64	* sparc.h (sparc_opcode_lookup_arch) Make return type in declaration consistent with return type in definition.	31 years ago
David Edelsohn	7484896ba2	* sparc.h (enum sparc_opcode_arch_val): Replaces sparc_architecture. (SPARC_OPCODE_CONFLICT_P): Renamed from ARCHITECTURES_CONFLICT_P. (bfd_* defines): Delete. (sparc_opcode_archs): Replaces architecture_pname. (sparc_opcode_lookup_arch): Declare. (NUMOPCODES): Delete.	31 years ago
David Edelsohn	2d422c4234	(ARCHITECTURES_CONFLICT_P): Add ChangeLog entry for v9a addition and fix typo in macro.	31 years ago
David Edelsohn	224721792f	* sparc.h (enum sparc_architecture): Add v9a.	31 years ago
David Edelsohn	44292d2e1e	* sparc.h (sparc_{encode,decode}_asi): Declare.	31 years ago
David Edelsohn	97eab8a17c	* sparc.h (F_NOTV9): Define.	31 years ago
Ken Raeburn	f2c42ba402	update doc for sparclite 934 opcode table changes	32 years ago
Ken Raeburn	7b22a53c6c	m68k.h (m68ec030): Defined as alias for 68030. (m68k_opcodes): New type characters "3" for 68030 MMU regs and "t" for immediate 0-7 added. Set up some opcodes (ptest, bkpt) to use them. Tightened description of "fmovex" to distinguish it from some "pmove" encodings. Added "pmove" for 68030 MMU regs, cleaned up descriptions that claimed versions were available for chips not supporting them. Added "pmovefd". sparc.h: Fixed up some comments.	34 years ago
Ken Raeburn	47660bef1b	fix for PRs 1360 and 1370 -- new v8 patterns for save,inc,dec	34 years ago
Stu Grossman	cc35cb05ce	* sparc.h: fix opcode for tsubcctv.	35 years ago
Michael Tiemann	a9b0d1aece	* sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is disassembled as a nop.	35 years ago

34 Commits (cf0e0a0ba91664b680dff1e310f24dbe6447bd4c)