binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Richard Sandiford	9752cf1b67	[include/opcode/] * mips.h: Update comment for new opcodes. (OP_MASK_VECBYTE, OP_SH_VECBYTE): New. (OP_MASK_VECALIGN, OP_SH_VECALIGN): New. (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New. (CPU_VR4120, CPU_VR5400, CPU_VR5500): New. (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags. Don't match CPU_R4111 with INSN_4100. [opcodes/] * mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'. (mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400 and bfd_mach_mips5500. * mips-opc.c (V1): Include INSN_4111 and INSN_4120. (N411, N412, N5, N54, N55): New convenience defines. (mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes. Change dmadd16 and madd16 from V1 to N411.	24 years ago
Thiemo Seufer	3396de367a	/gas/ChangeLog * config/tc-mips.c (CPU_HAS_MIPS16): Add mips-lsi-elf as MIPS16 capable configuration. (macro_build): Check for MIPS16 capability, not for actual MIPS16 code generation. (mips_ip): Likewise. /gas/testsuite/ChangeLog * gas/mips/mips-jalx.d: New file, check jalx assembly. * gas/mips/mips-jalx.s: Likewise. * gas/mips/mips-no-jalx.l: Likewise. * gas/mips/mips-no-jalx.s: Likewise. * gas/mips/mips16-jalx.d: Likewise. * gas/mips/mips16-jalx.s: Likewise. * gas/mips/mips.exp: Add new tests. /opcodes/ChangeLog: * mips-dis.c (print_insn_mips): Always allow disassembly of 32-bit jalx opcode.	24 years ago
Nick Clifton	1a40396432	Updated German translation.	24 years ago
Alan Modra	2d2550d688	* Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.	24 years ago
Nick Clifton	0ec499f72c	Allow CRFS and CRFD operands to accept CR register names	24 years ago
Alan Modra	4415b5c296	* tic4x-dis.c: Add function declarations and ATTRIBUTE_UNUSED. Convert functions to K&R format.	24 years ago
Nick Clifton	dde1b13223	Fix Book-E opcodes	24 years ago
Alan Modra	9ec878e367	* ppc-dis.c (powerpc_dialect): Add missing PPC_OPCODE_CLASSIC.	24 years ago
Nick Clifton	e09f439535	Update translations	24 years ago
Nick Clifton	341026c1c1	Do not insert non-BookE32 instructions into the hash table if the target cpu is the BookE32. (case 107575)	24 years ago
Nick Clifton	07dd56a969	Have objdump's --help switch document PPC -M options.	24 years ago
Nick Clifton	2e32aab953	The BookE implementations of the TLBWE and TLBRE instructions do not take any arguments.	24 years ago
Nick Clifton	bf5be08227	Remove redundant references to V850EA architecture.	24 years ago
Alan Modra	d943fe33c6	* arc-opc.c: Include bfd.h. (arc_get_opcode_mach): Subtract off base bfd_mach value.	24 years ago
Alan Modra	53f32ea5c6	* v850-dis.c (disassemble): Remove bfd_mach_v850ea case. * mips-dis.c (_print_insn_mips): Don't use hard-coded mach constants.	24 years ago
Nick Clifton	026df7c5e6	Add TMS320C4x support	24 years ago
Nick Clifton	1489984027	opcodes: Fix definition of "in rd,imm16" opcode. gas: Adjust ptr variable also in "case 0" case.	24 years ago
Elena Zannoni	2397604975	2002-08-19 Elena Zannoni <ezannoni@redhat.com> From matthew green <mrg@redhat.com> * ppc-dis.c (powerpc_dialect): Support `-m500', `-m500x2' and `-mefs'. Turn off AltiVec for E500 and efs. (print_insn_powerpc): Don't print an AltiVec instruction if the dialect is not efs. * ppc-opc.c (insert_pmrn, extract_pmrn, insert_ev2, extract_ev2, insert_ev4, extract_ev4, insert_ev8, extract_ev8): New functions for extracting pmrn/evld/evstd/etc operands. (CRB, CRFD, CRFS, DC, RD): New instruction fields. (CT): Make this equal to RD + 1. (PMRN): New operand. (RA): Update. (EVUIMM, EVUIMM_2, EVUIMM_4, EVUIMM_8): New operands. (WS): Update. (EVSEL, EVSEL_MASK): New instruction form and mask for EVSEL. (ISEL, ISEL_MASK): New instruction form and mask for ISEL. (XISEL, XISEL_MASK): New instruction form and mask for ISEL. (CTX, CTX_MASK): New instruction form and mask for context cache instructions. (UCTX, UCTX_MASK): New instruction form and mask for user context cache instructions. (XC, XC_MASK, XUC, XUC_MASK): New instruction forms. (CLASSIC): New define. (PPCESPE): New define. (PPCISEL, , PPCBRLK, PPCPMR, PPCCHLK, PPCRFMI): New defines for integer select, cache control, branch locking, power management, cache locking and machine check APU instructions, respectively. (efsabs, efsnabs, efsneg, efsadd, efssub, efsmul, efsdiv, efscmpgt, efscmplt, efscmpeq, efststgt, efststlt, efststeq, efscfui, efsctuiz, efscfsi, efscfuf, efscfsf, efsctui, efsctsi, efsctsiz, efsctuf, efsctsf, evaddw, evaddiw, evsubfw, evsubifw, evabs, evneg, evextsb, evextsh, evrndw, evcntlzw, evcntlsw, brinc, evand, evandc, evor, evorc, evxor, eveqv, evnand, evnor, evrlw, evrlwi, evslw, evslwi, evsrws, evsrwu, evsrwis, evsrwiu, evsplati, evsplatfi, evmergehi, evmergelo, evmergehilo, evmergelohi, evcmpgts, evcmpgtu, evcmplts, evcmpltu, evcmpeq, evsel, evldd, evlddx, evldw, evldwx, evldh, evldhx, evlwhe, evlwhex, evlwhou, evlwhoux, evlwhos, evlwhosx, evlwwsplat, evlwwsplatx, evlwhsplat, evlwhsplatx, evlhhesplat, evlhhesplatx, evlhousplat, evlhousplatx, evlhossplat, evlhossplatx, evstdd, evstddx, evstdw, evstdwx, evstdh, evstdhx, evstwwe, evstwwex, evstwwo, evstwwox, evstwhe, evstwhex, evstwho, evstwhox, evfsabs, evfsnabs, evfsneg, evfsadd, evfssub, evfsmul, evfsdiv, evfscmpgt, evfscmplt, evfscmpeq, evfststgt, evfststlt, evfststeq, evfscfui, evfsctuiz, evfscfsi, evfscfuf, evfscfsf, evfsctui, evfsctsi, evfsctsiz, evfsctuf, evfsctsf, evsabs, evsnabs, evsneg, evsadd, evssub, evsmul, evsdiv, evscmpgt, evsgmplt, evsgmpeq, evststgt, evststlt, evststeq, evscfui, evscfsi, evscfuf, evscfsf, evsctui, evsctuiz, evsctsi, evsctsiz, evsctuf, evsctsf, evmhossf, evmhossfa, evmhosmf, evmhosmfa, evmhosmi, evmhosmia, evmhoumi, evmhoumia, evmhessf, evmhessfa, evmhesmf, evmhesmfa, evmhesmi, evmhesmia, evmheumi, evmheumia, evmhossfaaw, evmhossiaaw, evmhosmfaaw, evmhosmiaaw, evmhousiaaw, evmhoumiaaw, evmhessfaaw, evmhessiaaw, evmhesmfaaw, evmhesmiaaw, evmheusiaaw, evmheumiaaw, evmhossfanw, evmhossianw, evmhosmfanw, evmhosmianw, evmhousianw, evmhoumianw, evmhessfanw, evmhessianw, evmhesmfanw, evmhesmianw, evmheusianw, evmheumianw, evmhogsmfaa, evmhogsmiaa, evmhogumiaa, evmhegsmfaa, evmhegsmiaa, evmhegumiaa, evmhogsmfan, evmhogsmian, evmhogumian, evmhegsmfan, evmhegsmian, evmhegumian, evmwhssf, evmwhssfa, evmwhssfaa, evmwhssmaa, evmwhsmfaa, evmwhsmiaa, evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, evmwhsmfan, evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, evmwhgsmfaa, evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, evmwhgsmian, evmwhgumian, evmwhsmf, evmwhsmfa, evmshsmi, evmshsmia, evmshumi, evmshumia, evmmlssf, evmmlssfa, evmwlsmf, evmwlsmfa, evmwlumi, evmwlumia, evmwlssfaaw, evmwlssiaaw, evmwlsmfaaw, evmwlsmiaaw, evmwlusiaaw, evmwlumiaaw, evmwissfanw, evmwissianw, evmwlsmfanw, evmwlsmianw, evmwlusianw, evmwlumianw, evmwssf, evmwssfa, evmwsmf, evmwsmfa, evmwsmi, evmwsmia, evmwumi, evmwumia, evmwssfaa, evmwsmfaa, evmwsmiaa, evmwumiaa, evmwssfan, evmwsmfan, evmwsmian, evmwumian, evaddssiaaw, evaddsmiaaw, evaddusiaaw, evaddumiaaw, evsubfssiaaw, evsubfsmiaaw, evsubfusiaaw, evsubfumiaaw, evmra, evdivws, evdivws): New e500x2 Core Complex instructions. (rfmci): New machine check APU instruction. (isel): New integer select APU instructino. (icbtls, icbtlse, icblc, icblce, dcbtls, dcbtlse, dcbtstls, dcbtstlse, dcblc, dcblce): New cache control APU instructions. (mtspefscr, mfspefscr): New instructions. (mfpmr, mtpmr): New performance monitor APU instructions. (savecontext): New context cache APU instructions. (bblels, bbelr): New branch locking APU instructions. (bblels, bbelr): New instructions. (mftbl, mftbu, mftb): Set as CLASSIC instructions. Add BOOKE alias.	24 years ago
Stephane Carrez	7eccd7f6f1	* m68hc11-opc.c: Update call operand to accept the page definition. Identify instructions that are branches and calls to generate a RL_JUMP relocation.	24 years ago
Stephane Carrez	f07534f64e	* m68hc11-dis.c (print_insn): Take into account 68HC12 memory banks and fix disassembling of call instruction. (print_indexed_operand): New param to tell whether it was an indirect addressing operand (for disassembling call).	24 years ago
Nick Clifton	2b692c5912	Updated Swedish translation	24 years ago
Maciej W. Rozycki	0c11417f42	* config/tc-mips.c (macro): Handle a register plus a 16-bit immediate offset in "dla" and "la" expansions. * gas/mips/empic.d: Treat "addiu" and "daddiu" as equivalent when $0 is source. * mips-opc.c (mips_builtin_opcodes): Remove "dla" and "la" as aliases to "daddiu" and "addiu".	24 years ago
Nick Clifton	83e1617e06	Updated Translations	24 years ago
Nick Clifton	219576a4db	New translations	24 years ago
Nick Clifton	ff3063f557	Update Spanish and Swedish translations	24 years ago
Alan Modra	8c3bb577a6	* Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.	24 years ago
Nick Clifton	2c71db8993	oops - omitted from previous delta	24 years ago
Nick Clifton	0461a601af	update translations.	24 years ago
Nick Clifton	a40cbfa3c9	Add IP2k GAS and OPCODES support.	24 years ago
H.J. Lu	ae66e5d720	2002-07-17 David Mosberger <davidm@hpl.hp.com> * ia64-opc-b.c (bWhc): New macro. (mWhc): Ditto. (OpPaWhcD): Ditto. (ia64_opcodes_b): Correct patterns for indirect call instructions to use 3-bit "wh" field. * ia64-asmtab.c: Regnerate.	24 years ago
Thiemo Seufer	aec421e08b	* config/tc-mips.c (macro_build): Handle MIPS16 insns. (mips_ip): Likewise. * mips.h (INSN_MIPS16): New define. * mips-dis.c (mips_isa_type): Add MIPS16 insn handling. * mips-opc.c (I16): New define. (mips_builtin_opcodes): Make jalx an I16 insn.	24 years ago
Dave Brolley	fd3c93d5a7	2002-06-18 Dave Brolley <brolley@redhat.com> * po/POTFILES.in: Add frv-.[ch]. disassemble.c (ARCH_frv): New macro. (disassembler): Handle bfd_arch_frv. * configure.in: Support frv_bfd_arch. * Makefile.am (HFILES): Add frv-.h. (CFILES): Add frv-.c (ALL_MACHINES): Add frv-.lo. (CLEANFILES): Add stamp-frv. (FRV_DEPS): New variable. (stamp-frv): New target. (frv-asm.lo): New target. (frv-desc.lo): New target. (frv-dis.lo): New target. (frv-ibld.lo): New target. (frv-opc.lo): New target. (frv-.[ch]): New files.	25 years ago
Ben Elliston	bc98a6310f	* Makefile.am (CGENDEPS): Remove unnecessary stamp-cgen. * Makefile.in: Regenerate.	25 years ago
Alan Modra	56da5fedc7	* a29k-dis.c: Replace CONST with const. * h8300-dis.c: Likewise. * m68k-dis.c: Likewise. * or32-dis.c: Likewise. * sparc-dis.c: Likewise.	25 years ago
Jason Thorpe	5b0e55b627	bfd: * Makefile.am (BFD32_BACKENDS): Add elf32-sh64-nbsd.lo. (BFD32_BACKENDS_CFILES): Add elf32-sh64-nbsd.c. (BFD64_BACKENDS): Add elf64-sh64-nbsd.lo. (BFD64_BACKENDS_CFILES): Add elf64-sh64-nbsd.c. (elf32-sh64-nbsd.lo, elf64-sh64-nbsd.lo): New rules. * Makefile.in: Regenerate. * config.bfd (sh5le--netbsd, sh5--netbsd, sh64le--netbsd) (sh64--netbsd): New targets. * configure.in: Add bfd_elf32_sh64nbsd_vec, bfd_elf32_sh64lnbsd_vec, bfd_elf64_sh64nbsd_vec, and bfd_elf64_sh64lnbsd_vec. * configure: Regenerate. * elf32-sh64-nbsd.c: New file. * elf64-sh64-nbsd.c: New file. * targets.c: Add extern decls for bfd_elf32_sh64nbsd_vec, bfd_elf32_sh64lnbsd_vec, bfd_elf64_sh64nbsd_vec, and bfd_elf64_sh64lnbsd_vec. gas: * configure.in (sh5): Set cpu_type to sh64 and endian to big. (sh5le, sh64le): Set cpu_type to sh64 and endian to little. (sh5--netbsd, sh64--netbsd): New targets. configure: Regenerate. * config/tc-sh64.c (sh64_target_format): Add support for NetBSD environment. ld: * Makefile.am (ALL_EMULATIONS): Add eshelf32_nbsd.o, eshlelf32_nbsd.o, eshelf64_nbsd.o, and eshlelf64_nbsd.o. (eshelf32_nbsd.c, eshelf64_nbsd.c, eshlelf32_nbsd.c) (eshlelf64_nbsd.c): New rules. * Makefile.in: Regenerate. * configure.tgt (sh5le--netbsd, sh5--netbsd, sh64le--netbsd) (sh64--netbsd): New targets. * emulparams/shelf32_nbsd.sh: New file. * emulparams/shelf64_nbsd.sh: New file. * emulparams/shlelf32_nbsd.sh: New file. * emulparams/shlelf64_nbsd.sh: New file. opcodes: * configure.in: Add "sh5-" to list of targets which include sh64 support. * configure: Regenerate.	25 years ago
Chris Demetriou	154bce22d5	2002-05-31 Chris G. Demetriou <cgd@broadcom.com> * mips-opc.c: Clean up a few whitespace issues, and sort a few entries understanding that 'x' follows 'w' in the alphabet.	25 years ago
Chris Demetriou	107c6e1ad8	[ opcodes/ChangeLog ] 2002-05-31 Chris G. Demetriou <cgd@broadcom.com> Ed Satterthwaite <ehs@broadcom.com> * mips-opc.c: Add support for SB-1 MDMX subset and extensions. [ gas/testsuite/ChangeLog ] 2002-05-31 Chris G. Demetriou <cgd@broadcom.com> * gas/mips/sb1-ext-mdmx.s: New file. * gas/mips/sb1-ext-mdmx.d: Likewise. * gas/mips/mips.exp: Run new "sb1-ext-mdmx" test.	25 years ago
Alan Modra	194b521088	* Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.	25 years ago
Chris Demetriou	deec17343c	[ gas/ChangeLog ] 2002-05-30 Chris G. Demetriou <cgd@broadcom.com> Ed Satterthwaite <ehs@broadcom.com> * config/tc-mips.c (mips_set_options): New "ase_mdmx" member. (mips_opts): Initialize "ase_mdmx" member. (file_ase_mdmx): New variable. (CPU_HAS_MDMX): New macro. (md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx based on command line options and configuration defaults. (macro_build): Note in comment that use of MDMX in macros is not currently allowed. (validate_mips_insn): Add support for the "O", "Q", "X", "Y", and "Z" MDMX operand types. (mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set, and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand types. (OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option): Add support for "-mdmx" and "-no-mdmx" options. (OPTION_ELF_BASE): Move to accomodate new options. (s_mipsset): Support ".set mdmx" and ".set nomdmx". (mips_elf_final_processing): Set MDMX ASE ELF header flag if file_ase_mdmx was set. * doc/as.texinfo: Document -mdmx and -no-mdmx options. * doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set nomdmx" directives. [ gas/testsuite/ChangeLog ] 2002-05-30 Chris G. Demetriou <cgd@broadcom.com> * gas/mips/mips64-mdmx.s: New file. * gas/mips/mips64-mdmx.d: Likewise. * gas/mips/mips.exp: Run new "mips64-mdmx" test. [ include/opcode/ChangeLog ] 2002-05-30 Chris G. Demetriou <cgd@broadcom.com> * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL) (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH) (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC) (INSN_MDMX): New constants, for MDMX support. (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX. [ opcodes/ChangeLog ] 2002-05-30 Chris G. Demetriou <cgd@broadcom.com> Ed Satterthwaite <ehs@broadcom.com> * mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y', and 'Z' formats, for MDMX. (mips_isa_type): Add MDMX instructions to the ISA bit mask for bfd_mach_mipsisa64. * mips-opc.c: Add support for MDMX instructions. (MX): New definition. * mips-dis.c: Update copyright years to include 2002.	25 years ago
Tom Rix	c20129930b	Fix for invalid conflict warning.	25 years ago
Nick Clifton	d172d4ba03	Add DLX target	25 years ago
Alan Modra	19f33eeef5	* Makefile.am (sh-dis.lo): Don't put make commands in deps. * Makefile.in: Regenerate. * arc-dis.c: Use #include "" instead of <> for local header files. * m68k-dis.c: Likewise.	25 years ago
Nick Clifton	baf0cc5e96	Fix handling of BLX instruction to conform to Operations definition in the ARM ARM.	25 years ago
Joern Rennecke	9ccc8931b8	* Makefile.am (sh-dis.lo): Compile with @archdefs@. * Makefile.in: regenerate.	25 years ago
Joern Rennecke	4ee33023a0	Avoid dereferencing null pointer in: * sh-dis.c (print_insn_sh): If coff and bfd_mach_sh, use arch_sh4 for disassembly.	25 years ago
Joern Rennecke	426e6456c0	* sh-dis.c (print_insn_sh): If coff and bfd_mach_sh, use arch_sh4 for disassembly.	25 years ago
Thiemo Seufer	771c7ce4bc	? gas/testsuite/gas/mips/rol64.d ? gas/testsuite/gas/mips/rol64.s Index: gas/ChangeLog =================================================================== RCS file: /cvs/src/src/gas/ChangeLog,v retrieving revision 1.1334 diff -u -p -r1.1334 ChangeLog --- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334 +++ gas/ChangeLog 21 May 2002 23:32:51 -0000 @@ -1,3 +1,8 @@ +2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * config/tc-mips.c (macro2): Add 64 bit drol, dror macros. + Optimize the rotate by zero case. + 2002-05-21 Nick Clifton <nickc@cambridge.redhat.com> * configure.in: Remove accidental enabling of bfd_gas=yes for Index: gas/config/tc-mips.c =================================================================== RCS file: /cvs/src/src/gas/config/tc-mips.c,v retrieving revision 1.123 diff -u -p -r1.123 tc-mips.c --- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123 +++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000 @@ -6686,6 +6686,17 @@ macro2 (ip) --mips_opts.noreorder; break; + case M_DROL: + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "dsubu", + "d,v,t", AT, 0, treg); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "dsrlv", + "d,t,s", AT, sreg, AT); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "dsllv", + "d,t,s", dreg, sreg, treg); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", + "d,v,t", dreg, dreg, AT); + break; + case M_ROL: macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "subu", "d,v,t", AT, 0, treg); @@ -6697,15 +6708,55 @@ macro2 (ip) "d,v,t", dreg, dreg, AT); break; + case M_DROL_I: + { + unsigned int rot; + char l, r; + + if (imm_expr.X_op != O_constant) + as_bad (_("rotate count too large")); + rot = imm_expr.X_add_number & 0x3f; + if (! rot) + break; + l = (rot < 0x20) ? "dsll" : "dsll32"; + r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; + rot &= 0x1f; + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, l, + "d,w,<", AT, sreg, rot); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, r, + "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", + "d,v,t", dreg, dreg, AT); + } + break; + case M_ROL_I: - if (imm_expr.X_op != O_constant) - as_bad (_("rotate count too large")); - macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "sll", "d,w,<", - AT, sreg, (int) (imm_expr.X_add_number & 0x1f)); - macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "srl", "d,w,<", - dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f)); - macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", "d,v,t", - dreg, dreg, AT); + { + unsigned int rot; + + if (imm_expr.X_op != O_constant) + as_bad (_("rotate count too large")); + rot = imm_expr.X_add_number & 0x1f; + if (! rot) + break; + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "sll", + "d,w,<", AT, sreg, rot); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "srl", + "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", + "d,v,t", dreg, dreg, AT); + } + break; + + case M_DROR: + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "dsubu", + "d,v,t", AT, 0, treg); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "dsllv", + "d,t,s", AT, sreg, AT); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "dsrlv", + "d,t,s", dreg, sreg, treg); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", + "d,v,t", dreg, dreg, AT); break; case M_ROR: @@ -6719,15 +6770,44 @@ macro2 (ip) "d,v,t", dreg, dreg, AT); break; + case M_DROR_I: + { + unsigned int rot; + char l, r; + + if (imm_expr.X_op != O_constant) + as_bad (_("rotate count too large")); + rot = imm_expr.X_add_number & 0x3f; + if (! rot) + break; + r = (rot < 0x20) ? "dsrl" : "dsrl32"; + l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; + rot &= 0x1f; + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, r, + "d,w,<", AT, sreg, rot); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, l, + "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", + "d,v,t", dreg, dreg, AT); + } + break; + case M_ROR_I: - if (imm_expr.X_op != O_constant) - as_bad (_("rotate count too large")); - macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "srl", "d,w,<", - AT, sreg, (int) (imm_expr.X_add_number & 0x1f)); - macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "sll", "d,w,<", - dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f)); - macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", "d,v,t", - dreg, dreg, AT); + { + unsigned int rot; + + if (imm_expr.X_op != O_constant) + as_bad (_("rotate count too large")); + rot = imm_expr.X_add_number & 0x1f; + if (! rot) + break; + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "srl", + "d,w,<", AT, sreg, rot); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "sll", + "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); + macro_build ((char ) NULL, &icnt, (expressionS ) NULL, "or", + "d,v,t", dreg, dreg, AT); + } break; case M_S_DOB: Index: gas/testsuite/ChangeLog =================================================================== RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v retrieving revision 1.315 diff -u -p -r1.315 ChangeLog --- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315 +++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000 @@ -1,3 +1,9 @@ +2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * gas/mips/rol64.s: New file, test of drol, dror macros. + * gas/mips/rol64.d: Likewise. + * gas/mips/mips.exp: Add new test. + 2002-05-20 Nick Clifton <nickc@cambridge.redhat.com> * gas/arm/arm.exp: Replace deprecated command line switches Index: gas/testsuite/gas/mips/mips.exp =================================================================== RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v retrieving revision 1.32 diff -u -p -r1.32 mips.exp --- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32 +++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000 @@ -122,6 +122,7 @@ if { [istarget mips--] } then { run_dump_test "mul" } run_dump_test "rol" + run_dump_test "rol64" if !$aout { run_dump_test "sb" } run_dump_test "trunc" if !$aout { run_dump_test "ulh" } Index: include/opcode/ChangeLog =================================================================== RCS file: /cvs/src/src/include/opcode/ChangeLog,v retrieving revision 1.167 diff -u -p -r1.167 ChangeLog --- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167 +++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000 @@ -1,3 +1,7 @@ +2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases. + 2002-05-17 Andrey Volkov <avolkov@sources.redhat.com> * h8300.h: Corrected defs of all control regs Index: include/opcode/mips.h =================================================================== RCS file: /cvs/src/src/include/opcode/mips.h,v retrieving revision 1.24 diff -u -p -r1.24 mips.h --- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24 +++ include/opcode/mips.h 21 May 2002 23:32:57 -0000 @@ -526,9 +526,13 @@ enum M_REM_3I, M_REMU_3, M_REMU_3I, + M_DROL, M_ROL, + M_DROL_I, M_ROL_I, + M_DROR, M_ROR, + M_DROR_I, M_ROR_I, M_S_DA, M_S_DOB, Index: opcodes/ChangeLog =================================================================== RCS file: /cvs/src/src/opcodes/ChangeLog,v retrieving revision 1.447 diff -u -p -r1.447 ChangeLog --- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447 +++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000 @@ -1,3 +1,7 @@ +2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros. + Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com> * disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh. Index: opcodes/mips-opc.c =================================================================== RCS file: /cvs/src/src/opcodes/mips-opc.c,v retrieving revision 1.32 diff -u -p -r1.32 mips-opc.c --- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32 +++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000 @@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s\|RD_t\|WR_HILO, I3 }, {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 }, {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 }, +{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 }, +{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 }, +{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 }, +{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 }, {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d\|RD_t\|RD_s, I3 }, {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d\|RD_t, I3 }, {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d\|RD_t\|RD_s, I3 }, /* dsllv */	25 years ago
Joern Rennecke	1c509ca821	print_insn_sh cleanup: include: * dis-asm.h (print_insn_shl, print_insn_sh64l): Remove prototype. gdb: * sh-tdep.c (gdb_print_insn_sh64): Delete. (gdb_print_insn_sh): Just set info->endian and use print_insn_sh. (sh_gdbarch_init): Always use gdb_print_insn_sh. opcodes: * disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh. * sh-dis.c (LITTLE_BIT): Delete. (print_insn_sh, print_insn_shl): Deleted. (print_insn_shx): Renamed to (print_insn_sh). No longer static. Handle SHmedia instructions. Use info->endian to determine endianness. * sh64-dis.c (print_insn_sh64, print_insn_sh64l): Delete. (print_insn_sh64x): No longer static. Renamed to (print_insn_sh64). Removed pfun_compact and endian arguments. If we got an uneven address to indicate SHmedia, adjust it. Return -2 for SHcompact instructions. sim/sh64: * sim-if.c (sh64_disassemble_insn): Use print_insn_sh instead of print_insn_shl.	25 years ago
Alan Modra	81172ff2bd	* acinclude.m4 (AM_INSTALL_LIBBFD): Fake to fool autotools. * configure.in: Invoke AM_INSTALL_LIBBFD. * Makefile.am (install-data-local): Move to.. (install_libopcodes): .. New target. (uninstall_libopcodes): Likewise. (install-bfdlibLTLIBRARIES): Likewise. (uninstall-bfdlibLTLIBRARIES): Likewise. (bfdlibdir): New. (bfdincludedir): New. (lib_LTLIBRARIES): Rename to bfdlib_LTLIBRARIES. * aclocal.m4: Regenerate. * configure: Regenerate. * Makefile.in: Regenerate.	25 years ago
Nick Clifton	a978a3e5d8	Regernate cgen built files.	25 years ago

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533 Commits (ccc8590d3aecf4e3e2ee5ab30eba7f8598625e9d)