binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Jonathan Larmour	53f541af8d	* gencode.c (tab): Avoid inserting code before variables all declared.	22 years ago
Corinna Vinschen	ae0a84af70	* gencode.c (movua.l): Compensate for endianness. * interp.c (RAISE_EXCEPTION_IF_IN_DELAY_SLOT): New macro. (in_delay_slot): New flag variable. (Delay_Slot): Set in_delay_slot. (sim_resume): Reset in_delay_slot after leaving code switch. * gencode.c (op tab): Call RAISE_EXCEPTION_IF_IN_DELAY_SLOT for all instructions not allowed in delay slots. Commited by Corinna Vinschen <vinschen@redhat.com> Introduce SH2a support. * interp.c: Change type of jump table to short. Add various macros. (sim_load): Save the bfd machine code. (sim_create_inferior): Ditto. (union saved_state_type): Add tbr, ibnr and ibcr registers. Move bfd_mach to end of struct. Add regstack pointer. (init_dsp): Don't swap contents of sh_dsp_table any more. Instead use it directly in its own switch statement. Allocate space for 512 register banks. (do_long_move_insn): New function. (do_blog_insn): Ditto. (trap): Use trap #13 and trap #14 to set ibnr and ibcr. * gencode.c: Move movx/movy insns into separate switch statement. (op tab): Add sh2a insns. Reject instructions that are disabled on that chip. (gensim_caselist): Generate default case here instead of in caller. (gensim): Generate two separate switch statements. Call gensim_caselist once for each (for movsxy_tab and for tab). Add tokens for r15 and multiple regs. (conflict_warn, warn_conflicts): Add for debugging.	22 years ago
Joern Rennecke	a134f341e6	* gencode.c (tab): For shad snd shld, fix result for (op1 < 0 && shift_amount == 0).	22 years ago
Michael Snyder	915213a4d5	2004-02-02 Michael Snyder <msnyder@redhat.com> * gencode.c (movua.l): Set thislock to 0, not n.	23 years ago
Michael Snyder	3e5117978b	2004-02-12 Michael Snyder <msnyder@redhat.com> * gencode.c (table): Change from char to short. (dumptable): Change generated table from char to short. * interp.c (sh_jump_table, sh_dsp_table, ppi_table): char to short. (init_dsp): Compute size of sh_dsp_table. (sim_resume): Change jump_table from char to short.	23 years ago
Michael Snyder	0145ab2e52	2004-01-27 Michael Snyder <msnyder@redhat.com> * gencode.c: (op tab): Some refs and defs fixes. "fsrra" -> "fsrra <FREG_N>". "sleep": replace array ref with array addr. "trapa": ditto.	23 years ago
Michael Snyder	4ae0cff4ca	2004-01-27 Michael Snyder <msnyder@redhat.com> * gencode.c: Comment and whitespace clean-ups.	23 years ago
Michael Snyder	87acb4a7d1	2004-01-07 Michael Snyder <msnyder@redhat.com> * gencode.c: Whitespace cleanup. * interp.c: Ditto.	23 years ago
Michael Snyder	86bc60ebf4	2004-01-07 Michael Snyder <msnyder@redhat.com> * gencode.c: Replace 'Hitachi' with 'Renesas'. (op tab): Add new instructions for sh4a, DBR, SBR. (expand_opcode): Add handling for new movxy combinations. (gensym_caselist): Ditto. (expand_ppi_movxy): Remove movx/movy expansions, now handled in expand_opcode. (gensym): Add some helpful macros. (expand_ppi_code): Flatten loop for simplicity, tweak for 12-bit instead of 8-bit table (some insns are ambiguous to 8 bits). (ppi_gensim, main): Generate 12-bit instead of 8-bit ppi table. * interp.c: Replace 'Hitachi' with 'Renesas'. (union saved_state_type): Add dbr, sgr, ldst. (get_loop_bounds_ext): New function. (init_dsp): Add bfd_mach_sh4al_dsp. (sim_resume): Handle extended loop bounds.	23 years ago
Michael Snyder	673fc5d0a7	2003-12-18 Michael Snyder <msnyder@redhat.com> * gencode.c (expand_opcode): Simplify and reorganize. Eliminate "shift" parameter. Eliminate "4 bits at a time" assumption. Flatten switch statement to a single level. Add "eeee" token for even-numbered registers. (bton): Delete. (fsca): Use "eeee" token. (ppi_moves): Rename to "expand_ppi_movxy". Do the ddt [movx/movy] expansion here, as well as the ppi expansion. (gensim_caselist): Accept 'eeee' along with 'nnnn'.	23 years ago
Joern Rennecke	794cd17b28	* interp.c (fsca_s, fsrra_s): New functions. * gencode.c (tab): Add entries for fsca and fsrra. (expand_opcode): Allow variable length n / m fields.	23 years ago
Michael Snyder	d1789acece	2003-08-11 Shrinivas Atre <shrinivasa@KPITCummins.com> * sim/sh/gencode.c ( tab[] ): Addition of MAC.L handler and correction for MAC.W handler * sim/sh/interp.c ( macl ): New Function. Implementation of MAC.L handler.	23 years ago
Michael Snyder	240f98d342	2003-08-07 Michael Snyder <msnyder@redhat.com> * gencode.c (expand_ppi_code): Comment spelling fix.	23 years ago
Michael Snyder	437b0e60a1	2003-07-25 Michael Snyder <msnyder@redhat.com> * gencode.c (pshl): Change < to <= (shift by 16 is allowed). Cast argument of >> to unsigned to prevent sign extension. (psha): Change < to <= (shift by 32 is allowed).	23 years ago
Michael Snyder	32fcda6a20	2003-07-24 Michael Snyder <msnyder@redhat.com> * gencode.c: Fix typo in comment.	23 years ago
Michael Snyder	e343a93ac0	2003-07-23 Michael Snyder <msnyder@redhat.com> * gencode.c: A few more fix-ups of refs and defs. (frchg): Raise SIGILL if in double-precision mode. (ldtlb): We don't simulate cache, so this is a no-op. (movsxy_tab): Correct a few bit pattern errors.	23 years ago
Michael Snyder	1b606171ad	2003-07-09 Michael Snyder <msnyder@redhat.com> * gencode.c (prnd): Clear LSW of result to zeros.	23 years ago
Michael Snyder	fcfae95cf8	2003-07-09 Michael Snyder <msnyder@redhat.com> * gencode.c (pmuls): Expression is mis-parenthesized.	23 years ago
Michael Snyder	c13a4caaf8	2003-07-09 Michael Snyder <msnyder@redhat.com> * gencode.c (ppi_gensim): For a conditional ppi insn, if the condition is false, we want to return (not break). A break will take us to the end of the function where registers will be updated, whereas the desired outcome is for nothing to change.	23 years ago
Michael Snyder	b939d772c1	2003-06-27 Michael Snyder <msnyder@redhat.com> * gencode.c (op tab): Some fix-ups of refs and defs. (ocbi, ocbp): Cache not simulated, but may cause memory fault. (gensym_caselist): Add default case to switch statement. (expand_ppi_code): Add default case to switch statement.	23 years ago
Michael Snyder	d2f18ae42a	2003-06-27 Michael Snyder <msnyder@redhat.com> * gencode.c (op tab): Implement movca.l.	23 years ago
Michael Snyder	9e1d0fc1a1	2003-06-27 Michael Snyder <msnyder@redhat.com> * gencode.c (op movsxy_tab): Fix an error in the bit pattern.	23 years ago
Michael Snyder	15dee5d561	2003-06-27 Michael Snyder <msnyder@redhat.com> * gencode.c (gensim_caselist): The movy instructions use registers R6 and R7 (not R4 and R5 like the movx insns).	23 years ago
Michael Snyder	e53a5a69d7	2003-07-03 Michael Snyder <msnyder@redhat.com> * gencode.c (movs): Fix a couple of text transpositions.	23 years ago
Michael Snyder	0b2828595e	2003-06-27 Michael Snyder <msnyder@redhat.com> * gencode.c (op movsxy_tab): Fix up some copy/paste errors in name: s/REG_x/REG_y/.	24 years ago
Michael Snyder	8dc30ef74a	2003-06-27 Michael Snyder <msnyder@redhat.com> * gencode.c (op tab): Move misplaced semicolon.	24 years ago
Nick Clifton	2bc8946db8	Commit Sh2E addition	24 years ago
Joern Rennecke	fd8f4948fe	gcc uses trap 33 for profiling, but the simulator didn't support it. This patch fixes the gcc.dg/nest.c failures for sh-elf. Fri Oct 11 16:22:28 2002 J"orn Rennecke <joern.rennecke@superh.com> * interp.c (trap): Return int. Take extra parameter for address of the trap instruction. Changed all callers. Add case 33 for profiling. * gencode.c (trapa): Handle trap 33 using the trap function. Add read of vector for generic traps.	24 years ago
Ben Elliston	8f1e3ff591	* pendanticism 2000-10-24 Ben Elliston <bje@redhat.com> * gencode.c (tab): Delimit strings with commas where applicable.	26 years ago
Joern Rennecke	63978407cb	sh-dsp support, simulator speedup by using host byte order: sim: * Makefile.in (interp.o): Depends on ppi.c . (ppi.c): New rule. * gencode.c (printonmatch, think, genopc): Deleted. (MAX_NR_STUFF): Now 42. (tab): Add SH-DSP CPU instructions. Amalgamate ldc / stc / lds / sts instructions with similar bit patterns. Fix opcodes of stc Rm_BANK,@-<REG_N>. Fix semantics of lds.l @<REG_N>+,MACH (no sign extend). (movsxy_tab): New array. For movs, change MMMM field to GGGG, and mmmm field to MMMM. Added entries for movx, movy and parallel processing insns. (ppi_tab): New array. (qfunc): Stabilize sort. (expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy. Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'. (dumptable): Now takes three arguments. Changed all callers. Emit just one contigous jump table. (filltable): Now takes an argument. Changed all callers. Make index static. (ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions. (gensim_caselist): New function, broken out of gensim. Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'. Handle ref '9'. (gensim): Handle 'N' in code field and '8' in refs field. Call gensim_caselist - twice. (ppi_index): New static variable. (main): Unsupport default action. Add dsp support for -x / -s option. Add -p option. * interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare. (saved_state_type): Rearrange to allow amalgamated ldc / stc / lds / sts to work efficiently. (target_dsp): New static variable. (GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change. (FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise. (SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise. (RS, RE, MOD, MOD_ME, DSP_R): Likewise. (set_fpscr1): Likewise. Use target_dsp to check for dsp. (MOD_MSi, SIG_BUS_FETCH): Deleted. (CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros. (SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise. (SET_MOD): Reflect saved_state_type change. Set MOD_DELTA instead of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME. (set_sr): Reflect saved_state_type change. Fix SR_RB handling. Use SET_MOD. (MA, L, TL, TB): Now controlled by ACE_FAST. (SEXT32): Just cast to int. (SIGN32): Fixed to only shift by 31. (CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0. (ppi_insn): Declare. (ppi.c): Include. (init_dsp): Set target_dsp. When it changes, switch end of sh_jump_table with sh_dsp_table. (sim_resume) Don't declare sh_jump_table0. Use sh_jump_table instead. Don't Declare PR if it's #defined. Fix single-stepping (Was broken in Mar 6 16:59:10 patch). (sim_store_register, sim_read_register): Translate accesses to reflect saved_state_type change. * interp.c (set_sr): Set sr. (SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros. (set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp. (DSP_R): Fix definition. (sim_resume): Remove outdated SET_SR use. * interp.c (saved_state): New members for struct member asregs: rs, re, insn_end, xram_start, yram_start. (struct loop_bounds): New struct. (SKIP_INSN): New macro. (get_loop_bounds): New function. (endianw): Renamed to global_endianw. (maskw): negated bits. (PC): Now insn_ptr. (SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros. (RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise. (M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise. (SIG_BUS_FETCH): Likewise (raise_exception, riat_fast): New functions. (raise_buserror, sim_stop): Use raise_exception. (PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start. (BUSERROR, WRITE_BUSERROR, READ_BUSERROR): Reverse sense of mask argument. (FP_OP, set_dr): Use RAISE_EXCEPTION. (wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast): Declare. Remove redundant masking. (wwat_fast, rwat_fast): Add argument endianw. Changed callers. (MA): Updated for change pc -> PC. (Delay_Slot): Use RIAT. (empty): Deleted. (trap): Remove argument little_endian. Add argument endianw. Changed all callers. Use raise_exception. (macw): Add argument endainw. Changed all callers. (init_dsp): New function, extended after broken out of init_pointers. (sim_resume): Replace pc with insn_ptr. Replace little_endian with endianw. Replace nia with nip. Reverse sense of maskb / maskw / maskl. Implement logic for zero-overhead loops. Don't try to interpret garbage when getting a SIGBUS at insn fetch. (sim_open): Call init_dsp. * gencode.c (tab): Use SET_NIP instead of nia = . Use PH2T / PT2H / RAISE_EXCEPTION where appropriate. Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr. * interp.c (sim_store_register, sim_fetch_register): Do proper endianness switch. * interp.c (saved_state_type): New members for struct member asregs: xymem_select, xmem, ymem, xmem_offset, ymem_offset. (special_address): Delete. (BUSERROR): Now a two-argument predicate. (PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros. (wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete. (process_wlat_addr, process_wwat_addr): New functions. (process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise. (process_rbat_addr): Likewise. (wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR. (rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete. (rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR. (RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions. (do_rdat, trap): Delete SLOW code. (SEXT32, SIGN32): New macros. (swap, swap16): Now integer in - integer out. Changed all callers. (strswaplen, strnswap): Delete SLOW versions. (init_pointers): Initialize dsp memory selection (preliminary). (sim_store_register, sim_fetch_register): Use swap instead of big / little endian read / write functions. * interp.c (maskl): Deleted. (endianw, endianb): New variables. (special_address): Now inline. (bp_holder): Put raising of buserror there, rename to: (raise_buserror). (BUSERROR): Now yields a value. Changed all users. (wbat_big): Delete. (wlat_fast, wwat_fast, wbat_fast): New functions. (rlat_fast, rwat_fast, rbat_fast): Likewise. (RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions. (do_rdat, do_wdat): Likewise. Take maskl argument instead of little_endian one. Changed caller macros. (swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly. (strswaplen, strnswap): New functions. (trap): Use them to fix up endian mismatches; disable SYS_execve and SYS_execv; fix double address translation for SYS_pipe and SYS_stat. (sym_write, sym_read): Add endianness translation. (sym_store_register, sym_fetch_register): Add maskl local variable. (sim_open): Set endianw and endianb. gdb: * sh-tdep.c (sh_dsp_reg_names, sh3_dsp_reg_names): New arrays. (sh_processor_type_table): Add entries for bfd_mach_sh_dsp and bfd_mach_sh3_dsp. (sh_show_regs): Floating point registers are called fr0-fr15. For sh4, display fpul, fpscr and fr0-fr15 / dr0-dr14 as appropriate. Handle sh-dsp and sh3-dsp. config/sh/tm-sh.h (REGISTER_VIRTUAL_TYPE): sh-dsp / sh3-dsp don't have floating point registers. (DSR_REGNUM, A0G_REGNUM, A0_REGNUM, A1G_REGNUM, A1_REGNUM): Define. (M0_REGNUM, M1_REGNUM, X0_REGNUM, X1_REGNUM, Y0_REGNUM): Likewise. (Y1_REGNUM, MOD_REGNUM, RS_REGNUM, RE_REGNUM, R0B_REGNUM): Likewise.	27 years ago
Jason Molenda	104c1213b4	import gdb-1999-08-30 snapshot	27 years ago
Stan Shebs	7a292a7adf	import gdb-19990422 snapshot	28 years ago
Stan Shebs	c906108c21	Initial creation of sourceware repository	28 years ago
Stan Shebs	071ea11e85	Initial creation of sourceware repository	28 years ago
Andrew Cagney	4de6b5d361	Merge SH4 branch simulator in to devo.	29 years ago
J.T. Conklin	2434e38489	* gencode.c (tab): Added several sh3 opcodes. (think): Added printonmatch for A_SSR and A_SPC. * interp.c (SSR, SPC): Added definitions. (saved_state_type): Added ssr and spc registers.	31 years ago
Jim Wilson	9dfb65e661	* gencode.c (tab): In shad/shld definitions, negate R[m] before the and operation instead of after. For shad delete cast. For shld use UR instead of R and delete cast.	31 years ago
Stu Grossman	fe2f8313f0	* gencode.c: jsr, bsr and bsrf actually save pc+4 in pr, and rts actually uses pr+0.	31 years ago
Stu Grossman	9999417ef6	* gencode.c: jsr actually saves pc+4, and rts actually uses pr+0.	31 years ago
Jeff Law	2ca7c3c417	* gencode.c (gensim): abort if an unknown opcode is encountered.	31 years ago
Steve Chamberlain	a43b22b577	Wed May 24 14:07:11 1995 Steve Chamberlain <sac@slash.cygnus.com> * gencode.c (tab): Add bsrf and braf.	32 years ago
Torbjorn Granlund	acae2683a9	Fix for PR 6200 (SUBC problems).	32 years ago
Steve Chamberlain	594266fc8a	New stuff for SH.	34 years ago

43 Commits (caa0503690d27cbcd6fbc1a09caa44ba9f49e29f)