binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Alan Modra	0c0577f6a8	PR26446 UBSAN: tc-csky.c:2618,4022 index out of bounds PR 26446 * csky-opc.h (MAX_OPRND_NUM): Define to 5. (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.	6 years ago
Alan Modra	a1e60a1bdc	PR26449, PR26450 UBSAN: frv-ibld.c:135 left shift Eh well, I guess the code didn't quite live up to the comment. PR 26449 PR 26450 * cgen-ibld.in (insert_1): Use 1UL in forming mask. (extract_normal): Likewise. (insert_normal): Likewise, and move past zero length test. (put_insn_int_value): Handle mask for zero length, use 1UL. * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.	6 years ago
Cooper Qu	0861f561eb	CSKY: Support attribute section. bfd * elf32-csky.c (csky_archs): Fix arch names. (csky_find_arch_with_name): New. (elf32_csky_merge_attributes): New. (csky_elf_merge_private_bfd_data): Add process of merge attribute section. (elf32_csky_obj_attrs_arg_type): New. (elf32_csky_obj_attrs_handle_unknown): New. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section): Define. (elf_backend_obj_attrs_arg_type): Define. (elf_backend_obj_attrs_section_type): Define. binutils/ * readelf.c (get_csky_section_type_name): New. (get_section_type_name): Add handler for CSKY. (display_csky_attribute): New. (process_arch_specific): Add handler for CSKY. * testsuite/binutils-all/strip-3.d: Remove .csky.attributes section. elfcpp/ * elfcpp.h (enum SHT): New enum SHT_CSKY_ATTRIBUTES. gas/ * gas/config/tc-csky.c (md_begin): Set attributes. (isa_flag): Change type to unsigned 64 bits. (struct csky_cpu_info): Likewise. (struct csky_macro_info): Likewise. (set_csky_attribute): New. * testsuite/gas/csky/802j.d: Ignore .csky.attributes section. * testsuite/gas/csky/all.d: Likewise. * testsuite/gas/csky/bsr1.d: Likewise. * testsuite/gas/csky/csky_vdsp.d: Likewise. * testsuite/gas/csky/cskyv2_all.d: Likewise. * testsuite/gas/csky/cskyv2_ck803r2.d: Likewise. * testsuite/gas/csky/cskyv2_ck860.d: Likewise. * testsuite/gas/csky/cskyv2_dsp.d: Likewise. * testsuite/gas/csky/cskyv2_elrw.d: Likewise. * testsuite/gas/csky/cskyv2_float.d: Likewise. * testsuite/gas/csky/enhance_dsp.d: Likewise. * testsuite/gas/csky/java.d: Likewise. * testsuite/gas/csky/v1_float.d: Likewise. * testsuite/gas/csky/v2_float_part1.d: Likewise. * testsuite/gas/csky/v2_float_part2.d: Likewise. * testsuite/gas/csky/v2_tls_gd.d: Likewise. * testsuite/gas/csky/v2_tls_ie.d: Likewise. * testsuite/gas/csky/v2_tls_ld.d: Likewise. * testsuite/gas/csky/v2_tls_le.d: Likewise. * testsuite/gas/elf/elf.exp: Add handler for CSKY. * testsuite/gas/elf/section2.e-csky: New. include/ * elf/csky.h (SHT_CSKY_ATTRIBUTES): Define. (Tag_CSKY_ARCH_NAME): New enum constant. (Tag_CSKY_CPU_NAME): Likewise. (Tag_CSKY_ISA_FLAGS): Likewise. (Tag_CSKY_DSP_VERSION): Likewise. (Tag_CSKY_VDSP_VERSION): Likewise. (Tag_CSKY_FPU_VERSION): Likewise. (Tag_CSKY_FPU_ABI): Likewise. (Tag_CSKY_FPU_ROUNDING): Likewise. (Tag_CSKY_FPU_DENORMAL): Likewise. (Tag_CSKY_FPU_Exception): Likewise. (Tag_CSKY_FPU_NUMBER_MODULE): Likewise. (Tag_CSKY_FPU_HARDFP): Likewise. (Tag_CSKY_MAX): Likewise. (VAL_CSKY_DSP_VERSION_EXTENSION): Likewise. (VAL_CSKY_DSP_VERSION_2): Likewise. (VAL_CSKY_VDSP_VERSION_1): Likewise. (VAL_CSKY_VDSP_VERSION_2): Likewise. (VAL_CSKY_FPU_ABI_SOFT): Likewise. (VAL_CSKY_FPU_ABI_SOFTFP): Likewise. (VAL_CSKY_FPU_ABI_HARD): Likewise. (VAL_CSKY_FPU_HARDFP_HALF): Likewise. (VAL_CSKY_FPU_HARDFP_SINGLE): Likewise. (VAL_CSKY_FPU_HARDFP_DOUBLE): Likewise. * opcode/csky.h (CSKY_ISA_VDSP_V2): Define. CSKYV1_ISA_E1: Change to long constant type. CSKYV2_ISA_E1: Likewise. CSKYV2_ISA_1E2: Likewise. CSKYV2_ISA_2E3: Likewise. CSKYV2_ISA_3E7: Likewise. CSKYV2_ISA_7E10: Likewise. CSKYV2_ISA_3E3R1: Likewise. CSKYV2_ISA_3E3R2: Likewise. CSKYV2_ISA_10E60: Likewise. CSKY_ISA_TRUST: Likewise. CSKY_ISA_CACHE: Likewise. CSKY_ISA_NVIC: Likewise. CSKY_ISA_CP: Likewise. CSKY_ISA_MP: Likewise. CSKY_ISA_MP_1E2: Likewise. CSKY_ISA_JAVA: Likewise. CSKY_ISA_MAC: Likewise. CSKY_ISA_MAC_DSP: Likewise. CSKY_ISA_DSP: Likewise. CSKY_ISA_DSP_1E2: Likewise. CSKY_ISA_DSP_ENHANCE: Likewise. CSKY_ISA_FLOAT_E1: Likewise. CSKY_ISA_FLOAT_1E2: Likewise. CSKY_ISA_FLOAT_1E3: Likewise. CSKY_ISA_FLOAT_3E4: Likewise. CSKY_ISA_VDSP: Likewise. ld/ * emulparams/cskyelf.sh: Support attribute section. * testsuite/ld-csky/tls-le-v1.d: Match .csky.attributes section. * ld/testsuite/ld-csky/tls-le.d: Likewise. * testsuite/ld-elf/non-contiguous.ld: Ignore .csky.attributes section. opcodes/ * csky-dis.c (CSKY_DEFAULT_ISA): Define. (csky_dis_info): Add member isa. (csky_find_inst_info): Skip instructions that do not belong to current CPU. (csky_get_disassembler): Get infomation from attribute section. (print_insn_csky): Set defualt ISA flag. * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2. * csky-opc.h (struct csky_opcode): Change isa_flag16 and isa_flag32'type to unsigned 64 bits.	6 years ago
Jose E. Marchesi	31b3f3e6e4	opcodes: Add missing entries to ebpf_isa_attr opcodes/ * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.	6 years ago
David Faust	4449c81a85	bpf: add xBPF ISA This patch adds support for xBPF, another ISA targetting the BPF virtual architecture. For now, the primary difference between eBPF and xBPF is that xBPF supports indirect calls through the 'call %reg' form of the call instruction. bfd/ * archures.c (bfd_mach_xbpf): Define. * bfd-in2.h: Regenerate. * cpu-bpf.c (bfd_xbpf_arch) New. (bfd_bpf_arch) Update next in list field to point to xbpf arch. cpu/ * bpf.cpu (arch bpf): Add xbpf mach and isas. (define-xbpf-isa) New pmacro. (all-isas) Add xbpfle,xbpfbe. (endian-isas): New pmacro. (mach xbpf): New. (model xbpf-def): Likewise. (h-gpr): Add xbpf mach. (f-dstle, f-srcle, dstle, srcle): Add xbpfle isa. (f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa. (define-alu-insn-un): Use new endian-isas pmacro. (define-alu-insn-bin, define-alu-insn-mov): Likewise. (define-endian-insn, define-lddw): Likewise. (dlind, dxli, dxsi, dsti): Likewise. (define-cond-jump-insn, define-call-insn): Likewise. (define-atomic-insns): Likewise. gas/ * config/tc-bpf.c: Add option -mxbpf to select xbpf isa. * testsuite/gas/bpf/indcall-1.d: New file. * testsuite/gas/bpf/indcall-1.s: Likewise. * testsuite/gas/bpf/indcall-bad-1.l: Likewise. * testsuite/gas/bpf/indcall-bad-1.s: Likewise. * testsuite/gas/bpf/bpf.exp: Run new tests. opcodes/ * bpf-desc.c: Regenerate. * bpf-desc.h: Likewise. * bpf-opc.c: Likewise. * bpf-opc.h: Likewise. * disassemble.c (disassemble_init_for_target): Set bits for xBPF ISA when appropriate.	6 years ago
Alan Modra	8640c87dcd	PR26504, ASAN: parse_disassembler_options vax-dis.c:142 PR 26504 * vax-dis.c (parse_disassembler_options): Always add at least one to entry_addr_total_slots.	6 years ago
Cooper Qu	531c73a37b	CSKY: Add new arch CK860. bfd/ * bfd-in2.h (bfd_mach_ck860): New. * cpu-csky.c (arch_info_struct): Add item for CK860. gas/ * config/tc-csky.c (csky_archs): Add item for CK860, change ck810 and ck807's arch_flag. (csky_cpus): Add item for CK860. (md_begin): Enable DSP for CK810 and CK807 by default. (md_apply_fix): Fix CKCORE_TLS_IE32 relocation failure. * gas/testsuite/gas/csky/cskyv2_all.d: Change 'sync 0' to 'sync'. * gas/testsuite/gas/csky/cskyv2_all.s: Likewise. * gas/testsuite/gas/csky/cskyv2_ck860.d: New. * gas/testsuite/gas/csky/cskyv2_ck860.s: New. * gas/testsuite/gas/csky/enhance_dsp.d: Change plsli.u16 to plsli.16. * gas/testsuite/gas/csky/enhance_dsp.s: Likewise. include/ * opcode/csky.h (CSKYV2_ISA_10E60): New. (CSKY_ARCH_860): New. opcode/ * csky-dis.c (csky_find_inst_info): Skip CK860's instructions in other CPUs to speed up disassembling. * csky-opc.h (csky_v2_opcodes): Add CK860's instructions, Change plsli.u16 to plsli.16, change sync's operand format. Change-Id: I80ec1a9c0cc600d668082a9b91ae6d45b33ec0fc	6 years ago
Cooper Qu	d04aee0f41	CSKY: Add ck803r2 series cpu. gas/ * config/tc-csky.c (CSKY_ISA_803R2): New. (csky_archs): Add ck803r2 series. (md_begin): Fix warning about -medsp. (csky_get_freg_val): Support lowercase of fpu register name. * testsuite/gas/csky/cskyv2_ck803r2.s: New file. * testsuite/gas/csky/cskyv2_ck803r2.d: New file. include/ * csky.h (CSKYV2_ISA_3E3R2): New. opcodes/ * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.	6 years ago
Nick Clifton	ccf61261eb	Fix problems with the AArch64 linker exposed by testing it with sanitization enabled. bfd * elfnn-aarch64.c (_bfd_aarch64_erratum_835769_scan): Only sort the data map if there are entries in it. (_bfd_aarch64_erratum_843419_scan): Likewise. opcodes * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF symbols.	6 years ago
Cooper Qu	d285ba8d06	CSKY: Support two operands form for bloop. gas/ * config/tc-csky.c (csky_insn_info): Add member last_isize. (md_assemble): Assign value to csky_insn.last_isize. * testsuite/gas/csky/enhance_dsp.d: Test bloop's two operands form. * testsuite/gas/csky/enhance_dsp.s: Likewise. opcodes/ * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.	6 years ago
Alan Modra	18a8a00ebe	Correct vcmpsq, vcmpuq and xvtlsbb BF field These shouldn't be optional. The record form of vector instructions set CR6, giving an expectation that omitting BF should be the same as specifying CR6. opcodes/ * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq, vcmpuq and xvtlsbb. gas/ * testsuite/gas/ppc/int128.s: Correct vcmpuq. * testsuite/gas/ppc/int128.d: Update. * testsuite/gas/ppc/xvtlsbb.d: Update.	6 years ago
Peter Bergner	587a437176	Add ChangeLog entries for previous commit.	6 years ago
Alex Coplan	2e49fd1edf	aarch64: Add support for MPAM system registers This patch adds support for the system registers introduced in the Armv8-A MPAM extension. See https://developer.arm.com/documentation/ddi0598/latest for the Arm ARM supplement documenting this extension. gas/ChangeLog: * testsuite/gas/aarch64/mpam-bad.d: New test. * testsuite/gas/aarch64/mpam-bad.l: Error output. * testsuite/gas/aarch64/mpam-bad.s: Input. * testsuite/gas/aarch64/mpam.d: New test. * testsuite/gas/aarch64/mpam.s: Input. opcodes/ChangeLog: * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.	6 years ago
Nick Clifton	79ddc88496	Updated Serbian and Russian translations for various sub-directories	6 years ago
Alan Modra	08770ec259	PowerPC CELL cctp* * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.	6 years ago
Przemyslaw Wirkus	f7cb161ea6	[aarch64] GAS doesn't validate the architecture version for any tlbi registers. Fixed with this patch. * gas/config/tc-aarch64.c (parse_sys_reg): Call to aarch64_sys_ins_reg_supported_p instead of aarch64_sys_reg_supported_p. (parse_sys_ins_reg): Add aarch64_sys_reg_deprecated_p check. * include/opcode/aarch64.h (aarch64_sys_reg_deprecated_p): Functions paramaters changed. (aarch64_sys_reg_supported_p): Function removed. (aarch64_sys_ins_reg_supported_p): Functions paramaters changed. * opcodes/aarch64-opc.c (aarch64_print_operand): (aarch64_sys_reg_deprecated_p): Functions paramaters changed. (aarch64_sys_reg_supported_p): Function removed. (aarch64_sys_ins_reg_supported_p): Functions paramaters changed. (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p into this function. * gas/testsuite/gas/aarch64/illegal-sysreg-5.d: New test. * gas/testsuite/gas/aarch64/illegal-sysreg-5.l: New test. * gas/testsuite/gas/aarch64/sysreg-5.s: New test.	6 years ago
Alan Modra	3eb651743e	Implement missing powerpc mtspr and mfspr extended insns * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended instructions.	6 years ago
Alan Modra	8b2742a156	Implement missing powerpc extended mnemonics gas/ * testsuite/gas/ppc/power8.d, * testsuite/gas/ppc/power8.s: Add miso. * testsuite/gas/ppc/power9.d, * testsuite/gas/ppc/power8.s: Add exser, msgsndu, msgclru. opcodes/ * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru. Enable icbt for power5, miso for power8.	6 years ago
Alan Modra	5fbec329ec	Prioritise mtfprd and mtvrd over mtvsrd in PowerPC disassembly gas/ * testsuite/gas/ppc/power8.d: Update. * testsuite/gas/ppc/vsx2.d: Update. opcodes/ * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over mtvsrd, and similarly for mfvsrd.	6 years ago
Christian Groessler	563a322515	Z8k: fix sout/soudb opcodes with direct address Problem found by Tadashi G. Takaoka. 2020-08-04 Christian Groessler <chris@groessler.org> Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com> * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs" opcodes (special "out" to absolute address). * z8k-opc.h: Regenerate. 2020-08-04 Christian Groessler <chris@groessler.org> * gas/testsuite/gas/z8k/inout.d: Adapt to correct encoding of "sout/soutb #imm,reg"	6 years ago
H.J. Lu	41eb8e8885	x86: Add {disp16} pseudo prefix Use Prefix_XXX for pseudo prefixes. Add {disp16} pseudo prefix and replace {disp32} pseudo prefix with {disp16} in 16-bit mode test. Check invalid {disp16}/{disp32} pseudo prefixes. gas/ PR gas/26305 * config/tc-i386.c (_i386_insn::disp_encoding): Add disp_encoding_16bit. (parse_insn): Check Prefix_XXX for pseudo prefixes. Handle {disp16}. (build_modrm_byte): Handle {disp16}. (i386_index_check): Check invalid {disp16} and {disp32} pseudo prefixes. * doc/c-i386.texi: Update {disp32} documentation and document {disp16}. * testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo. * testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16} tests. * testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps tests with 128-byte displacement. Add {disp16} tests. * testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32} vmovaps test. Add (%r13)/(%r13d) tests. * testsuite/gas/i386/x86-64-inval-pseudo.l: New file. * testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise. * testsuite/gas/i386/inval-pseudo.l: Updated. * testsuite/gas/i386/pseudos.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. opcodes/ PR gas/26305 * i386-opc.h (Prefix_Disp8): New. (Prefix_Disp16): Likewise. (Prefix_Disp32): Likewise. (Prefix_Load): Likewise. (Prefix_Store): Likewise. (Prefix_VEX): Likewise. (Prefix_VEX3): Likewise. (Prefix_EVEX): Likewise. (Prefix_REX): Likewise. (Prefix_NoOptimize): Likewise. * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}. * i386-tbl.h: Regenerated.	6 years ago
Andreas Arnez	9811697376	PR26279 Work around maybe-uninitialized warning in s390-mkopc.c In s390-mkopc.c, the function insertExpandedMnemonic() searches for the first occurrence of '' or '$' in the given mnemonic, and, if a match is found, chooses an extension table using a switch() on that character. The switch statement contains a default case that prints an error message and does not set the extension table. Although this case cannot occur, some GCC versions obviously conclude that the extension table might have been left uninitialized after the switch statement and consequently emit maybe-uninitialized warnings for the variables 'ext_table' and 'ext_table_length'. Circumvent the warning by handling the unreachable default case with abort(). opcodes/ s390-mkopc.c (insertExpandedMnemonic): Handle unreachable default case with abort() instead of printing an error message and continuing, to avoid a maybe-uninitialized warning.	6 years ago
Nick Clifton	2dddfa201b	Updated German translation for the opcodes sub-directory	6 years ago
Jan Beulich	bf4ba07ca6	Revert "x86: Don't display eiz with no scale" This reverts commit `04c662e2b6`. In my underlying suggestion I neglected the fact that in those cases (,%eiz,1) is the only visible indication that 32-bit addressing is in effect.	6 years ago
H.J. Lu	04c662e2b6	x86: Don't display eiz with no scale Change 67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef(,%eiz,1),%rbx to 67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef,%rbx in AT&T syntax and 67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR [eiz1+0x89abcdef] to 67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR ds:0x89abcdef in Intel syntax. gas/ PR gas/26237 testsuite/gas/i386/evex-no-scale-64.d: Updated. * testsuite/gas/i386/addr32.d: Likewise. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Don't display eiz with no scale without base nor index registers.	6 years ago
Jan Beulich	f0e8d0bae4	x86: move putop() case labels to restore alphabetic sorting ... as far as non-fall-through behavior permits.	6 years ago
Jan Beulich	c3f5525ff1	x86: make PUSH/POP disassembly uniform Irrespective of their encoding the resulting output should look the same. Therefore wire the handling of PUSH/POP with GPR operands encoded in the main opcode byte to the same logic used for other operands. This frees up yet another macro character.	6 years ago
Jan Beulich	36938cabf0	x86: avoid attaching suffixes to unambiguous insns "Unambiguous" is is in particular taking as reference the assembler, which also accepts certain insns - despite them allowing for varying operand size, and hence in principle being ambiguous - without any suffix. For example, from the very beginning of the life of x86-64 I had trouble understanding why a plain and simple RET had to be printed as RETQ. In case someone really used the 16-bit form, RETW disambiguates the two quite fine.	6 years ago
H.J. Lu	8e58ef803c	x86-64: Zero-extend lower 32 bits displacement to 64 bits Since the addr32 (0x67) prefix zero-extends the lower 32 bits address to 64 bits, change disassembler to zero-extend the lower 32 bits displacement to 64 bits when there is no base nor index registers. gas/ PR gas/26237 * testsuite/gas/i386/addr32.s: Add tests for 32-bit wrapped around address. * testsuite/gas/i386/x86-64-addr32.s: Likewise. * testsuite/gas/i386/addr32.d: Updated. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Without base nor index registers, 32-bit displacement to 64 bits.	6 years ago
Claudiu Zissulescu	570b0ed6d5	arc: Detect usage of illegal double register pairs ARC can use odd-even double register pairs in some selected instructions. Although the GNU assembler doesn't allow even-odd registers to be used, there may be cases when the disassembler is presented with such situation. This patch add a test and detects such cases. opcodes/ 2020-07-14 Claudiu Zissulescu <claziss@gmail.com> * arc-dis.c (print_insn_arc): Detect and emit a warning when a faulty double register pair is detected. binutils/ 2020-07-14 Claudiu Zissulescu <claziss@gmail.com> * testsuite/binutils-all/arc/double_regs.s: New test. * testsuite/binutils-all/arc/objdump.exp: Add the above test. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>	6 years ago
Jan Beulich	bfbd943845	x86/Intel: debug registers are named DRn %db<n> is an AT&T invention; the Intel documentation and MASM have only ever specified DRn (in line with CRn and TRn). (In principle gas also shouldn't accept the names in Intel mode, but at least for now I've kept things as they are. Perhaps as a first step this should just be warned about.)	6 years ago
Jan Beulich	78467458dd	x86: drop Rm and the 'L' macro Rm (and hence OP_R()) can be dropped by making 'Z' force modrm.mod to 3 (for OP_E()) instead of ignoring it. While at it move 'Z' handling to its designated place (after 'Y'; 'W' handling will be moved by a later change). Moves to/from TRn are illegal in 64-bit mode and thus get converted to honor this at the same time (also getting them in line with moves to/from CRn/DRn ModRM.mod handling wise). This then also frees up the L macro.	6 years ago
Jan Beulich	464d2b6568	x86: drop Rdq, Rd, and MaskR Rdq, Rd, and MaskR can be replaced by Edq, Ed / Rm, and MaskE respectively, as OP_R() doesn't enforce ModRM.mod == 3, and hence where MOD matters but hasn't been decoded yet it needs to be anyway. (The case of converting to Rm is temporary until a subsequent change.)	6 years ago
Jan Beulich	035e7389dd	x86: simplify decode of opcodes valid only without any (embedded) prefix In this case there's no need to go through prefix_table[] at all - the .prefix_requirement == PREFIX_OPCODE machinery takes care of this case already. A couple of further adjustments are needed though: - Gv / Ev and alike then can't be used (needs to be Gdq / Edq instead), - dq_mode and friends shouldn't lead to PREFIX_DATA getting set in used_prefixes.	6 years ago
Jan Beulich	bb5b3501b3	x86: also use %BW / %DQ for kshift*	6 years ago
Jan Beulich	7531c61332	x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].	6 years ago
Jan Beulich	17d3c7eccd	x86: drop further EVEX table entries that can be served by VEX ones A few cases were missed by `6df22cf64c` ("x86: drop EVEX table entries that can be served by VEX ones").	6 years ago
Jan Beulich	41f5efc685	x86: drop need_vex_reg It was quite odd for the prior operand handling to have to clear this flag for the actual operand handling to print nothing. Have the actual operand handling determine whether the operand is actually present. With this {d,q}_scalar_swap_mode become unused and hence also get dropped.	6 years ago
Jan Beulich	89e65d17e3	x86: drop Vex128 and Vex256 These are only used when VEX.L or EVEX.L'L have already been decoded, and hence the "normal" length dependent name determination is quite fine. Adjust a few enumerators to make clear that vex_len_table[] has been consulted; be consistent and do so for all f128 and i128 insns in one go.	6 years ago
Jan Beulich	492a76aab5	x86: replace %LW by %DQ This makes more visible what the two alternatives will be that result from this macro.	6 years ago
Jan Beulich	059edf8b97	x86: merge/move logic determining the EVEX disp8 shift Fold redundant case blocks and move the extra adjustments logic into the single case block that actually needs it - there's no need to go through the extra logic for all the other cases. Also utilize there that vex.b cannot be set at this point, due to earlier logic. Reduce the comment there, which was partly stale anyway.	6 years ago
Jan Beulich	4726e9a479	x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W} Unlike the earlier ones these also need their operands adjusted. Replace the (mis-described: there's nothing "scalar" here) {b,w}_scalar_mode by a single new mode, with the actual unit width controlled by EVEX.W.	6 years ago
Jan Beulich	b24d668c07	x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel mode The operands don't allow disambiguating the insn in 64-bit mode, and hence suffixes need to be emitted not just in AT&T mode. Achieve this by re-using %LQ while dropping PCMPESTR_Fixup().	6 years ago
Jan Beulich	c4de76066e	x86: fold VCMP_Fixup() into CMP_Fixup() There's no reason to have two functions and two tables, when the AVX functionality here is a proper superset of the SSE one.	6 years ago
Jan Beulich	9ab00b61a9	x86: don't disassemble MOVBE with two suffixes MOVBE_Fixup() is entirely redundant with the S macro already used on the mnemonics, leading to double suffixes in suffix-always mode. Drop the function.	6 years ago
Jan Beulich	2875b28aa8	x86: avoid attaching suffix to register-only CRC32 Just like other insns with GPR operands, CRC32 with only register operands should not get a suffix added unless in suffix-always mode. Do away with CRC32_Fixup() altogether, using other more generic logic instead.	6 years ago
Jan Beulich	e184e6110e	x86-64: don't hide an empty but meaningless REX prefix Unlike for non-zero values passed to USED_REX(), where rex_used gets updated only when the respective bit was actually set in the encoding, zero getting passed in is not further guarded, yet such a (potentially "empty") REX prefix takes effect only when there are registers numbered 4 and up.	6 years ago
Jan Beulich	e8b5d5f971	x86: drop dead code from OP_IMREG() There's only a very limited set of modes that this function gets invoked with - avoid it being more generic than it needs to be. This may, down the road, allow actually doing away with the function altogether. This eliminates a first improperly used "USED_REX (0)".	6 years ago
Lili Cui	260cd341da	x86: Add support for Intel AMX instructions gas/ * doc/c-i386.texi: Document amx_int8, amx_bf16 and amx_tile. * config/tc-i386.c (i386_error): Add invalid_sib_address. (cpu_arch): Add .amx_int8, .amx_bf16 and .amx_tile. (cpu_noarch): Add noamx_int8, noamx_bf16 and noamx_tile. (match_simd_size): Add tmmword check. (operand_type_match): Add tmmword. (type_names): Add rTMM. (i386_error): Add invalid_tmm_register_set. (check_VecOperands): Handle invalid_sib_address and invalid_tmm_register_set. (match_template): Handle invalid_sib_address. (build_modrm_byte): Handle non-vector SIB and zmmword. (i386_index_check): Disallow RegIP for non-vector SIB. (check_register): Handle zmmword. * testsuite/gas/i386/i386.exp: Add AMX new tests. * testsuite/gas/i386/intel-regs.d: Add tmm. * testsuite/gas/i386/intel-regs.s: Add tmm. * testsuite/gas/i386/x86-64-amx-intel.d: New. * testsuite/gas/i386/x86-64-amx-inval.l: New. * testsuite/gas/i386/x86-64-amx-inval.s: New. * testsuite/gas/i386/x86-64-amx.d: New. * testsuite/gas/i386/x86-64-amx.s: New. * testsuite/gas/i386/x86-64-amx-bad.d: New. * testsuite/gas/i386/x86-64-amx-bad.s: New. opcodes/ * i386-dis.c (TMM): New. (EXtmm): Likewise. (VexTmm): Likewise. (MVexSIBMEM): Likewise. (tmm_mode): Likewise. (vex_sibmem_mode): Likewise. (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise. (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise. (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise. (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise. (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise. (PREFIX_VEX_0F3849_X86_64): Likewise. (PREFIX_VEX_0F384B_X86_64): Likewise. (PREFIX_VEX_0F385C_X86_64): Likewise. (PREFIX_VEX_0F385E_X86_64): Likewise. (X86_64_VEX_0F3849): Likewise. (X86_64_VEX_0F384B): Likewise. (X86_64_VEX_0F385C): Likewise. (X86_64_VEX_0F385E): Likewise. (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise. (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise. (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise. (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise. (VEX_W_0F3849_X86_64_P_0): Likewise. (VEX_W_0F3849_X86_64_P_2): Likewise. (VEX_W_0F3849_X86_64_P_3): Likewise. (VEX_W_0F384B_X86_64_P_1): Likewise. (VEX_W_0F384B_X86_64_P_2): Likewise. (VEX_W_0F384B_X86_64_P_3): Likewise. (VEX_W_0F385C_X86_64_P_1): Likewise. (VEX_W_0F385E_X86_64_P_0): Likewise. (VEX_W_0F385E_X86_64_P_1): Likewise. (VEX_W_0F385E_X86_64_P_2): Likewise. (VEX_W_0F385E_X86_64_P_3): Likewise. (names_tmm): Likewise. (att_names_tmm): Likewise. (intel_operand_size): Handle void_mode. (OP_XMM): Handle tmm_mode. (OP_EX): Likewise. (OP_VEX): Likewise. * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. (operand_type_shorthands): Add RegTMM. (operand_type_init): Likewise. (operand_types): Add Tmmword. (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. * i386-opc.h (CpuAMX_INT8): New. (CpuAMX_BF16): Likewise. (CpuAMX_TILE): Likewise. (SIBMEM): Likewise. (Tmmword): Likewise. (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile. (i386_opcode_modifier): Extend width of fields vexvvvv and sib. (i386_operand_type): Add tmmword. * i386-opc.tbl: Add AMX instructions. * i386-reg.tbl: Add AMX registers. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	6 years ago
Jan Beulich	467bbef07f	x86: various XOP insns lack L and/or W bit decoding While some insns support both XOP.W based operand swapping and 256-bit operation (XOP.L=1), many others don't support one or both. For {L,S}LWPCB also fix the so far not decoded ModRM.mod == 3 restriction. Take the opportunity and replace the custom OP_LWP_E() and OP_LWPCB_E() routines by suitable other, non-custom operanbd specifiers.	6 years ago

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3560 Commits (c930281005b0a01ab824864c231c19c297bfdda5)