binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Alan Modra	a38d139645	PR1202, mcore disassembler: wrong address loopt Fixes a 16 year old bug report, which even came with a patch. opcodes/ PR 1202 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly. Use unsigned int for inst. gas/ PR 1202 * testsuite/gas/mcore/allinsn.d: Correct loopt expected output.	5 years ago
Shahab Vahedi	8f46711443	arc: Construct disassembler options dynamically The idea of this change is simple: Populate a data structure, namely "disasm_option_and_arg_t" from "include/dis-asm.h", to encompass the disassembly options and their possible arguments. This will make it easier to manage or extend those options by adapting entries in a data structure, "arc_options". There will be lesser need to hard-code the options in the code itself. Moreover, ARC GDB will use this population function, "disassembler_options_arc ()", to enable the "set disassembler-option" for ARC targets. The gdb change will be in a separate patch though. The changes in this patch can be divided into: 1) Introduction of "disassembler_options_arc ()" that will return a "disasm_option_and_arg_t" structure representing the disassembly options and their likely arguments. 2) New data type "arc_options_arg_t" and new data "arc_options". These are the internals for keeping track of options and arguments entries that can easily be extended. 3) To print the options, the "print_arc_disassembler_options ()" has been adjusted to use this dynamically built structure instead of having them hard-coded inside. To see this in effect, one can look into the output of: $ ./binutils/objdump --help ... The following ARC specific disassembler options are... ... include/ChangeLog: * dis-asm.h (disassembler_options_arc): New prototype. opcodes/ChangeLog: * arc-dis.c (arc_option_arg_t): New enumeration. (arc_options): New variable. (disassembler_options_arc): New function. (print_arc_disassembler_options): Reimplement in terms of "disassembler_options_arc".	5 years ago
Alan Modra	1ff6a3b8e5	PowerPC table driven -Mraw disassembly opcodes/ * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many. Don't special case PPC_OPCODE_RAW. (lookup_prefix): Likewise. (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and.. (print_insn_powerpc): ..update caller. * ppc-opc.c (EXT): Define. (powerpc_opcodes): Mark extended mnemonics with EXT. (prefix_opcodes, vle_opcodes): Likewise. (XISEL, XISEL_MASK): Add cr field and simplify. (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort all isel variants to where the base mnemonic belongs. Sort dstt, dststt and dssall. gas/ * testsuite/gas/ppc/raw.s, * testsuite/gas/ppc/raw.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.	5 years ago
Maciej W. Rozycki	49149d595c	MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions Group legacy instructions using the COP0, COP2, COP3 opcodes together and by their coprocessor number, and move them towards the end of the opcode table. No functional change. With the addition of explicit ISA exclusions this is maybe not strictly necessary anymore as the individual legacy instructions are not supposed to match ISA levels or CPU implementations that have discarded them or replaced with a new instruction each, but let's not have them scattered randomly across blocks of unrelated instruction sets where someone chose to put them previously. Perhaps they could be put back in alphabetical order in the main instruction block, but let's leave it for another occasion. opcodes/ * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2, COP3 opcode instructions.	5 years ago
Maciej W. Rozycki	9573a461da	MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership Adjust opcode table entries for coprocessor instructions that have been removed from certain ISA levels or CPU implementations as follows: - remove CP0 memory access instructions from MIPS II up as the LWC0 and SWC0 opcodes have been reused for the LL and SC instructions respectively[1]; strictly speaking LWC0 and SWC0 have never really been defined in the first place[2], but let's keep them for now in case an odd implementation did, - remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as they have been removed as from those ISAs, - remove CP0 control register move instructions from MIPS32 up, as they have been removed as from that ISA[5], - remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it has been removed as from those ISAs in favour to ERET, - remove CP2 instructions from Vr5400 CPUs as their encodings have been reused for the multimedia instruction set extensions[8] and no CP2 registers exist[9], - remove CP3 memory access instructions from MIPS III up as coprocessor 3 has been removed as from that ISA[10][11] and from MIPS32 up as the LWC3 opcode has been reused for the PREF instruction and consequently all the four memory access instructions removed from the ISA (though the COP3 opcode has been retained)[12]. Update the testsuite accordingly. References: [1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding - MIPS II Architecture", p. A-178 [2] same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12 [3] "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS Technologies, Inc., January 29, 1997, Section 14.25 "CP0 Instructions", Subsection "Branch on Coprocessor 0", p. 285 [4] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [5] same [6] Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000 Opcode Bit Encoding", p. A-182 [8] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 1.2.3 "CPU Instruction Set Overview", p. 9 [9] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 19.2 "Multimedia Instruction Format", p. 681 [10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3 and CP3 load/store", p. A-176 [11] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture", p. A-179 [12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding of the Opcode Field", p. 241 opcodes/ * mips-opc.c (mips_builtin_opcodes): Update exclusion list for "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0", "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t", "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2", "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3", "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3", "cop2", and "cop3" entries. gas/ * testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3 instruction removal. * testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.	5 years ago
Maciej W. Rozycki	fa49574399	MIPS/opcodes: Remove DMFC3 and DMTC3 instructions Coprocessor 3 has been removed from the MIPS ISA as from MIPS III[1][2] with the LDC3 and SDC3 instructions having been replaced with LD and SD instructions respectively and therefore the doubleword move instructions from and to that coprocessor have never materialized (for 32-bit ISAs coprocessor 3 has likewise been removed as from MIPS32r2[3]). Remove the DMFC3 and DMTC3 instructions from the opcode table then to avoid confusion. References: [1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3 and CP3 load/store", p. A-176 [2] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture", p. A-179 [3] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 2.00, June 9, 2003, Table A-2 "MIPS32 Encoding of the Opcode Field", p. 317 opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3" entries and associated comments.	5 years ago
Maciej W. Rozycki	b930964c42	MIPS/opcodes: Disassemble the RFE instruction Fix a commit `b015e599c7` ("[MIPS] Add new virtualization instructions"), <https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression and bring the disassembly of the RFE instruction back for the relevant ISA levels. It is because the "rfe" opcode table entry was incorrectly moved behind the catch-all generic "c0" entry for CP0 instructions, causing output like: 00: 42000010 c0 0x10 to be produced rather than: 00: 42000010 rfe even for ISA levels that do include the RFE instruction. Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a suitable test case. opcodes/ * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead of "c0". gas/ * testsuite/gas/mips/rfe.d: New test. * testsuite/gas/mips/rfe.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.	5 years ago
Maciej W. Rozycki	dd84446824	MIPS/opcodes: Add legacy CP1 control register names The two CP1 control registers defined by legacy ISAs used to be referred to by various names, such as FCR0, FCR31, FSR, however their documented full names have always been the Implementation and Revision, and Control and Status respectively, so the FIR and FCSR acronyms coming from modern ISA revisions will be just as unambiguous while improving the clarity of disassembly. Do not update the TX39 though as it did not have an FPU. opcodes/ * mips-dis.c (mips_cp1_names_mips): New variable. (mips_arch_choices): Use it rather than `mips_cp1_names_numeric' for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120", "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500", "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000", "r12000", "r14000", "r16000", "mips5", "loongson2e", and "loongson2f". gas/ * testsuite/gas/mips/cp1-names-r3900.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. * testsuite/gas/mips/branch-misc-3.d: Update disassembly according to changes to opcodes. * testsuite/gas/mips/cp1-names-r3000.d: Likewise. * testsuite/gas/mips/cp1-names-r4000.d: Likewise. * testsuite/gas/mips/relax-swap1-mips1.d: Likewise. * testsuite/gas/mips/relax-swap1-mips2.d: Likewise. * testsuite/gas/mips/trunc.d: Likewise.	5 years ago
Maciej W. Rozycki	9204ccd4b1	MIPS/opcodes: Do not use CP0 register names for control registers The CP0 control register set has never been defined, however encodings for the CFC0 and CTC0 instructions remained available for implementers up until the MIPS32 ISA declared them invalid and causing the Reserved Instruction exception[1]. Therefore we handle them for both assembly and disassembly, however in the latter case the names of CP0 registers from the regular set are incorrectly printed if named registers are requested. This is because we do not define separate operand classes for coprocessor regular and control registers respectively, which means the disassembler has no way to tell the two cases apart. Consequently nonsensical disassembly is produced like: cfc0 v0,c0_random Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 instructions[2] although it failed to document them in the relevant opcode table until MIPSr6 only. Correct the issue then by defining a new register class, OP_REG_CONTROL, and corresponding operand codes, `g' and `y' for the two positions in the machine instruction a control register operand can take. Adjust the test cases affected accordingly. While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries with each other so that they come in the alphabetical order. References: [1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 195, 216 include/ * opcode/mips.h: Document `g' and `y' operand codes. (mips_reg_operand_type): Add OP_REG_CONTROL enumeration constant. gas/ * tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case. (macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' operand code. opcodes/ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register handling code over to... <OP_REG_CONTROL>: ... this new case. * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries replacing the `G' operand code with `g'. Update "cftc1" and "cftc2" entries replacing the `E' operand code with `y'. * micromips-opc.c (decode_micromips_operand) <'g'>: New case. (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" entries replacing the `G' operand code with `g'. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 operand disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.	5 years ago
Maciej W. Rozycki	a3fb396f2d	MIPS/opcodes: Add TX39 CP0 register names The TX39 core has its distinct set of CP0 registers[1], so it needs a separate table to hold their names. Add a test case accordingly. References: [1] "32-Bit RISC Microprocessor TX39 Family Core Architecture User's Manual", Toshiba, Jul. 27, 1995, Section 2.2.2 "System control coprocessor (CP0) registers", pp. 9-10 opcodes/ * mips-dis.c (mips_cp0_names_r3900): New variable. (mips_arch_choices): Use it rather than `mips_cp0_names_numeric' for "r3900". gas/ * testsuite/gas/mips/cp0-names-r3900.d: New test. * testsuite/gas/mips/mips.exp: Run it.	5 years ago
Maciej W. Rozycki	cccc84faff	MIPS/opcodes: Free up redundant `g' operand code In the operand handling rewrite made for the MIPS disassembler with commit `ab90248154` ("Add structures to describe MIPS operands"), <https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g' operand code has become redundant for the regular MIPS instruction set by duplicating the OP_REG_COPRO semantics of the `G' operand code. Later commit `351cdf24d2` ("Implement O32 FPXX, FP64 and FP64A ABI extensions") converted the CTTC1 instruction from the `g' to the `G' operand code, but still left a few instructions behind. Convert the three remaining instructions still using the `g' code then, namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand code, freeing it up for other use. opcodes/ * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2", and "mtthc2" to using the `G' rather than `g' operand code for the coprocessor control register referred. include/ * opcode/mips.h: Complement change made to opcodes and remove references to the `g' regular MIPS ISA operand code.	5 years ago
Maciej W. Rozycki	c9de3168a9	microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1 The DMTC1 instruction operates on a floating-point general register as its second operand, however in the disassembly of the microMIPS encoding a floating-point control register is shown instead. This is due to an incorrect ordering of the two "dmtc1" entries in the opcode table, which gives precedence to one using the `G' aka coprocessor format over one using the `S' or floating-point register format. The coprocessor format, or OP_REG_COPRO, is used so that GAS supports referring to FPRs by their numbers in assembly, such as $0, $1, etc. however in the case of CP1/FPU it is also used by the disassembler to decode those numbers to the names of corresponding control registers. This in turn causes nonsensical disassembly such as: dmtc1 a1,c1_fir in a reference to $f0. It has been like this ever since microMIPS ISA support has been added. Correct the ordering of the two entries then by swapping them with each other, making disassembly output consistent with the regular MIPS DMTC1 instruction as well all the remaining CP1 move instructions. Adjust all the test cases affected accordingly. opcodes/ * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1" entries with each other. gas/ * testsuite/gas/mips/micromips.d: Update disassembly according to "dmtc1" entry fix with opcodes. * testsuite/gas/mips/micromips-compact.d: Likewise. * testsuite/gas/mips/micromips-insn32.d: Likewise. * testsuite/gas/mips/micromips-noinsn32.d: Likewise. * testsuite/gas/mips/micromips-trap.d: Likewise. * testsuite/gas/mips/micromips@isa-override-1.d: Likewise.	5 years ago
Peter Bergner	ebcab74124	PowerPC: Add new xxmr and xxlnot extended mnemonics opcodes/ * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics. gas/ * testsuite/gas/ppc/vsx.d <xxmr, xxlnot>: Add tests. * testsuite/gas/ppc/vsx.s: Likewise.	5 years ago
Alan Modra	bc30a119f3	Regen cris files * cris-desc.c: Regenerate. * cris-desc.h: Regenerate. * cris-opc.h: Regenerate. * po/POTFILES.in: Regenerate.	5 years ago
Mike Frysinger	5471128011	opcodes: cris: move desc & opc files from sim/ All other cgen ports keep their generated desc & opc files under opcodes/, so move the cris files over too. The cris-opc.c file, while not generated, is already here to complement.	5 years ago
Job Noorman	113bb7618a	RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary. 2021-05-18 Job Noorman <mtvec@pm.me> opcodes/ PR 27814 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for the elf objects.	5 years ago
Alex Coplan	e683cb4120	arm: Fix bugs with MVE vmov from two GPRs to vector lanes The initial problem I wanted to fix here is that GAS was rejecting MVE instructions such as: vmov q3[2], q3[0], r2, r2 with: Error: General purpose registers may not be the same -- `vmov q3[2],q3[0],r2,r2' which is incorrect; such instructions are valid. Note that for moves in the other direction, e.g.: vmov r2, r2, q3[2], q3[0] GAS is correct in rejecting this as it does not make sense to move both lanes into the same register (the Arm ARM says this is CONSTRAINED UNPREDICTABLE). After fixing this issue, I added assembly/disassembly tests for these vmovs. This revealed several disassembly issues, including incorrectly marking the moves into vector lanes as UNPREDICTABLE, and disassembling many of the vmovs as vector loads. These are now fixed. gas/ChangeLog: * config/tc-arm.c (do_mve_mov): Only reject vmov if we're moving into the same GPR twice. * testsuite/gas/arm/mve-vmov-bad-2.l: Tweak error message. * testsuite/gas/arm/mve-vmov-3.d: New test. * testsuite/gas/arm/mve-vmov-3.s: New test. opcodes/ChangeLog: * arm-dis.c (mve_opcodes): Fix disassembly of MVE_VMOV2_GP_TO_VEC_LANE when idx == 1. (is_mve_encoding_conflict): MVE vector loads should not match when P = W = 0. (is_mve_unpredictable): It's not unpredictable to use the same source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).	5 years ago
Nick Clifton	a680affc63	Fix an illegal memory access when attempting to disassemble a corrupt TIC30 binary. PR 27840 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond the end of the code buffer.	5 years ago
Stafford Horne	0b3e14c902	or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha() The gotha() relocation mnemonic will be outputted by OpenRISC GCC when using the -mcmodel=large option. This relocation is used along with got() to generate 32-bit GOT offsets. This increases the previous GOT offset limit from the previous 16-bit (64K) limit. This is needed on large binaries where the GOT grows larger than 64k. bfd/ChangeLog: PR 21464 * bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation. * elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise. (or1k_final_link_relocate, or1k_elf_relocate_section, or1k_elf_check_relocs): Likewise. * libbfd.h (bfd_reloc_code_real_names): Likewise. * reloc.c: Likewise. cpu/ChangeLog: PR 21464 * or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic for gotha() relocation. include/ChangeLog: PR 21464 * elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number. opcodes/ChangeLog: PR 21464 * or1k-asm.c: Regenerate. gas/ChangeLog: PR 21464 * testsuite/gas/or1k/reloc-1.s: Add test for new relocation. * testsuite/gas/or1k/reloc-1.d: Add test result for new relocation. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> fixup reloc, add tests	5 years ago
Max Filippov	6aee2cb249	opcodes: xtensa: support branch visualization 2021-05-01 Max Filippov <jcmvbkbc@gmail.com> opcodes/ * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and info->insn_info_valid.	5 years ago
Jan Beulich	fe134c6569	x86: optimize LEA Over the years I've seen a number of instances where people used lea (%reg1), %reg2 or lea symbol, %reg despite the same thing being expressable via MOV. Since additionally LEA often has restrictions towards the ports it can be issued to, while MOV typically gets dealt with simply by register renaming, transform to MOV when possible (without growing opcode size and without altering involved relocation types). Note that for Mach-O the new 64-bit testcases would fail (for BFD_RELOC_X86_64_32S not having a representation), and hence get skipped there.	5 years ago
Max Filippov	b3ea76397a	opcodes: xtensa: display loaded literal value Display literal value loaded with l32r opcode as a part of disassembly. This significantly simplifies reading of disassembly output. 2020-04-23 Max Filippov <jcmvbkbc@gmail.com> opcodes/ * xtensa-dis.c (print_xtensa_operand): For PC-relative operand of l32r fetch and display referenced literal value.	5 years ago
Max Filippov	c1cbb7d8a1	opcodes: xtensa: improve literal output Output literals as 4-byte words, not as separate bytes. 2021-04-23 Max Filippov <jcmvbkbc@gmail.com> opcodes/ * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk to 4 for literal disassembly.	5 years ago
Przemyslaw Wirkus	02202574ec	aarch64: New instructions for maintenance of GPT entries cached in a TLB This patch adds support to four new system registers (RPAOS, RPALOS, PAALLOS, PAALL) in conjunction with TLBI instruction. This change is part of RME (Realm Management Extension). gas/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update news. * testsuite/gas/aarch64/rme.d: Update test. * testsuite/gas/aarch64/rme.s: Update test. opcodes/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support for TLBI instruction.	5 years ago
Przemyslaw Wirkus	cd6608e49d	aarch64: Add new data cache maintenance operations This patch adds support to two new system registers (CIPAPA, CIGDPAPA) in conjunction with DC instruction. This change is part of RME (Realm Management Extension). gas/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/rme.d: Update test. * testsuite/gas/aarch64/rme.s: Update test. opcodes/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for DC instruction.	5 years ago
Jan Beulich	fe1640ff8e	arm64: add two initializers Old enough gcc can't cope and would warn about the variables potentially remaining uninitialized.	5 years ago
Przemyslaw Wirkus	100e914da3	aarch64: Define RME system registers This patch introduces RME (Realm Management Extension) system registers. gas/ChangeLog: 2021-03-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/rme-invalid.d: New test. * testsuite/gas/aarch64/rme-invalid.l: New test. * testsuite/gas/aarch64/rme-invalid.s: New test. * testsuite/gas/aarch64/rme.d: New test. * testsuite/gas/aarch64/rme.s: New test. opcodes/ChangeLog: 2021-03-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add RME system registers.	5 years ago
Nelson Chu	a21b96dd66	Update the ChangeLog, and add the missing entries.	5 years ago
Lifang Xia	a8ab209320	RISC-V: compress "addi d,CV,z" to "c.mv d,CV" PR 27732 gas/ * testsuite/gas/riscv/c-zero-imm.d: Compress addi a4,a4,0 to c.mv a4,a4. * testsuite/gas/riscv/c-zero-imm.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress "addi d,CV,z" to "c.mv d,CV".	5 years ago
Alan Modra	43e05cd4f4	ENABLE_CHECKING in bfd, opcodes, binutils, ld gas already has this. Here it enables checking hash table type passed to elf_link_hash_lookup and elf_link_hash_traverse. bfd/ * elf-bfd.h (ENABLE_CHECKING): Define. (elf_link_hash_lookup): Abort if wrong type of hash table. (elf_link_hash_traverse): Likewise. * configure.ac (--enable-checking): Add support. * config.in: Regenerate. * configure: Regenerate. binutils/ * configure.ac (--enable-checking): Add support. * config.in: Regenerate. * configure: Regenerate. ld/ * configure.ac (--enable-checking): Add support. * config.in: Regenerate. * configure: Regenerate. opcodes/ * configure.ac (--enable-checking): Add support. * config.in: Regenerate. * configure: Regenerate.	5 years ago
Tejas Belagod	52efda8266	AArch64: Fix Atomic LD64/ST64 classification. Patch 1: Fix diagnostics for exclusive load/stores and reclassify Armv8.7-A ST/LD64 Atomics. Following upstream pointing out some inconsistencies in diagnostics, https://sourceware.org/pipermail/binutils/2021-February/115356.html attached is a patch set that fixes the issues. I believe a combination of two patches mainly contributed to these bugs: https://sourceware.org/pipermail/binutils/2020-November/113961.html https://sourceware.org/pipermail/binutils/2018-June/103322.html A summary of what this patch set fixes: For instructions STXR w0,x2,[x0] STLXR w0,x2,[x0] The warning we emit currently is misleading: Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]' it ought to be: Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]' For instructions: ldaxp x0,x0,[x0] ldxp x0,x0,[x0] The warning we emit is incorrect Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]' Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]' it ought to be: Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]' Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]' For instructions stlxp w0, x2, x2, [x0] stxp w0, x2, x2, [x0] We don't emit any warning when it ought to be: Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]' For instructions: st64bv x0, x2, [x0] st64bv x2, x0, [x0] We incorrectly warn when its not necessary. This is because we classify them incorrectly as ldstexcl when it should be lse_atomics in the opcode table. The incorrect classification makes it pick up the warnings from warning on exclusive load/stores. Patch 2: Reclassify Armv8.7-A ST/LD64 Atomics. This patch reclassifies ST64B{V,V0}, LD64B as lse_atomics rather than ldstexcl according to their encoding class as specified in the architecture. This also has the fortunate side-effect of spurious unpredictable warnings getting eliminated. For eg. For instruction: st64bv x0, x2, [x0] We incorrectly warn when its not necessary: Warning: unpredictable: identical transfer and status registers --`st64bv x0,x2,[x0]' This is because we classify them incorrectly as ldstexcl when it should be lse_atomics in the opcode table. The incorrect classification makes it pick up the warnings from warning on exclusive load/stores. This patch fixes it by reclassifying it and no warnings are issued for this instruction. opcodes/ChangeLog: 2021-04-09 Tejas Belagod <tejas.belagod@arm.com> * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify LD64/ST64 instructions to lse_atomic instead of ldstexcl.	5 years ago
Alan Modra	c3f72de4f5	PowerPC disassembly of pcrel references This adds some annotation to Power10 pcrel instructions, displaying the target address (ie. pc + D34 field) plus a symbol if there is one at exactly that target address. pld from the .got or .plt will also look up the entry and display it, symbolically if there is a dynamic relocation on the entry. include/ * dis-asm.h (struct disassemble_info): Add dynrelbuf and dynrelcount. binutils/ * objdump.c (struct objdump_disasm_info): Delete dynrelbuf and dynrelcount. (find_symbol_for_address): Adjust for dynrelbuf and dynrelcount move. (disassemble_section, disassemble_data): Likewise. opcodes/ * ppc-dis.c (struct dis_private): Add "special". (POWERPC_DIALECT): Delete. Replace uses with.. (private_data): ..this. New inline function. (disassemble_init_powerpc): Init "special" names. (skip_optional_operands): Add is_pcrel arg, set when detecting R field of prefix instructions. (bsearch_reloc, print_got_plt): New functions. (print_insn_powerpc): For pcrel instructions, print target address and symbol if known, and decode plt and got loads too. gas/ * testsuite/gas/ppc/prefix-pcrel.d: Update expected output. * testsuite/gas/ppc/prefix-reloc.d: Likewise. * gas/testsuite/gas/ppc/vsx_32byte.d: Likewise. ld/ * testsuite/ld-powerpc/inlinepcrel-1.d: Update expected output. * testsuite/ld-powerpc/inlinepcrel-2.d: Likewise. * testsuite/ld-powerpc/notoc2.d: Likewise. * testsuite/ld-powerpc/notoc3.d: Likewise. * testsuite/ld-powerpc/pcrelopt.d: Likewise. * testsuite/ld-powerpc/startstop.d: Likewise. * testsuite/ld-powerpc/tlsget.d: Likewise. * testsuite/ld-powerpc/tlsget2.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. * testsuite/ld-powerpc/weak1.d: Likewise. * testsuite/ld-powerpc/weak1so.d: Likewise.	5 years ago
Alan Modra	ce7d813a0f	PR27684, PowerPC missing mfsprg0 and others PR 27684 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.	5 years ago
Alan Modra	97bf40d859	PR27676, PowerPC missing extended dcbt, dcbtst mnemonics Note that this doesn't implement the ISA to the letter regarding dcbtds (and dcbtstds), which says that the TH field may be zero. That doesn't make sense because allowing TH=0 would mean you no long have a dcbtds but rather a dcbtct instruction. I'm interpreting the ISA wording about allowing TH=0 to mean that the TH field of dcbtds is optional (in which case the TH value is 0b1000). opcodes/ PR 27676 * ppc-opc.c (DCBT_EO): Move earlier. (insert_thct, extract_thct, insert_thds, extract_thds): New functions. (powerpc_operands): Add THCT and THDS entries. (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds. gas/ * testsuite/gas/ppc/pr27676.d, * testsuite/gas/ppc/pr27676.s: New test. * testsuite/gas/ppc/ppc.exp: Run it. * testsuite/gas/ppc/dcbt.d: Update. * testsuite/gas/ppc/power4_32.d: Update.	5 years ago
Alan Modra	a2e6677373	Return symbol from symbol_at_address_func include/ * dis-asm.h (struct disassemble_info <symbol_at_address_func>): Return asymbol. binutils/ objdump.c (objdump_symbol_at_address): Return asymbol. opcodes/ dis-buf.c (generic_symbol_at_address): Return symbol* NULL. * s12z-dis.c (decode_possible_symbol): Use symbol returned from symbol_at_address_func.	5 years ago
Alan Modra	ab2af25e83	C99 opcodes configury * configure.ac: Don't check for limits.h, string.h, strings.h or stdlib.h. (AC_ISC_POSIX): Don't invoke. * sysdep.h: Include stdlib.h and string.h unconditionally. * i386-opc.h: Include limits.h unconditionally. * wasm32-dis.c: Likewise. * cgen-opc.c: Don't include alloca-conf.h. * config.in: Regenerate. * configure: Regenerate.	5 years ago
Martin Liska	e9b095a538	Remove strneq macro and use startswith. bfd/ChangeLog: * ecoff.c (strneq): Remove strneq and use startswith. (_bfd_ecoff_slurp_armap): Likewise. binutils/ChangeLog: * elfcomm.h (strneq): Remove strneq and use startswith. * readelf.c (ia64_process_unwind): Likewise. (process_note): Likewise. gas/ChangeLog: * config/obj-coff.c (strneq): Remove strneq and use startswith. (weak_is_altname): Likewise. (obj_coff_section): Likewise. * config/tc-cr16.c (process_label_constant): Likewise. * config/tc-crx.c (strneq): Likewise. include/ChangeLog: * opcode/cr16.h (strneq): Remove strneq and use startswith. ld/ChangeLog: * ldbuildid.c (strneq): Remove strneq and use startswith. (validate_build_id_style): Likewise. (compute_build_id_size): Likewise. opcodes/ChangeLog: * arm-dis.c (strneq): Remove strneq and use startswith. * cr16-dis.c (print_insn_cr16): Likewise. * score-dis.c (streq): Likewise. (strneq): Likewise. * score7-dis.c (strneq): Likewise.	5 years ago
Alan Modra	1cb108e416	PR27675, PowerPC missing extended mnemonic mfummcr2 PR 27675 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.	5 years ago
Alan Modra	78933a4ad9	Use bool in opcodes cpu/ * frv.opc: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout. opcodes/ * sysdep.h (POISON_BFD_BOOLEAN): Define. * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h, * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h, * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c, * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c, * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c, * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c, * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c, * microblaze-dis.h, * micromips-opc.c, * mips-dis.c, * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c, * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c, * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c, * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c, * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout.	5 years ago
Alan Modra	3dfb1b6d34	Remove bfd_stdint.h If we require C99 for binutils then stdint.h is available. bfd/ * .gitignore: Delete bfd_stdint.h entry. * Makefile.am (bfdinclude_HEADERS): Delete bfd_stdint.h. (BUILD_HFILES, LOCAL_H_DEPS): Likewise. * bfd-in.h: Include stdint.h in place of bfd_stdint.h. * configure.ac: Don't invoke GCC_HEADER_STDINT. * configure.com: Don't create bfd_stdint.h. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in2.h: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. binutils/ * coffdump.c: Include stdint.h in place of bfd_stdint.h. * dwarf.c: Likewise. gas/ * config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h. * config/tc-crx.c: Likewise. * config/tc-nds32.h: Likewise. include/ * cgen/basic-modes.h: Include stdint.h in place of bfd_stdint.h. * elf/nfp.h: Likewise. * opcode/aarch64.h: Likewise. * opcode/cgen.h: Likewise. * opcode/nfp.h: Likewise. * opcode/ppc.h: Likewise. ld/ * elf-hints-local.h: Include stdint.h in place of bfd_stdint.h. * emultempl/nds32elf.em: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise. * testsuite/ld-elf/pr18718.c: Likewise. * testsuite/ld-elf/pr18720a.c: Likewise. * testsuite/ld-elf/pr25749-1.c: Likewise. * testsuite/ld-elf/pr25749-1a.c: Likewise. * testsuite/ld-elf/pr25749-1b.c: Likewise. * testsuite/ld-elf/pr25749-1c.c: Likewise. * testsuite/ld-elf/pr25749-1d.c: Likewise. * testsuite/ld-elf/pr25749-2.c: Likewise. * testsuite/ld-elf/pr25754-1a.c: Likewise. * testsuite/ld-elf/pr25754-2a.c: Likewise. * testsuite/ld-elf/pr25754-3a.c: Likewise. * testsuite/ld-elf/pr25754-4a.c: Likewise. * testsuite/ld-elf/pr25754-5a.c: Likewise. * testsuite/ld-elf/pr25754-6a.c: Likewise. opcodes/ * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h. * aarch64-dis.h: Likewise. * aarch64-opc.c: Likewise. * avr-dis.c: Likewise. * csky-dis.c: Likewise. * nds32-asm.c: Likewise. * nds32-dis.c: Likewise. * nfp-dis.c: Likewise. * riscv-dis.c: Likewise. * s12z-dis.c: Likewise. * wasm32-dis.c: Likewise.	5 years ago
Jan Beulich	5e0423804a	x86: drop seg_entry Use struct reg_entry instead for most purposes, with a separate array holding just the respective opcode prefix bytes.	5 years ago
Jan Beulich	3468486226	x86: drop REGNAM_{AL,AX,EAX} The former two are unused anyway. And having such constants isn't very helpful either, when they live in a place where updating the register table wouldn't even allow noticing the need to adjust these constants.	5 years ago
Jan Beulich	6288d05f11	x86: adjust st(<N>) parsing st(1) ... st(7) will never be looked up in the hash table, so there's no point inserting the entries. It's also not really necessary to do a 2nd hash lookup after parsing the register number, nor is there a real reason for having both st and st(0) entries. Plus we can easily do away with the need for st to be first in the table.	5 years ago
Jan Beulich	bbe1eca622	x86: move some opcode table entries For a long time there hasn't been a need anymore to keep together all templates with identical mnemonics. Move the MOVQ and MOVABS ones next to their MOV counterparts. Move the string forms of CMPSD and MOVSD next to their CMPS / MOVS counterparts. Re-arrange what so fgar was the SSE3 section. This makes reasonably obvious that MONITOR/MWAIT aren't suitable to cover by CpuSSE3, but adjusting this is left for another time.	5 years ago
Jan Beulich	c8cad9d389	x86: VPSADBW's source operands are also commutative In commit `79dec6b7ba` ("x86-64: optimize certain commutative VEX-encoded insns") I missed the fact that there being subtraction involved here doesn't matter, as absolute differences get summed up.	5 years ago
Jan Beulich	5cdaf10025	x86: fold SSE2AVX and their base MMX/SSE templates This way not only the overall (source) table size shrinks by quite a bit and the risk of related templates going out of sync with one another gets lowered, but also (dis)similarities between neighboring templates become easier to spot. Note that for certain SSE2AVX templates this results in benign attribute changes: - LDMXCSR and STMXCSR: NoAVX gets set, - MOVMSKPS, PMOVMSKB, PEXTR{B,W} (register destination), and PINSR{B,W} (register source): IgnoreSize and NoRex64 get set, - CVT{DQ,PS}2PD, CVTSD2SS, MOVMSKPD, MOVDDUP, PMOV{S,Z}X{BW,WD,DQ}, and ROUNDSD: NoRex64 gets set, - CVTSS2SD, INSERTPS, PEXTRW (memory destination), PINSRW (memory source), and PMOV{S,Z}X{BD,WQ,BQ}: IgnoreSize gets set. Similarly the "normal" (non-SSE2AVX) - non-64-bit CVTS{I,S}2SD forms get NoRex64 set, - CMP{EQ,ORD,NEQ,UNORD}{P,S}{S,D} forms get C set, all again in a benign way. The remaining differences in the generated table are due to re-ordering of entries in the course of being folded into templates.	5 years ago
Jan Beulich	73e45eb208	x86: undo Prefix_0X<nn> use in opcode table The table entries are more natural to read (and slightly shorter) when the prefixes, like is the case for VEX/XOP/EVEX-encoded entries, are specified as part of the opcode. This is particularly noticable for side-by-side legacy and SSE2AVX entries. An implication is that we now need to use "unsigned long long" for the initially parsed opcode in i386-gen. I don't expect this to be an issue.	5 years ago
Jan Beulich	9df6f676c2	x86: shrink some struct insn_template fields Now that all base opcodes are only at most 2 bytes in size, shrink its template field to just as much. By also shrinking extension_opcode and operands to just what they really need, we can free up an entire 32-bit slot (plus 4 left bits past the bitfields themselves). At present this alters sizeof(struct insn_template) only for 32-bit builds. In 64-bit builds it instead leaves a padding hole that will allow to buffer future growth of other fields (opcode_modifier, cpu_flags, operand_types[]).	5 years ago
Jan Beulich	389d00a5e5	x86: derive opcode encoding space attribute from base opcode Just like is already done for VEX/XOP/EVEX encoded insns, record the encoding space information in the respective opcode modifier field. Do this again without changing the source table, but rather by deriving the values from their existing source representation.	5 years ago
Alan Modra	63b4cc53dc	TRUE/FALSE simplification There is really no need to write code like "foo != 0 ? TRUE : FALSE" unless we had stupidly defined FALSE as something other than 0 or TRUE as something other than 1. The simpler "foo != 0" does just as well. Similarly "(condition == TRUE)" or "(condition == FALSE) can be simplified to "(condition)" and "(!condition)" respectively. I'll note that there is reason to use "integer_expression != 0" when assigning a bfd_boolean rather than the simpler "integer_expression", if you expect the variable to have 0 or 1 value. It's probably even a good idea to not rely on implicit conversion if bfd_boolean were _Bool. bfd/ * aoutx.h (aout_link_write_symbols): Don't cast boolean expression to bfd_boolean. * elf32-or1k.c (or1k_set_got_and_rela_sizes): Dont compare booleans against FALSE. * elf32-arc.c (name_for_global_symbol): Don't compare boolean to TRUE. (is_reloc_PC_relative): Don't use "boolean_condition ? TRUE : FALSE". (is_reloc_SDA_relative, is_reloc_for_GOT): Likewise. (is_reloc_for_PLT, is_reloc_for_TLS): Likewise. * elf32-arm.c (stm32l4xx_need_create_replacing_stub): Likewise. * elf32-nds32.c (insert_nds32_elf_blank): Likewise. * elf32-rx.c (rx_set_section_contents): Likewise. * elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Likewise. * elfxx-mips.c (_bfd_mips_elf_ignore_undef_symbol): Likewise. * mach-o.c (bfd_mach_o_read_command): Likewise. * targets.c (bfd_get_target_info): Likewise. binutils/ * dlltool.c (main): Don't use "boolean_condition ? TRUE : FALSE". * dwarf.c (read_and_display_attr_value): Likewise. (display_debug_str_offsets): Likewise. * objdump.c (dump_bfd): Likewise. * readelf.c (dump_section_as_strings): Likewise. (dump_section_as_bytes): Likewise. gas/ * atof-generic.c (FALSE, TRUE): Don't define. * config/obj-elf.h (FALSE, TRUE): Don't define. * config/obj-som.h (FALSE, TRUE): Don't define. * config/tc-hppa.h (FALSE, TRUE): Don't define. * config/tc-pdp11.c (FALSE, TRUE): Don't define. * config/tc-iq2000.h (obj_fix_adjustable): Delete. * config/tc-m32r.h (TC_FIX_ADJUSTABLE): Delete. * config/tc-mt.h (obj_fix_adjustable): Delete. * config/tc-nds32.h (TC_FIX_ADJUSTABLE): Delete. * config/tc-arc.c (parse_opcode_flags): Simplify boolean expression. (relaxable_flag, relaxable_operand, assemble_insn): Likewise. (tokenize_extregister): Likewise. * config/tc-csky.c (parse_opcode, get_operand_value): Likewise. (parse_operands_op, parse_operands, md_assemble): Likewise. * config/tc-d10v.c (build_insn): Likewise. * config/tc-score.c (s3_gen_insn_frag): Likewise. * config/tc-score7.c (s7_gen_insn_frag, s7_relax_frag): Likewise. * config/tc-tic6x.c (tic6x_update_features, md_assemble): Likewise. * config/tc-z80.c (emit_byte): Likewise. include/ * opcode/aarch64.h (alias_opcode_p): Simplify boolean expression. (opcode_has_alias, pseudo_opcode_p, optional_operand_p): Likewise. (opcode_has_special_coder): Likewise. ld/ * emultempl/aix.em (gld${EMULATION_NAME}_before_allocation): Simplify boolean expression. * lexsup.c (parse_args): Likewise. * pe-dll.c (pe_dll_id_target): Likewise. opcodes/ * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression. (fp_qualifier_p, get_data_pattern): Likewise. (aarch64_get_operand_modifier_from_value): Likewise. (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise. (operand_variant_qualifier_p): Likewise. (qualifier_value_in_range_constraint_p): Likewise. (aarch64_get_qualifier_esize): Likewise. (aarch64_get_qualifier_nelem): Likewise. (aarch64_get_qualifier_standard_value): Likewise. (get_lower_bound, get_upper_bound): Likewise. (aarch64_find_best_match, match_operands_qualifier): Likewise. (aarch64_print_operand): Likewise. * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise. (operand_need_sign_extension, operand_need_shift_by_two): Likewise. (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise. * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise. * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise. (print_insn_tic6x): Likewise.	5 years ago

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3897 Commits (c70fdc45f60845852f98eae3b8035de1a2df78de)