binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Simon Marchi	af39b1c216	Disable -Wformat-nonliteral in parts of printcmd.c commit `3322c5d9a1` ("Remove unneeded explicit .o targets") broke the build with clang, because -Wno-format-nonliteral was in fact needed. This patch fixes the problem by introducing DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL and using it in printcmd.c. This seems preferable to reverting the patch because now the warning suppression is more targeted. gdb/ChangeLog 2018-09-05 Simon Marchi <simon.marchi@ericsson.com> * printcmd.c (printf_c_string): Use DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL. (printf_wide_c_string, printf_pointer, ui_printf): Likewise. include/ChangeLog 2018-09-05 Simon Marchi <simon.marchi@ericsson.com> * diagnostics.h (DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL): New macro.	8 years ago
Alan Modra	4a9699735b	PowerPC64 higher REL16 relocations There are occasions where someone might want to build a 64-bit pc-relative offset from 16-bit pieces. This adds the necessary REL16 relocs corresponding to existing ADDR16 relocs that can be used to build 64-bit absolute values. include/ * elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA), (R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA), (R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define. (R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value. bfd/ * reloc.c (BFD_RELOC_PPC64_REL16_HIGH, BFD_RELOC_PPC64_REL16_HIGHA), (BFD_RELOC_PPC64_REL16_HIGHER, BFD_RELOC_PPC64_REL16_HIGHERA), (BFD_RELOC_PPC64_REL16_HIGHEST, BFD_RELOC_PPC64_REL16_HIGHESTA): Define. * elf64-ppc.c (ppc64_elf_howto_raw): Add new REL16 howtos. (ppc64_elf_reloc_type_lookup): Translate new REL16 relocs. (ppc64_elf_check_relocs, ppc64_elf_relocate_section): Handle them. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Allow ADDR16 HIGH, HIGHA, HIGHER, HIGHERA, HIGHEST, and HIGHESTA relocs. Group 16-bit relocs. * config/tc-ppc.c (md_apply_fix): Translate those ADDR16 relocs to REL16 when pcrel. Sort relocs.	8 years ago
Jim Wilson	43135d3b15	RISC-V: Allow instruction require more than one extension 2018-08-29 Kito Cheng <kito@andestech.com> gas/ * config/tc-riscv.c (riscv_subset_supports): New argument: xlen_required. (riscv_multi_subset_supports): New function, able to check more than one extension. (riscv_ip): Use riscv_multi_subset_supports instead of riscv_subset_supports. (riscv_set_arch): Update call-site for riscv_subset_supports. (riscv_after_parse_args): Likewise. include/ opcode/riscv.h (MAX_SUBSET_NUM): New. (riscv_opcode): Add xlen_requirement field and change type of subset. opcodes/ riscv-dis.c (riscv_disassemble_insn): Check XLEN by riscv_opcode.xlen_requirement. * riscv-opc.c (riscv_opcodes): Update for struct change.	8 years ago
Chenghua Xu	9108bc33b1	[MIPS] Add Loongson 2K1000 proccessor support. bfd/ * archures.c (bfd_architecture): New machine bfd_mach_mips_gs264e. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_GS264E. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Map bfd_mach_mips_gs264e to bfd_mach_mips_gs464e extension. binutils/ * NEWS: Mention Loongson 2K1000 proccessor support. * readelf.c (get_machine_flags): Handle gs264e. elfcpp/ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E. (mips_cpu_info_table): Add gs264e descriptors. * doc/as.texi (march table): Add gs264e. include/ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E. * opcode/mips.h (CPU_XXX): New CPU_GS264E. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination gs264e and gs464e. opcodes/ * mips-dis.c (mips_arch_choices): Add gs264e descriptors.	8 years ago
Chenghua Xu	bd782c07b9	[MIPS] Add Loongson 3A2000/3A3000 proccessor support. bfd/ * archures.c (bfd_architecture): New machine bfd_mach_mips_gs464e. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_GS464E. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Map bfd_mach_mips_gs464e to bfd_mach_mips_gs464 extension. binutils/ * NEWS: Mention Loongson 3A2000/3A3000 proccessor support. * readelf.c (get_machine_flags): Handle gs464e. elfcpp/ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E. (mips_cpu_info_table): Add gs464e descriptors. * doc/as.texi (march table): Add gs464e. include/ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E. * opcode/mips.h (CPU_XXX): New CPU_GS464E. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination gs464e and gs464. opcodes/ * mips-dis.c (mips_arch_choices): Add gs464e descriptors.	8 years ago
Chenghua Xu	ac8cb70f36	[MIPS] Add Loongson 3A1000 proccessor support. bfd/ * archures.c (bfd_architecture): Rename bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Likewise. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Likewise. (bfd_mips_isa_ext_mach): Likewise. (bfd_mips_isa_ext): Likewise. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. binutils/ * NEWS: Mention Loongson 3A1000 proccessor support. * readelf.c (get_machine_flags): Rename loongson-3a to gs464. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. elfcpp/ * mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename CPU_LOONGSON_3A to CPU_GS464. (mips_cpu_info_table): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * doc/as.texi (march table): Rename loongson3a to gs464. * testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension" flag to None. gold/ * mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach): Rename loongson3a to gs464. (mips_isa_ext_mach, mips_isa_ext): Delete loongson3a. (infer_abiflags): Use ases instead of isa_ext for infer ABI flags. (elf_mips_mach_name): Rename loongson3a to gs464. include/ * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A. * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A. (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464. * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a to gs464. opcodes/ * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * mips-opc.c (mips_opcodes): Change Comments.	8 years ago
Chenghua Xu	a693765e23	[MIPS/GAS] Add Loongson EXT2 Instructions support. bfd/ * elfxx-mips.c (print_mips_ases): Add Loongson EXT2 extension. binutils/ * readelf.c (print_mips_ases): Add Loongson EXT2 extension. gas/ * NEWS: Mention Loongson EXTensions R2 (EXT2) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT2 and OPTION_NO_LOONGSON_EXT2. (md_longopts): Likewise. (mips_ases): Define availability for EXT. (mips_convert_ase_flags): Map ASE_LOONGSON_EXT2 to AFL_ASE_LOONGSON_EXT2. (md_show_usage): Add help for -mloongson-ext2 and -mno-loongson-ext2. * doc/as.texi: Document -mloongson-ext2, -mno-loongson-ext2. * doc/c-mips.texi: Document -mloongson-ext2, -mno-loongson-ext2, .set loongson-ext2 and .set noloongson-ext2. * testsuite/gas/mips/loongson-ext2.d: New test. * testsuite/gas/mips/loongson-ext2.s: New test. * testsuite/gas/mips/mips.exp: Run loongson-ext2 test. include/ * elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2. * opcode/mips.h (ASE_LOONGSON_EXT2): New macro. opcodes/ * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext option. (print_mips_disassembler_options): Document -M loongson-ext. * mips-opc.c (LEXT2): New macro. (mips_opcodes): Add cto, ctz, dcto, dctz instructions.	8 years ago
Chenghua Xu	bdc6c06e3b	[MIPS/GAS] Split Loongson EXT Instructions from loongson3a. bfd/ * elfxx-mips.c (infer_mips_abiflags): Use ases instead of isa_ext for infer ABI flags. (print_mips_ases): Add Loongson EXT extension. binutils/ * readelf.c (print_mips_ases): Add Loongson EXT extension. elfcpp/ * mips.h (AFL_ASE_LOONGSON_EXT): New enum. gas/ * NEWS: Mention Loongson EXTensions (EXT) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and OPTION_NO_LOONGSON_EXT. (md_longopts): Likewise. (mips_ases): Define availability for EXT. (mips_convert_ase_flags): Map ASE_LOONGSON_EXT to AFL_ASE_LOONGSON_EXT. (mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a. (md_show_usage): Add help for -mloongson-ext and -mno-loongson-ext. * doc/as.texi: Document -mloongson-ext, -mno-loongson-ext. * doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext, .set loongson-ext and .set noloongson-ext. * testsuite/gas/mips/loongson-mmi.d: Add ASE flag. include/ * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT. * opcode/mips.h (ASE_LOONGSON_EXT): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add EXT to loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-ext option. (print_mips_disassembler_options): Document -M loongson-ext. * mips-opc.c (IL3A): Delete. * mips-opc.c (LEXT): New macro. (mips_opcodes): Replace IL2F\|IL3A marking with LEXT for EXT instructions.	8 years ago
Chenghua Xu	716c08de28	[MIPS/GAS] Split Loongson CAM Instructions from loongson3a bfd/ * elfxx-mips.c (print_mips_ases): Add CAM extension. binutils/ * readelf.c (print_mips_ases): Add CAM extension. gas/ * NEWS: Mention Loongson Content Address Memory (CAM) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and OPTION_NO_LOONGSON_CAM. (md_longopts): Likewise. (mips_ases): Define availability for CAM. (mips_convert_ase_flags): Map ASE_LOONGSON_CAM to AFL_ASE_LOONGSON_CAM. (mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a. (md_show_usage): Add help for -mloongson-cam and -mno-loongson-cam. * doc/as.texi: Document -mloongson-cam, -mno-loongson-cam. * doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam, .set loongson-cam and .set noloongson-cam. * testsuite/gas/mips/loongson-3a-2.d: Move cam test to ... * testsuite/gas/mips/loongson-cam.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-3a-2.s: Move cam test to ... * testsuite/gas/mips/loongson-cam.s: Here. * testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag. * testsuite/gas/mips/mips.exp: Run loongson-cam test. include/ * elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM. * opcode/mips.h (ASE_LOONGSON_CAM): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add CAM to loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-cam option. (print_mips_disassembler_options): Document -M loongson-cam. * mips-opc.c (LCAM): New macro. (mips_opcodes): Replace IL2F\|IL3A marking with LCAM for CAM instructions.	8 years ago
H.J. Lu	a9eafb08b3	x86: Update GNU_PROPERTY_X86_XXX macros This patch updates GNU_PROPERTY_X86_XXX macros: 1. GNU_PROPERTY_X86_UINT32_AND_XXX: A 4-byte unsigned integer property. A bit is set if it is set in all relocatable inputs: #define GNU_PROPERTY_X86_UINT32_AND_LO 0xc0000002 #define GNU_PROPERTY_X86_UINT32_AND_HI 0xc0007fff 2. GNU_PROPERTY_X86_UINT32_OR_XXX: A 4-byte unsigned integer property. A bit is set if it is set in any relocatable inputs: #define GNU_PROPERTY_X86_UINT32_OR_LO 0xc0008000 #define GNU_PROPERTY_X86_UINT32_OR_HI 0xc000ffff 3. GNU_PROPERTY_X86_UINT32_OR_AND_XXX: A 4-byte unsigned integer property. A bit is set if it is set in any relocatable inputs and the property is present in all relocatable inputs: #define GNU_PROPERTY_X86_UINT32_OR_AND_LO 0xc0010000 #define GNU_PROPERTY_X86_UINT32_OR_AND_HI 0xc0017fff 4. GNU_PROPERTY_X86_FEATURE_2_NEEDED, GNU_PROPERTY_X86_FEATURE_2_USED and GNU_PROPERTY_X86_FEATURE_2_XXX bits. GNU_PROPERTY_X86_FEATURE_1_AND is unchanged. GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED are updated to better support targeted processors since GNU_PROPERTY_X86_ISA_1_?86 aren't isn't very useful. A new set of GNU_PROPERTY_X86_ISA_1_XXX bits are defined. The previous GNU_PROPERTY_X86_ISA_1_XXX macros are deprecated and renamed to GNU_PROPERTY_X86_COMPAT_ISA_1_XXX. bfd/ * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Handle X86_COMPAT_ISA_1_USED, X86_COMPAT_ISA_1_NEEDED, X86_UINT32_AND_LO, X86_UINT32_AND_HI, X86_UINT32_OR_LO, X86_UINT32_OR_HI, X86_UINT32_OR_AND_LO and X86_UINT32_OR_AND_HI instead of X86_ISA_1_USED, X86_ISA_1_NEEDED and X86_FEATURE_1_AND. (_bfd_x86_elf_merge_gnu_properties): Likewise. (_bfd_x86_elf_link_setup_gnu_properties): Add X86_FEATURE_2_NEEDED instead of X86_ISA_1_NEEDED. (_bfd_x86_elf_link_fixup_gnu_properties): Handle X86_COMPAT_ISA_1_USED, X86_COMPAT_ISA_1_NEEDED, X86_UINT32_AND_LO, X86_UINT32_AND_HI, X86_UINT32_OR_LO, X86_UINT32_OR_HI, X86_UINT32_OR_AND_LO and X86_UINT32_OR_AND_HI instead of X86_ISA_1_USED, X86_ISA_1_NEEDED and X86_FEATURE_1_AND. binutils/ * readelf.c (decode_x86_compat_isa): New function. (decode_x86_feature_2): Likewise. (decode_x86_isa): Updated for new X86_ISA_1_XXX bits. (decode_x86_feature): Renamed to ... (decode_x86_feature_1): This. Remove the type argument. (print_gnu_property_note): Handle X86_COMPAT_ISA_1_USED, X86_COMPAT_ISA_1_NEEDED, X86_UINT32_AND_LO, X86_UINT32_AND_HI, X86_UINT32_OR_LO, X86_UINT32_OR_HI, X86_UINT32_OR_AND_LO and X86_UINT32_OR_AND_HI instead of X86_ISA_1_USED, X86_ISA_1_NEEDED and X86_FEATURE_1_AND. * testsuite/binutils-all/i386/pr21231b.s: Updated to the current GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED values. * testsuite/binutils-all/x86-64/pr21231b.s: Likewise. * testsuite/binutils-all/x86-64/pr23494a.s: Likewise. * testsuite/binutils-all/x86-64/pr23494b.s: Likewise. * testsuite/binutils-all/x86-64/pr23494c.s: Likewise. * testsuite/binutils-all/i386/pr21231b.d: Updated. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e.d: Likewise. include/ * elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ... (GNU_PROPERTY_X86_COMPAT_ISA_1_USED): This. (GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ... (GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED): This. (GNU_PROPERTY_X86_ISA_1_XXX): Renamed to ... (GNU_PROPERTY_X86_COMPAT_ISA_1_XXX): This. (GNU_PROPERTY_X86_UINT32_AND_LO): New. (GNU_PROPERTY_X86_UINT32_AND_HI): Likewise. (GNU_PROPERTY_X86_UINT32_OR_LO): Likewise. (GNU_PROPERTY_X86_UINT32_OR_HI): Likewise. (GNU_PROPERTY_X86_UINT32_OR_AND_LO): Likewise. (GNU_PROPERTY_X86_UINT32_OR_AND_HI): Likewise. (GNU_PROPERTY_X86_ISA_1_CMOV): Likewise. (GNU_PROPERTY_X86_ISA_1_SSE): Likewise. (GNU_PROPERTY_X86_ISA_1_SSE2): Likewise. (GNU_PROPERTY_X86_ISA_1_SSE3): Likewise. (GNU_PROPERTY_X86_ISA_1_SSSE3): Likewise. (GNU_PROPERTY_X86_ISA_1_SSE4_1): Likewise. (GNU_PROPERTY_X86_ISA_1_SSE4_2): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX2): Likewise. (GNU_PROPERTY_X86_ISA_1_FMA): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512F): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512CD): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512ER): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512PF): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512VL): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512DQ): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512BW): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_BITALG): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_IFMA): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_VBMI): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2): Likewise. (GNU_PROPERTY_X86_ISA_1_AVX512_VNNI): Likewise. (GNU_PROPERTY_X86_FEATURE_2_X86): Likewise. (GNU_PROPERTY_X86_FEATURE_2_X87): Likewise. (GNU_PROPERTY_X86_FEATURE_2_MMX): Likewise. (GNU_PROPERTY_X86_FEATURE_2_XMM): Likewise. (GNU_PROPERTY_X86_FEATURE_2_YMM): Likewise. (GNU_PROPERTY_X86_FEATURE_2_ZMM): Likewise. (GNU_PROPERTY_X86_FEATURE_2_FXSR): Likewise. (GNU_PROPERTY_X86_FEATURE_2_XSAVE): Likewise. (GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT): Likewise. (GNU_PROPERTY_X86_FEATURE_2_XSAVEC): Likewise. (GNU_PROPERTY_X86_FEATURE_1_AND): Updated to (GNU_PROPERTY_X86_UINT32_AND_LO + 0). (GNU_PROPERTY_X86_ISA_1_NEEDED): Defined to (GNU_PROPERTY_X86_UINT32_OR_LO + 0). (GNU_PROPERTY_X86_FEATURE_2_NEEDED): New. Defined to (GNU_PROPERTY_X86_UINT32_OR_LO + 1). (GNU_PROPERTY_X86_ISA_1_USED): Defined to (GNU_PROPERTY_X86_UINT32_OR_AND_LO + 0). (GNU_PROPERTY_X86_FEATURE_2_USED): New. Defined to (GNU_PROPERTY_X86_UINT32_OR_AND_LO + 1). ld/ * testsuite/ld-i386/i386.exp: Run pr23372c, pr23372d, pr23486c and pr23486d. * testsuite/ld-i386/pr23372a.s: Update comments. * testsuite/ld-i386/pr23372b.s: Likewise. * testsuite/ld-i386/pr23372c.s: Likewise. * testsuite/ld-x86-64/pr23372a.s: Likewise. * testsuite/ld-x86-64/pr23372b.s: Likewise. * testsuite/ld-x86-64/pr23372c.s: Likewise. * testsuite/ld-x86-64/pr23486a.s: Likewise. * testsuite/ld-x86-64/pr23486b.s: Likewise. * testsuite/ld-i386/pr23372c.d: New file. * testsuite/ld-i386/pr23372d.d: Likewise. * testsuite/ld-i386/pr23486c.d: Likewise. * testsuite/ld-i386/pr23486d.d: Likewise. * testsuite/ld-x86-64/pr23372c-x32.d: Likewise. * testsuite/ld-x86-64/pr23372c.d: Likewise. * testsuite/ld-x86-64/pr23372d-x32.d: Likewise. * testsuite/ld-x86-64/pr23372d.d: Likewise. * testsuite/ld-x86-64/pr23372d.s: Likewise. * testsuite/ld-x86-64/pr23372e.s: Likewise. * testsuite/ld-x86-64/pr23372f.s: Likewise. * testsuite/ld-x86-64/pr23486c-x32.d: Likewise. * testsuite/ld-x86-64/pr23486c.d: Likewise. * testsuite/ld-x86-64/pr23486c.s: Likewise. * testsuite/ld-x86-64/pr23486d-x32.d: Likewise. * testsuite/ld-x86-64/pr23486d.d: Likewise. * testsuite/ld-x86-64/pr23486d.s: Likewise. * testsuite/ld-i386/property-3.r: Updated. * testsuite/ld-i386/property-4.r: Likewise. * testsuite/ld-i386/property-5.r: Likewise. * testsuite/ld-i386/property-x86-3.d: Likewise. * testsuite/ld-i386/property-x86-ibt3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3b.d: Likewise. * testsuite/ld-x86-64/property-3.r: Likewise. * testsuite/ld-x86-64/property-4.r: Likewise. * testsuite/ld-x86-64/property-5.r: Likewise. * testsuite/ld-x86-64/property-x86-3-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-3.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise. * testsuite/ld-i386/property-x86-1.S: Updated to the current GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED values. * testsuite/ld-i386/property-x86-2.S: Likewise. * testsuite/ld-i386/property-x86-3.s: Likewise. * testsuite/ld-x86-64/property-x86-1.S: Likewise. * testsuite/ld-x86-64/property-x86-2.S: Likewise. * testsuite/ld-x86-64/property-x86-3.s: Likewise. * ld/testsuite/ld-x86-64/x86-64.exp: Run pr23372c, pr23372c-x32, pr23372d, pr23372d-x32, pr23486c, pr23486c-x32, pr23486d and pr23486d-x32.	8 years ago
H.J. Lu	aa7bca9b2e	x86: Add GNU_PROPERTY_X86_UINT32_VALID The older linker treats .note.gnu.property section as a generic note and just concatenates all .note.gnu.property sections from the input to the output. On CET-enabled OS, the output of the older linker is marked as CET enabled, but in fact, it is not CET enabled and it crashes on CET-enabled machines. This patch defines GNU_PROPERTY_X86_UINT32_VALID. Linker is updated to set the GNU_PROPERTY_X86_UINT32_VALID bit in GNU property note for non-relocatable output to differentiate outputs from the older linker. bfd/ * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Mask out the GNU_PROPERTY_X86_UINT32_VALID bit. (_bfd_x86_elf_link_fixup_gnu_properties): Set the GNU_PROPERTY_X86_UINT32_VALID bit for non-relocatable output. binutils/ * readelf.c (print_gnu_property_note): Check the GNU_PROPERTY_X86_UINT32_VALID bit for invalid GNU property note. include/ * elf/common.h (GNU_PROPERTY_X86_UINT32_VALID): New.	8 years ago
Alan Modra	ebf983a444	Fix changelog entries	8 years ago
John Darrington	4e57b45639	S12Z: Rename reloc R_S12Z_UKNWN_3 to R_S12Z_EXT18 and implement according to recently inferred information about this reloc. * bfd/elf32-s12z.c: (opru18_reloc): New function. * bfd/elf32-s12z.c: (elf_s12z_howto_table): Adjust Howto according to new knowledge. * include/elf/s12z.h: Rename R_S12Z_UKNWN_3 to R_S12Z_EXT18.	8 years ago
Alan Modra	9cf7e5687f	Use operand->extract to provide defaults for optional PowerPC operands Most optional operands to powerpc instructions use a default value of zero, but there are a few exceptions. Those have been handled by PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table for the default value, smuggled in the shift field. This patch changes that to using the operand extract function to provide non-zero defaults. I've also moved the code determining whether optional operands are provided or omitted, to the point the first optional operand is seen, and allowed for the possibility of optional base register operands in a future patch. The patch does change the error you get on invalid assembly like ld 3,4 You'll now see "missing operand" rather than "syntax error; end of line, expected `('". gas/ * config/tc-ppc.c (md_assemble): Delay counting of optional operands until one is encountered. Allow for the possibility of optional base regs, ie. PPC_OPERAND_PARENS. Call ppc_optional_operand_value with extra args. include/ * opcode/ppc.h (struct powerpc_operand): Correct "insert" comment. Mention use of "extract" function to provide default value. (PPC_OPERAND_OPTIONAL_VALUE): Delete. (ppc_optional_operand_value): Rewrite to use extract function. opcodes/ * ppc-dis.c (operand_value_powerpc): Init "invalid". (skip_optional_operands): Count optional operands, and update ppc_optional_operand_value call. * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg. (extract_vlensi): Likewise. (extract_fxm): Return default value for missing optional operand. (extract_ls, extract_raq, extract_tbr): Likewise. (insert_sxl, extract_sxl): New functions. (insert_esync, extract_esync): Remove Power9 handling and simplify. (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE flag and extra entry. (powerpc_operands <SXL>): Likewise, and use insert_sxl and extract_sxl.	8 years ago
Alan Modra	08a8fe2ffd	Fix s12z test regexps Fixes ERROR: tcl error sourcing .../gas/testsuite/gas/s12z/s12z.exp. ERROR: couldn't compile regular expression pattern: quantifier operand invalid run_dump_test expected output lines are regexps. * testsuite/gas/s12z/bit-manip-invalid.d: Correct regexps.	8 years ago
Alan Modra	d203b41ac7	Tidy bit twiddling * sh-opc.h (MASK): Simplify.	8 years ago
John Darrington	7ba3ba91a3	S12Z: Move opcode header to public include directory. opcodes/ * s12z.h: Delete. * s12z-dis.c: Adjust path of included file. include/ * opcode/s12z.h: New file. gas/ * config/tc-s12z.c: Adjust path of included file.	8 years ago
Richard Earnshaw	57285adece	arm - Add some comments about the versions of ARM ELF that define various e_flags values This patch adds a few comments to include/elf/arm.h to clarify which versions of the ARM ELF specification defined which headers. Given that the EABI is pretty ubiquitous these days, I've marked anything not based on that as deprecated. There are no plans to remove any deprecated definitions at this time, but any new development shouldn't be building upon support for deprecated definitions remaining in the long term. * elf/arm.h: Updated comments for e_flags definitions.	8 years ago
claziss	db1e1b45b4	[ARC] Add Tag_ARC_ATR_version. Add a new tag (Tag_ARC_ATR_version) used to indicate if current attributes are interpreted in GNU way. This attribute is used by Synopsys custom compiler to correctly identify and interpret the object attributes section as generated by GNU tools. gas/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_set_public_attributes): Add Tag_ARC_ATR_version. (arc_convert_symbolic_attribute): Likewise. * testsuite/gas/arc/attr-arc600.d: Update test. * testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc600_norm.d: Likewise. * testsuite/gas/arc/attr-arc601.d: Likewise. * testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc601_mul64.d: Likewise. * testsuite/gas/arc/attr-arc601_norm.d: Likewise. * testsuite/gas/arc/attr-arc700.d: Likewise. * testsuite/gas/arc/attr-arcem.d: Likewise. * testsuite/gas/arc/attr-archs.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.d: Likewise. * testsuite/gas/arc/attr-cpu-a601.d: Likewise. * testsuite/gas/arc/attr-cpu-a700.d: Likewise. * testsuite/gas/arc/attr-cpu-em.d: Likewise. * testsuite/gas/arc/attr-cpu-hs.d: Likewise. * testsuite/gas/arc/attr-em.d: Likewise. * testsuite/gas/arc/attr-em4.d: Likewise. * testsuite/gas/arc/attr-em4_dmips.d: Likewise. * testsuite/gas/arc/attr-em4_fpuda.d: Likewise. * testsuite/gas/arc/attr-em4_fpus.d: Likewise. * testsuite/gas/arc/attr-hs.d: Likewise. * testsuite/gas/arc/attr-hs34.d: Likewise. * testsuite/gas/arc/attr-hs38.d: Likewise. * testsuite/gas/arc/attr-hs38_linux.d: Likewise. * testsuite/gas/arc/attr-mul64.d: Likewise. * testsuite/gas/arc/attr-name.d: Likewise. * testsuite/gas/arc/attr-nps400.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.d: Likewise. * testsuite/gas/arc/attr-quarkse_em.d: Likewise. bfd/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * elf32-arc.c (arc_elf_merge_attributes): Handle Tag_ARC_ATR_version. binutils/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (display_arc_attribute): Print Tag_ARC_ATR_version. include/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * elf/arc.h (Tag_ARC_ATR_version): New tag. ld/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/attr-merge-0.d: Update test. * testsuite/ld-arc/attr-merge-1.d: Likewise. * testsuite/ld-arc/attr-merge-2.d: Likewise. * testsuite/ld-arc/attr-merge-3.d: Likewise. * testsuite/ld-arc/attr-merge-5.d: Likewise.	8 years ago
claziss	b6523c37fb	[ARC] Update handling AUX-registers. Update aux-registers data-base, and accept aux-registers names with upper/lowercase names. opcode/ 2017-07-18 Claudiu Zissulescu <claziss@synopsys.com> * arc-regs.h: Update aux-registers. gas/ 2017-07-18 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (find_opcode_match): Accept uppercase aux-regs names. * testsuite/gas/arc/ld2.d: Update test. * testsuite/gas/arc/taux.d: Likewise. * testsuite/gas/arc/taux.s: Likewise. include/ 2017-07-18 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (ARC_OPCODE_ARCV1): Define.	8 years ago
marxin	50320b1d4a	Copy from GCC: Add linker_output as prefix for LTO temps (PR lto/86548). 2018-07-26 Martin Liska <mliska@suse.cz> PR lto/86548 * libiberty.h (make_temp_file_with_prefix): New function. 2018-07-26 Martin Liska <mliska@suse.cz> PR lto/86548 * make-temp-file.c (TEMP_FILE): Remove leading 'cc'. (make_temp_file): Call make_temp_file_with_prefix with first argument set to NULL. (make_temp_file_with_prefix): Support also prefix. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@262999 138bc75d-0d04-0410-961f-82ee72b054a4	8 years ago
Jim Wilson	eb41b24898	RISC-V: Set insn info fields correctly when disassembling. include/ * opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR) (INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE) (INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size fields. * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.	8 years ago
Andrew Jenner	b8891f8d62	Add support for the C_SKY series of processors. This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc. This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about. bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY. (BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise. * Makefile.in: Regenerated. * archures.c (enum bfd_architecture): Add bfd_arch_csky and related bfd_mach defines. (bfd_csky_arch): Declare. (bfd_archures_list): Add C-SKY. * bfd-in.h (elf32_csky_build_stubs): Declare. (elf32_csky_size_stubs): Declare. (elf32_csky_next_input_section: Declare. (elf32_csky_setup_section_lists): Declare. * bfd-in2.h: Regenerated. * config.bfd: Add C-SKY. * configure.ac: Likewise. * configure: Regenerated. * cpu-csky.c: New file. * elf-bfd.h (enum elf_target_id): Add C-SKY. * elf32-csky.c: New file. * libbfd.h: Regenerated. * reloc.c: Add C-SKY relocations. * targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare. (_bfd_target_vector): Add C-SKY target vector entries. binutils* readelf.c: Include elf/csky.h. (guess_is_rela): Handle EM_CSKY. (dump_relocations): Likewise. (get_machine_name): Likewise. (is_32bit_abs_reloc): Likewise. include * dis-asm.h (csky_symbol_is_valid): Declare. * opcode/csky.h: New file. opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c. * Makefile.in: Regenerated. * configure.ac: Add C-SKY. * configure: Regenerated. * csky-dis.c: New file. * csky-opc.h: New file. * disassemble.c (ARCH_csky): Define. (disassembler, disassemble_init_for_target): Add case for ARCH_csky. * disassemble.h (print_insn_csky, csky_get_disassembler): Declare. gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY. (TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise. * Makefile.in: Regenerated. * config/tc-csky.c: New file. * config/tc-csky.h: New file. * config/te-csky_abiv1.h: New file. * config/te-csky_abiv1_linux.h: New file. * config/te-csky_abiv2.h: New file. * config/te-csky_abiv2_linux.h: New file. * configure.tgt: Add C-SKY. * doc/Makefile.am (CPU_DOCS): Add entry for C-SKY. * doc/Makefile.in: Regenerated. * doc/all.texi: Set CSKY feature. * doc/as.texi (Overview): Add C-SKY options. (Machine Dependencies): Likewise. * doc/c-csky.texi: New file. * testsuite/gas/csky/: New test cases. ld Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations. (ecskyelf.c, ecskyelf_linux.c): New rules. * Makefile.in: Regenerated. * configure.tgt: Add C-SKY. * emulparams/cskyelf.sh: New file. * emulparams/cskyelf_linux.sh: New file. * emultempl/cskyelf.em: New file. * gen-doc.texi: Add C-SKY. * ld.texi: Likewise. (Options specific to C-SKY targets): New section. * testsuite/ld-csky/*: New tests.	8 years ago
Chenghua Xu	2bb9bbe2e8	MIPS/GAS: Correct the AFL_ASE_MASK macro Fix an issue with commit `8095d2f70e` ("MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a"), AFL_ASE_MASK should be 0x0006ffff instead of 0x0004ffff. 2018-07-27 Chenghua Xu <paul.hua.gm@gmail.com> Maciej W. Rozycki <macro@linux-mips.org> include/ * elf/mips.h (AFL_ASE_MASK): Correct typo.	8 years ago
Alex Chadwick	fa758a7046	PowerPC Improve support for Gekko & Broadway This is a relatively straightforward patch to improve support for the IBM Gekko and IBM Broadway processors. Broadway is functionally equivalent to the IBM 750CL, while Gekko's functionality is a subset of theirs. The patch simplifies this reality and adds -mgekko and -mbroadway as aliases for -m750cl. I didn't feel it was worth wasting a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of simplified mnemonics for special purpose register access. Notably, Broadway adds 4 additional IBAT and DBAT registers but these are not assigned sequential SPR numbers. gas/ * config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway. * doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * testsuite/gas/ppc/broadway.d, * testsuite/gas/ppc/broadway.s: New test for broadway. * testsuite/gas/ppc/ppc.exp: Run new test. include/ * opcode/ppc.h (PPC_OPCODE_750): Adjust comment. opcodes/ * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. (powerpc_init_dialect): Handle bfd_mach_ppc_750. * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to support disjointed BAT. (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. (XSPRGQR_MASK, GEKKO, BROADWAY): Define. (powerpc_opcodes): Add 750cl extended mnemonics for spr access.	8 years ago
Alan Modra	33cb30a1f9	Implement PowerPC64 .localentry for value 1 This adds support for ".localentry 1", a new st_other STO_PPC64_LOCAL_MASK encoding that signifies a function with a single entry point like ".localentry 0", but unlike a ".localentry 0" function does not preserve r2. include/ * elf/ppc64.h: Specify byte offset to local entry for values of two to six in STO_PPC64_LOCAL_MASK. Clarify r2 return value for such functions when entering via global entry point. Specify meaning of a value of one in STO_PPC64_LOCAL_MASK. bfd/ * elf64-ppc.c (ppc64_elf_size_stubs): Use a ppc_stub_long_branch_r2off for calls to symbols with STO_PPC64_LOCAL_MASK bits set to 1. gas/ * config/tc-ppc.c (ppc_elf_localentry): Allow .localentry values of 1 and 7 to directly set value into STO_PPC64_LOCAL_MASK bits. ld/testsuite/ * ld-powerpc/elfv2.s: Add .localentry f5,1 testcase. * ld-powerpc/elfv2exe.d: Update. * ld-powerpc/elfv2so.d: Update.	8 years ago
Alan Modra	67ce483baa	PR23430, Indices misspelled PR 23430 include/ * elf/common.h (SHT_SYMTAB_SHNDX): Fix comment typo. bfd/ * dwarf2.c (dwarf_debug_section_enum): Fix comment typo. * elf.c (bfd_section_from_shdr, elf_sort_sections): Likewise. binutils/ * elfcomm.h (struct archive_info): Rename uses_64bit_indicies to uses_64bit_indices. * elfcomm.c (setup_archive): Update uses of above. * readelf.c (process_archive): Likewise. (get_section_type_name): Rename indicies to indices. (get_32bit_elf_symbols, get_64bit_elf_symbols): Likewise. (process_section_groups): Likewise. cpu/ * or1kcommon.cpu (spr-reg-indices): Fix description typo. opcodes/ * or1k-desc.h: Regenerate.	8 years ago
Chenghua Xu	8095d2f70e	MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a The MMI instruction set has been implemented in many Loongson processors. There is a lot of software optimized for MMI. This patch splits MMI from loongson2f/3a, and adds GAS and disassembler options for MMI instructions. 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com> Maciej W. Rozycki <macro@mips.com> bfd/ * elfxx-mips.c (print_mips_ases): Add MMI extension. binutils/ * readelf.c (print_mips_ases): Add MMI extension. gas/ * NEWS: Mention MultiMedia extensions Instructions (MMI) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and OPTION_NO_LOONGSON_MMI. (md_longopts): Likewise. (mips_ases): Define availability for MMI. (mips_convert_ase_flags): Map ASE_LOONGSON_MMI to AFL_ASE_LOONGSON_MMI. (mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a. (md_show_usage): Add help for -mloongson-mmi and -mno-loongson-mmi. * doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi. * doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi, .set loongson-mmi and .set noloongson-mmi. * testsuite/gas/mips/loongson-2f.d: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-2f.s: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.s: Here. * testsuite/gas/mips/loongson-3a.d: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-3a.s: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.s: Here. * testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and loongson-3a-mmi tests. include/ * elf/mips.h (AFL_ASE_MMI): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI. * opcode/mips.h (ASE_LOONGSON_MMI): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-mmi option. (print_mips_disassembler_options): Document -M loongson-mmi. * mips-opc.c (LMMI): New macro. (mips_opcodes): Replace IL2F\|IL3A marking with LMMI for MMI instructions.	8 years ago
Maciej W. Rozycki	d5c928c053	LD: Export relative-from-absolute symbol marking to BFD It is usually possible to tell absolute and ordinary symbols apart in BFD throughout the link, by checking whether the section that owns the symbol is absolute or not. That however does not work for ordinary symbols defined in a linker script outside an output section statement. Initially such symbols are entered into to the link hash as absolute symbols, owned by the absolute section. A flag is set in the internal linker expression defining such symbols to tell the linker to convert them to section-relative ones in the final phase of the link. That flag is however not accessible to BFD linker code, including BFD target code in particular. Add a flag to the link hash then to copy the information held in the linker expression. Define a macro, `bfd_is_abs_symbol', for BFD code to use where determining whether a symbol is absolute or ordinary is required before the final link phase. This macro will correctly identify the special `__ehdr_start' symbol as ordinary throughout link, for example, even though early on it will be assigned to the absolute section. Of course this does not let BFD code identify what the symbol's ultimate section will be before the final link phase has converted this symbol (in `update_definedness'). include/ * bfdlink.h (bfd_link_hash_entry): Add `rel_from_abs' member. bfd/ * linker.c (bfd_is_abs_symbol): New macro. * bfd-in2.h: Regenerate. ld/ * ldexp.c (exp_fold_tree_1) <etree_assign, etree_provide> <etree_provided>: Copy expression's `rel_from_abs' flag to the link hash.	8 years ago
Alan Modra	fe75810f8e	Fix diagnostic errors Fixes a number of build errors like the following .../elf32-arm.c: In function 'elf32_arm_nabi_write_core_note': .../elf32-arm.c:2177: error: #pragma GCC diagnostic not allowed inside functions .../elf32-arm.c:2186: error: #pragma GCC diagnostic not allowed inside functions See the comment in diagnostics.h. include/ * diagnostics.h: Comment on macro usage. bfd/ * elf32-arm.c (elf32_arm_nabi_write_core_note): Don't use DIAGNOTIC_PUSH and DIAGNOSTIC_POP unconditionally. * elf32-ppc.c (ppc_elf_write_core_note): Likewise. * elf32-s390.c (elf_s390_write_core_note): Likewise. * elf64-ppc.c (ppc64_elf_write_core_note): Likewise. * elf64-s390.c (elf_s390_write_core_note): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_write_core_note): Likewise.	8 years ago
Simon Marchi	6821842f15	darwin: Silence syscall deprecated declaration warning This patch silences this warning: /Users/simark/src/binutils-gdb/gdb/darwin-nat.c:839:10: error: 'syscall' is deprecated: first deprecated in macOS 10.12 - syscall(2) is unsupported; please switch to a supported interface. For SYS_kdebug_trace use kdebug_signpost(). [-Werror,-Wdeprecated-declarations] res = syscall (SYS___pthread_kill, thread->gdb_port, nsignal); ^ /usr/include/unistd.h:745:6: note: 'syscall' has been explicitly marked deprecated here int syscall(int, ...); ^ The comment of the new pthread_kill function explains why we use the syscall function directly. include/ChangeLog: * diagnostics.h (DIAGNOSTIC_IGNORE_DEPRECATED_DECLARATIONS): Define for clang. gdb/ChangeLog: * darwin-nat.c (darwin_pthread_kill): New function. (darwin_resume_thread): Use darwin_pthread_kill.	8 years ago
Maciej W. Rozycki	471b9d1507	GDB PR tdep/8282: MIPS: Wire in `set disassembler-options' Implement MIPS target support for passing options to the disassembler, complementing commit `65b48a8140` ("GDB: Add support for the new set/show disassembler-options commands."). This includes options that expect an argument, so adjust the generic code and data structures used so as to handle such options. So as to give backends syntax flexibility no specific delimiter has been defined to separate options from their respective arguments, so it has to be included as the last character of the option name. Completion code however has not been adjusted and consequently option arguments cannot be completed at this time. Also the MIPS target has non-empty defaults for the options, so that ABI names for the general-purpose registers respect our `set mips abi ...' setting rather than always being determined from the ELF headers of the binary file selected. Handle these defaults as implicit options, never shown to the user and always prepended to the user-specified options, so that the latters can override the defaults. The resulting output for the MIPS target is as follows: (gdb) show disassembler-options The current disassembler options are '' The following disassembler options are supported for use with the 'set disassembler-options <option>[,<option>...]' command: no-aliases Use canonical instruction forms. msa Recognize MSA instructions. virt Recognize the virtualization ASE instructions. xpa Recognize the eXtended Physical Address (XPA) ASE instructions. ginv Recognize the Global INValidate (GINV) ASE instructions. gpr-names=ABI Print GPR names according to specified ABI. Default: based on binary being disassembled. fpr-names=ABI Print FPR names according to specified ABI. Default: numeric. cp0-names=ARCH Print CP0 register names according to specified architecture. Default: based on binary being disassembled. hwr-names=ARCH Print HWR names according to specified architecture. Default: based on binary being disassembled. reg-names=ABI Print GPR and FPR names according to specified ABI. reg-names=ARCH Print CP0 register and HWR names according to specified architecture. For the options above, the following values are supported for "ABI": numeric 32 n32 64 For the options above, the following values are supported for "ARCH": numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600 r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000 r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64 mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp (gdb) which corresponds to what `objdump --help' used to print for the MIPS target, with minor formatting changes, most notably option argument lists being wrapped, but also the amount of white space separating options from the respective descriptions. The relevant part the new code is now also used by `objdump --help', which means these formatting changes apply to both outputs, except for argument list wrapping, which is GDB-specific. This also adds a separating new line between the heading and option lists where descriptions are provided, hence: (gdb) set architecture s390:31-bit (gdb) show disassembler-options The current disassembler options are '' The following disassembler options are supported for use with the 'set disassembler-options <option>[,<option>...]' command: esa Disassemble in ESA architecture mode zarch Disassemble in z/Architecture mode insnlength Print unknown instructions according to length from first two bits (gdb) but: (gdb) set architecture powerpc:common (gdb) show disassembler-options The current disassembler options are '' The following disassembler options are supported for use with the 'set disassembler-options <option>[,<option>...]' command: 403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl, 821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300, e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5, power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge, ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe, spe2, titan, vle, vsx (gdb) Existing affected target backends have been adjusted accordingly. This has been verified manually with: (gdb) set architecture arm (gdb) set architecture powerpc:common (gdb) set architecture s390:31-bit to cause no issues with the `show disassembler-options' and `set disassembler-options' commands. A test case for the MIPS target has also been provided, covering the default settings with ABI overrides as well as disassembler option overrides. 2018-07-02 Maciej W. Rozycki <macro@mips.com> Simon Marchi <simon.marchi@polymtl.ca> include/ PR tdep/8282 * dis-asm.h (disasm_option_arg_t): New typedef. (disasm_options_and_args_t): Likewise. (disasm_options_t): Add `arg' member, document members. (disassembler_options_mips): New prototype. (disassembler_options_arm, disassembler_options_powerpc) (disassembler_options_s390): Update prototypes. opcodes/ PR tdep/8282 * mips-dis.c (mips_option_arg_t): New enumeration. (mips_options): New variable. (disassembler_options_mips): New function. (print_mips_disassembler_options): Reimplement in terms of `disassembler_options_mips'. * arm-dis.c (disassembler_options_arm): Adapt to using the `disasm_options_and_args_t' structure. * ppc-dis.c (disassembler_options_powerpc): Likewise. * s390-dis.c (disassembler_options_s390): Likewise. gdb/ PR tdep/8282 * disasm.h (gdb_disassembler): Add `m_disassembler_options_holder'. member * disasm.c (get_all_disassembler_options): New function. (gdb_disassembler::gdb_disassembler): Use it. (gdb_buffered_insn_length_init_dis): Likewise. (gdb_buffered_insn_length): Adjust accordingly. (set_disassembler_options): Handle options with arguments. (show_disassembler_options_sfunc): Likewise. Add a leading new line if showing options with descriptions. (disassembler_options_completer): Adapt to using the `disasm_options_and_args_t' structure. * mips-tdep.c (mips_disassembler_options): New variable. (mips_disassembler_options_o32): Likewise. (mips_disassembler_options_n32): Likewise. (mips_disassembler_options_n64): Likewise. (gdb_print_insn_mips): Don't set `disassembler_options'. (gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove functions. (mips_gdbarch_init): Always set `gdbarch_print_insn' to `gdb_print_insn_mips'. Set `gdbarch_disassembler_options', `gdbarch_disassembler_options_implicit' and `gdbarch_valid_disassembler_options'. * arm-tdep.c (_initialize_arm_tdep): Adapt to using the `disasm_options_and_args_t' structure. * gdbarch.sh (disassembler_options_implicit): New `gdbarch' method. (valid_disassembler_options): Switch from `disasm_options_t' to the `disasm_options_and_args_t' structure. * NEWS: Document `set disassembler-options' support for the MIPS target. * gdbarch.h: Regenerate. * gdbarch.c: Regenerate. gdb/doc/ PR tdep/8282 * gdb.texinfo (Source and Machine Code): Document `set disassembler-options' support for the MIPS target. gdb/testsuite/ PR tdep/8282 * gdb.arch/mips-disassembler-options.exp: New test. * gdb.arch/mips-disassembler-options.s: New test source.	8 years ago
Tamar Christina	369c9167d4	Fix AArch64 encodings for by element instructions. Some instructions in Armv8-a place a limitation on FP16 registers that can be used as the register from which to select an element from. e.g. fmla restricts Rm to 4 bits when using an FP16 register. This restriction does not apply for all instructions, e.g. fcmla does not have this restriction as it gets an extra bit from the M field. Unfortunately, this restriction to S_H was added for all _Em operands before, meaning for a large number of instructions you couldn't use the full register file. This fixes the issue by introducing a new operand _Em16 which applies this restriction only when paired with S_H and leaves the _Em and the other qualifiers for _Em16 unbounded (i.e. using the full 5 bit range). Also the patch updates all instructions that should be affected by this. opcodes/ PR binutils/23192 * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. * aarch64-opc.c (operand_general_constraint_met_p, aarch64_print_operand): Likewise. * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, fmlal2, fmlsl2. (AARCH64_OPERANDS): Add Em2. gas/ PR binutils/23192 * config/tc-aarch64.c (process_omitted_operand, parse_operands): Add AARCH64_OPND_Em16 * testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper 16 registers. * testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise. * testsuite/gas/aarch64/advsimd-compnum.s: Likewise. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise. * testsuite/gas/aarch64/sve.d: Likewise. include/ PR binutils/23192 *opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.	8 years ago
Alan Modra	2393a7e3e6	Revert "Use offsets instead of addresses in ELF_SECTION_IN_SEGMENT for non SHT_NOBITS" This reverts commit `57c0d77c2c`.	8 years ago
Nick Clifton	719d828850	Add 2.30 branch notes to ChangeLogs and NEWS files.	8 years ago
Alan Hayward	57c0d77c2c	Use offsets instead of addresses in ELF_SECTION_IN_SEGMENT for non SHT_NOBITS For sections that are not SHT_NOBITS, use sh_offset and p_offset instead of sh_addr and p_vaddr when calculating if a section fits in a segment. Both methods are valid when using the GNU linker. include/ * elf/internal.h (ELF_SECTION_IN_SEGMENT): Don’t check addresses for non SHT_NOBITS.	8 years ago
Simon Marchi	d856f9a8d6	include: Sync with GCC Bring changes from GCC in shared headers. include/ChangeLog: Sync with GCC 2018-05-24 Tom Rix <trix@juniper.net> * dwarf2.def (DW_FORM_strx, DW_FORM_addrx): New. 2017-11-20 Kito Cheng <kito.cheng@gmail.com> * longlong.h [__riscv] (__umulsidi3): Define. [__riscv] (umul_ppmm): Likewise. [__riscv] (__muluw3): Likewise.	8 years ago
Simon Marchi	978588dc58	libiberty: Sync with GCC Also sync include/simple-object.h, which goes together with the change in libiberty.	8 years ago
Faraz Shahbazker	6f20c942c3	MIPS: Add Global INValidate ASE support Add support for the Global INValidate Application Specific Extension for Release 6 of the MIPS Architecture. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 187-191 bfd/ * elfxx-mips.c (print_mips_ases): Add GINV extension. binutils/ * readelf.c (print_mips_ases): Add GINV extension. gas/ * NEWS: Mention MIPS Global INValidate ASE support. * config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV. (md_longopts): Likewise. (mips_ases): Define availability for GINV. (mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV. (md_show_usage): Add help for -mginv and -mno-ginv. * doc/as.texinfo: Document -mginv, -mno-ginv. * doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and .set noginv. * testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV ASE. * testsuite/gas/mips/ase-errors-2.s: Likewise. * testsuite/gas/mips/ase-errors-1.l: Likewise. * testsuite/gas/mips/ase-errors-2.l: Likewise. * testsuite/gas/mips/ginv.d: New test. * testsuite/gas/mips/ginv-err.d: New test. * testsuite/gas/mips/ginv-err.l: New test stderr output. * testsuite/gas/mips/ginv.s: New test source. * testsuite/gas/mips/ginv-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. include/ * elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros. (AFL_ASE_MASK): Update to include AFL_ASE_GINV. * opcode/mips.h: Document "+\" operand format. (ASE_GINV): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and mips64r6 descriptors. (parse_mips_ase_option): Handle -Mginv option. (print_mips_disassembler_options): Document -Mginv. * mips-opc.c (decode_mips_operand) <+\>: New operand format. (GINV): New macro. (mips_opcodes): Define ginvi and ginvt.	8 years ago
Scott Egerton	730c31740a	MIPS: Add CRC ASE support Add support for the CRC Application Specific Extension for Release 6 of the MIPS Architecture. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 143-148 [2] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 165-170 ChangeLog: bfd/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * elfxx-mips.c (print_mips_ases): Add CRC. binutils/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * readelf.c (print_mips_ases): Add CRC. gas/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> Maciej W. Rozycki <macro@mips.com> * config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC. (md_longopts): Likewise. (md_show_usage): Add help for -mcrc and -mno-crc. (mips_ases): Define availability for CRC and CRC64. (mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC. * doc/as.texinfo: Document -mcrc, -mno-crc. * doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and .set no-crc. * testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC ASE. * testsuite/gas/mips/ase-errors-2.l: Likewise. * testsuite/gas/mips/ase-errors-1.s: Likewise. * testsuite/gas/mips/ase-errors-2.s: Likewise. * testsuite/gas/mips/crc.d: New test. * testsuite/gas/mips/crc64.d: New test. * testsuite/gas/mips/crc-err.d: New test. * testsuite/gas/mips/crc64-err.d: New test. * testsuite/gas/mips/crc-err.l: New test stderr output. * testsuite/gas/mips/crc64-err.l: New test stderr output. * testsuite/gas/mips/crc.s: New test source. * testsuite/gas/mips/crc64.s: New test source. * testsuite/gas/mips/crc-err.s: New test source. * testsuite/gas/mips/crc64-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. include/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * elf/mips.h (AFL_ASE_CRC): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_CRC. * opcode/mips.h (ASE_CRC): New macro. * opcode/mips.h (ASE_CRC64): Likewise. opcodes/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs. * mips-opc.c (CRC, CRC64): New macros. (mips_builtin_opcodes): Define crc32b, crc32h, crc32w, crc32cb, crc32ch and crc32cw for CRC. Define crc32d and crc32cd for CRC64.	8 years ago
Max Filippov	4b8e28c793	xtensa: use property tables for correct disassembly xtensa disassembler does not use information from the .xt.prop sections to switch between code/data disassembly in text sections. This may result in incorrect disassembly when data is interpreted as code and disassembler loses synchronization with instruction stream. Use .xt.prop section information to correctly interpret code and data and synchronize with instruction stream. 2018-06-04 Max Filippov <jcmvbkbc@gmail.com> bfd/ * elf32-xtensa.c (xtensa_read_table_entries): Make global. (compute_fill_extra_space): Drop declaration. Rename function to xtensa_compute_fill_extra_space. (compute_ebb_actions, remove_dead_literal): Update references to compute_fill_extra_space. include/ * elf/xtensa.h (xtensa_read_table_entries) (xtensa_compute_fill_extra_space): New declarations. opcodes/ * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes. (dis_private): Add new fields for property section tracking. (xtensa_coalesce_insn_tables, xtensa_find_table_entry) (xtensa_instruction_fits): New functions. (fetch_data): Bump minimal fetch size to 4. (print_insn_xtensa): Make struct dis_private static. Load and prepare property table on section change. Don't disassemble literals. Don't disassemble instructions that cross property table boundaries.	8 years ago
H.J. Lu	95da985446	Use DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION to silence GCC 8.1 GCC 8.1 warns about destination size with -Wstringop-truncation: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643 Use DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION to silence it. bfd/ PR binutils/23146 * bfd-in.h: Include "diagnostics.h". * bfd-in2.h: Regenerated. * elf32-arm.c (elf32_arm_nabi_write_core_note): Use DIAGNOSTIC_PUSH, DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION and DIAGNOSTIC_POP to silence GCC 8.1 warnings with -Wstringop-truncation. * elf32-ppc.c (ppc_elf_write_core_note): Likewse. * elf32-s390.c (elf_s390_write_core_note): Likewse. * elf64-ppc.c (ppc64_elf_write_core_note): Likewse. * elf64-s390.c (elf_s390_write_core_note): Likewse. * elfxx-aarch64.c (_bfd_aarch64_elf_write_core_note): Likewse. include/ * diagnostics.h (DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): Always define for GCC.	8 years ago
H.J. Lu	23081219bf	Add DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION Add DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION for GCC 8.1 to silence -Wstringop-truncation warning: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643 * diagnostics.h (DIAGNOSTIC_STRINGIFY_1): New. (DIAGNOSTIC_STRINGIFY): Likewise. (DIAGNOSTIC_IGNORE): Replace STRINGIFY with DIAGNOSTIC_STRINGIFY. (DIAGNOSTIC_IGNORE_SELF_MOVE): Define empty if not defined. (DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER): Likewise. (DIAGNOSTIC_IGNORE_UNUSED_FUNCTION): Likewise. (DIAGNOSTIC_IGNORE_SWITCH_DIFFERENT_ENUM_TYPES): Likewise. (DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): New.	8 years ago
H.J. Lu	e9cb46ab59	Move gdb/common/diagnostics.h to include/diagnostics.h Move gdb/common/diagnostics.h to include/diagnostics.h so that it can be used in binutils. gdb/ * ada-lex.l: Include "diagnostics.h" instead of "common/diagnostics.h". * unittests/environ-selftests.c: Likewise. * common/diagnostics.h: Moved to ../include. include/ * diagnostics.h: Moved from ../gdb/common/diagnostics.h.	8 years ago
edlinger	22467434fd	include: 2018-05-28 Bernd Edlinger <bernd.edlinger@hotmail.de> include: * splay-tree.h (splay_tree_compare_strings, splay_tree_delete_pointers): Declare new utility functions. libiberty: 2018-05-28 Bernd Edlinger <bernd.edlinger@hotmail.de> * splay-tree.c (splay_tree_compare_strings, splay_tree_delete_pointers): New utility functions. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260850 138bc75d-0d04-0410-961f-82ee72b054a4	8 years ago
Peter Bergner	98553ad33e	Remove fake operand handling for extended mnemonics. opcodes/ * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba, insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions. (insert_bab, extract_bab, insert_btab, extract_btab, insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions. (BAT, BBA VBA RBS XB6S): Delete macros. (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros. (BB, BD, RBX, XC6): Update for new macros. (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset, crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp, e_crnot, e_crclr, e_crset, e_crmove>: Likewise. * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands. include/ * opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro. gas/ * config/tc-ppc.c (md_assemble): Delete handling of fake operands. * testsuite/gas/ppc/common.s (crmove, cror, or., or, nor., nor): Add test of extended mnemonics. * testsuite/gas/ppc/common.d: Likewise. Don't match instruction offset. * testsuite/gas/ppc/spe.s (evor, evnor): Add test of extended mnemonics. * testsuite/gas/ppc/spe.d: Likewise. Don't match instruction offset.	8 years ago
Jim Wilson	7f99954970	RISC-V: Add RV32E support. Kito Cheng <kito.cheng@gmail.com> Monk Chiang <sh.chiang04@gmail.com> bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Handle EF_RISCV_RVE. binutils/ * readelf.c (get_machine_flags): Handle EF_RISCV_RVE. gas/ * config/tc-riscv.c (rve_abi): New. (riscv_set_options): Add rve field. Initialize it. (riscv_set_rve) New function. (riscv_set_arch): Support 'e' ISA subset. (reg_lookup_internal): If rve, check register is available. (riscv_set_abi): New parameter rve. (md_parse_option): Pass new argument to riscv_set_abi. (riscv_after_parse_args): Call riscv_set_rve. If rve_abi, set EF_RISCV_RVE. * doc/c-riscv.texi (-mabi): Document new ilp32e argument. include/ * elf/riscv.h (EF_RISCV_RVE): New define.	8 years ago
John Darrington	7b4ae82428	Add support for the Freescale s12z processor. bfd * Makefile.am: Add s12z files. * Makefile.in: Regenerate. * archures.c: Add bfd_s12z_arch. * bfd-in.h: Add exports of bfd_putb24 and bfd_putl24. * bfd-in2.h: Regenerate. * config.bfd: Add s12z target. * configure.ac: Add s12z target. * configure: Regenerate. * cpu-s12z.c: New file. * elf32-s12z.c: New file. * libbfd.c (bfd_putb24): New function. (bfd_putl24): New function. * libbfd.h: Regenerate. * reloc.c: Add s12z relocations. (bfd_get_reloc_size): Handle size 5 relocs. * targets.c: Add s12z_elf32_vec. opcodes * Makefile.am: Add support for s12z architecture. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * s12z-dis.c: New file. * s12z.h: New file. include * elf/s12z.h: New header. ld * Makefile.am: Add support for s12z architecture. * configure.tgt: Likewise. * Makefile.in: Regenerate. * emulparams/m9s12zelf.sh: New file. * scripttempl/elfm9s12z.sc: New file. * testsuite/ld-discard/static.d: Expect to fail for the s12z target. * testsuite/ld-elf/endsym.d: Likewise. * testsuite/ld-elf/merge.d: Likewise. * testsuite/ld-elf/pr14926.d: Skip for the s12z target. * testsuite/ld-elf/sec64k.exp: Likewise. * testsuite/ld-s12z: New directory. * testsuite/ld-s12z/opr-linking.d: New file. * testsuite/ld-s12z/opr-linking.s: New file. * testsuite/ld-s12z/relative-linking.d: New file. * testsuite/ld-s12z/relative-linking.s: New file. * testsuite/ld-s12z/z12s.exp: New file. gas * Makefile.am: Add support for s12z target. * Makefile.in: Regenerate. * NEWS: Mention the new support. * config/tc-s12z.c: New file. * config/tc-s12z.h: New file. * configure.tgt: Add s12z support. * doc/Makefile.am: Likewise. * doc/Makefile.in: Regenerate. * doc/all.texi: Add s12z documentation. * doc/as.textinfo: Likewise. * doc/c-s12z.texi: New file. * testsuite/gas/s12z: New directory. * testsuite/gas/s12z/abs.d: New file. * testsuite/gas/s12z/abs.s: New file. * testsuite/gas/s12z/adc-imm.d: New file. * testsuite/gas/s12z/adc-imm.s: New file. * testsuite/gas/s12z/adc-opr.d: New file. * testsuite/gas/s12z/adc-opr.s: New file. * testsuite/gas/s12z/add-imm.d: New file. * testsuite/gas/s12z/add-imm.s: New file. * testsuite/gas/s12z/add-opr.d: New file. * testsuite/gas/s12z/add-opr.s: New file. * testsuite/gas/s12z/and-imm.d: New file. * testsuite/gas/s12z/and-imm.s: New file. * testsuite/gas/s12z/and-opr.d: New file. * testsuite/gas/s12z/and-opr.s: New file. * testsuite/gas/s12z/and-or-cc.d: New file. * testsuite/gas/s12z/and-or-cc.s: New file. * testsuite/gas/s12z/bfext-special.d: New file. * testsuite/gas/s12z/bfext-special.s: New file. * testsuite/gas/s12z/bfext.d: New file. * testsuite/gas/s12z/bfext.s: New file. * testsuite/gas/s12z/bit-manip.d: New file. * testsuite/gas/s12z/bit-manip.s: New file. * testsuite/gas/s12z/bit.d: New file. * testsuite/gas/s12z/bit.s: New file. * testsuite/gas/s12z/bra-expression-defined.d: New file. * testsuite/gas/s12z/bra-expression-defined.s: New file. * testsuite/gas/s12z/bra-expression-undef.d: New file. * testsuite/gas/s12z/bra-expression-undef.s: New file. * testsuite/gas/s12z/bra.d: New file. * testsuite/gas/s12z/bra.s: New file. * testsuite/gas/s12z/brclr-symbols.d: New file. * testsuite/gas/s12z/brclr-symbols.s: New file. * testsuite/gas/s12z/brset-clr-opr-imm-rel.d: New file. * testsuite/gas/s12z/brset-clr-opr-imm-rel.s: New file. * testsuite/gas/s12z/brset-clr-opr-reg-rel.d: New file. * testsuite/gas/s12z/brset-clr-opr-reg-rel.s: New file. * testsuite/gas/s12z/brset-clr-reg-imm-rel.d: New file. * testsuite/gas/s12z/brset-clr-reg-imm-rel.s: New file. * testsuite/gas/s12z/brset-clr-reg-reg-rel.d: New file. * testsuite/gas/s12z/brset-clr-reg-reg-rel.s: New file. * testsuite/gas/s12z/clb.d: New file. * testsuite/gas/s12z/clb.s: New file. * testsuite/gas/s12z/clr-opr.d: New file. * testsuite/gas/s12z/clr-opr.s: New file. * testsuite/gas/s12z/clr.d: New file. * testsuite/gas/s12z/clr.s: New file. * testsuite/gas/s12z/cmp-imm.d: New file. * testsuite/gas/s12z/cmp-imm.s: New file. * testsuite/gas/s12z/cmp-opr-inc.d: New file. * testsuite/gas/s12z/cmp-opr-inc.s: New file. * testsuite/gas/s12z/cmp-opr-rdirect.d: New file. * testsuite/gas/s12z/cmp-opr-rdirect.s: New file. * testsuite/gas/s12z/cmp-opr-reg.d: New file. * testsuite/gas/s12z/cmp-opr-reg.s: New file. * testsuite/gas/s12z/cmp-opr-rindirect.d: New file. * testsuite/gas/s12z/cmp-opr-rindirect.s: New file. * testsuite/gas/s12z/cmp-opr-sxe4.d: New file. * testsuite/gas/s12z/cmp-opr-sxe4.s: New file. * testsuite/gas/s12z/cmp-opr-xys.d: New file. * testsuite/gas/s12z/cmp-opr-xys.s: New file. * testsuite/gas/s12z/cmp-s-imm.d: New file. * testsuite/gas/s12z/cmp-s-imm.s: New file. * testsuite/gas/s12z/cmp-s-opr.d: New file. * testsuite/gas/s12z/cmp-s-opr.s: New file. * testsuite/gas/s12z/cmp-xy.d: New file. * testsuite/gas/s12z/cmp-xy.s: New file. * testsuite/gas/s12z/com-opr.d: New file. * testsuite/gas/s12z/com-opr.s: New file. * testsuite/gas/s12z/complex-shifts.d: New file. * testsuite/gas/s12z/complex-shifts.s: New file. * testsuite/gas/s12z/db-tb-cc-opr.d: New file. * testsuite/gas/s12z/db-tb-cc-opr.s: New file. * testsuite/gas/s12z/db-tb-cc-reg.d: New file. * testsuite/gas/s12z/db-tb-cc-reg.s: New file. * testsuite/gas/s12z/dbCC.d: New file. * testsuite/gas/s12z/dbCC.s: New file. * testsuite/gas/s12z/dec-opr.d: New file. * testsuite/gas/s12z/dec-opr.s: New file. * testsuite/gas/s12z/dec.d: New file. * testsuite/gas/s12z/dec.s: New file. * testsuite/gas/s12z/div.d: New file. * testsuite/gas/s12z/div.s: New file. * testsuite/gas/s12z/eor.d: New file. * testsuite/gas/s12z/eor.s: New file. * testsuite/gas/s12z/exg.d: New file. * testsuite/gas/s12z/exg.s: New file. * testsuite/gas/s12z/ext24-ld-xy.d: New file. * testsuite/gas/s12z/ext24-ld-xy.s: New file. * testsuite/gas/s12z/inc-opr.d: New file. * testsuite/gas/s12z/inc-opr.s: New file. * testsuite/gas/s12z/inc.d: New file. * testsuite/gas/s12z/inc.s: New file. * testsuite/gas/s12z/inh.d: New file. * testsuite/gas/s12z/inh.s: New file. * testsuite/gas/s12z/jmp.d: New file. * testsuite/gas/s12z/jmp.s: New file. * testsuite/gas/s12z/jsr.d: New file. * testsuite/gas/s12z/jsr.s: New file. * testsuite/gas/s12z/ld-imm-page2.d: New file. * testsuite/gas/s12z/ld-imm-page2.s: New file. * testsuite/gas/s12z/ld-imm.d: New file. * testsuite/gas/s12z/ld-imm.s: New file. * testsuite/gas/s12z/ld-immu18.d: New file. * testsuite/gas/s12z/ld-immu18.s: New file. * testsuite/gas/s12z/ld-large-direct.d: New file. * testsuite/gas/s12z/ld-large-direct.s: New file. * testsuite/gas/s12z/ld-opr.d: New file. * testsuite/gas/s12z/ld-opr.s: New file. * testsuite/gas/s12z/ld-s-opr.d: New file. * testsuite/gas/s12z/ld-s-opr.s: New file. * testsuite/gas/s12z/ld-small-direct.d: New file. * testsuite/gas/s12z/ld-small-direct.s: New file. * testsuite/gas/s12z/lea-immu18.d: New file. * testsuite/gas/s12z/lea-immu18.s: New file. * testsuite/gas/s12z/lea.d: New file. * testsuite/gas/s12z/lea.s: New file. * testsuite/gas/s12z/mac.d: New file. * testsuite/gas/s12z/mac.s: New file. * testsuite/gas/s12z/min-max.d: New file. * testsuite/gas/s12z/min-max.s: New file. * testsuite/gas/s12z/mod.d: New file. * testsuite/gas/s12z/mod.s: New file. * testsuite/gas/s12z/mov.d: New file. * testsuite/gas/s12z/mov.s: New file. * testsuite/gas/s12z/mul-imm.d: New file. * testsuite/gas/s12z/mul-imm.s: New file. * testsuite/gas/s12z/mul-opr-opr.d: New file. * testsuite/gas/s12z/mul-opr-opr.s: New file. * testsuite/gas/s12z/mul-opr.d: New file. * testsuite/gas/s12z/mul-opr.s: New file. * testsuite/gas/s12z/mul-reg.d: New file. * testsuite/gas/s12z/mul-reg.s: New file. * testsuite/gas/s12z/mul.d: New file. * testsuite/gas/s12z/mul.s: New file. * testsuite/gas/s12z/neg-opr.d: New file. * testsuite/gas/s12z/neg-opr.s: New file. * testsuite/gas/s12z/not-so-simple-shifts.d: New file. * testsuite/gas/s12z/not-so-simple-shifts.s: New file. * testsuite/gas/s12z/opr-18u.d: New file. * testsuite/gas/s12z/opr-18u.s: New file. * testsuite/gas/s12z/opr-expr.d: New file. * testsuite/gas/s12z/opr-expr.s: New file. * testsuite/gas/s12z/opr-ext-18.d: New file. * testsuite/gas/s12z/opr-ext-18.s: New file. * testsuite/gas/s12z/opr-idx-24-reg.d: New file. * testsuite/gas/s12z/opr-idx-24-reg.s: New file. * testsuite/gas/s12z/opr-idx3-reg.d: New file. * testsuite/gas/s12z/opr-idx3-reg.s: New file. * testsuite/gas/s12z/opr-idx3-xysp-24.d: New file. * testsuite/gas/s12z/opr-idx3-xysp-24.s: New file. * testsuite/gas/s12z/opr-indirect-expr.d: New file. * testsuite/gas/s12z/opr-indirect-expr.s: New file. * testsuite/gas/s12z/opr-symbol.d: New file. * testsuite/gas/s12z/opr-symbol.s: New file. * testsuite/gas/s12z/or-imm.d: New file. * testsuite/gas/s12z/or-imm.s: New file. * testsuite/gas/s12z/or-opr.d: New file. * testsuite/gas/s12z/or-opr.s: New file. * testsuite/gas/s12z/p2-mul.d: New file. * testsuite/gas/s12z/p2-mul.s: New file. * testsuite/gas/s12z/page2-inh.d: New file. * testsuite/gas/s12z/page2-inh.s: New file. * testsuite/gas/s12z/psh-pul.d: New file. * testsuite/gas/s12z/psh-pul.s: New file. * testsuite/gas/s12z/qmul.d: New file. * testsuite/gas/s12z/qmul.s: New file. * testsuite/gas/s12z/rotate.d: New file. * testsuite/gas/s12z/rotate.s: New file. * testsuite/gas/s12z/s12z.exp: New file. * testsuite/gas/s12z/sat.d: New file. * testsuite/gas/s12z/sat.s: New file. * testsuite/gas/s12z/sbc-imm.d: New file. * testsuite/gas/s12z/sbc-imm.s: New file. * testsuite/gas/s12z/sbc-opr.d: New file. * testsuite/gas/s12z/sbc-opr.s: New file. * testsuite/gas/s12z/shift.d: New file. * testsuite/gas/s12z/shift.s: New file. * testsuite/gas/s12z/simple-shift.d: New file. * testsuite/gas/s12z/simple-shift.s: New file. * testsuite/gas/s12z/single-ops.d: New file. * testsuite/gas/s12z/single-ops.s: New file. * testsuite/gas/s12z/specd6.d: New file. * testsuite/gas/s12z/specd6.s: New file. * testsuite/gas/s12z/st-large-direct.d: New file. * testsuite/gas/s12z/st-large-direct.s: New file. * testsuite/gas/s12z/st-opr.d: New file. * testsuite/gas/s12z/st-opr.s: New file. * testsuite/gas/s12z/st-s-opr.d: New file. * testsuite/gas/s12z/st-s-opr.s: New file. * testsuite/gas/s12z/st-small-direct.d: New file. * testsuite/gas/s12z/st-small-direct.s: New file. * testsuite/gas/s12z/st-xy.d: New file. * testsuite/gas/s12z/st-xy.s: New file. * testsuite/gas/s12z/sub-imm.d: New file. * testsuite/gas/s12z/sub-imm.s: New file. * testsuite/gas/s12z/sub-opr.d: New file. * testsuite/gas/s12z/sub-opr.s: New file. * testsuite/gas/s12z/tfr.d: New file. * testsuite/gas/s12z/tfr.s: New file. * testsuite/gas/s12z/trap.d: New file. * testsuite/gas/s12z/trap.s: New file. binutils* readelf.c: Add support for s12z architecture. * testsuite/lib/binutils-common.exp (is_elf_format): Excluse s12z targets.	8 years ago
Tamar Christina	f9830ec165	Implement Read/Write constraints on system registers on AArch64 This patch adds constraints for read and write only system registers with the msr and mrs instructions. The code will treat having both flags set and none set as the same. These flags add constraints that must be matched up. e.g. a system register with a READ only flag set, can only be used with mrs. If The constraint fails a warning is emitted. Examples of the warnings generated: test.s: Assembler messages: test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3' test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0' test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3' and disassembly notes: 0000000000000000 <main>: 0: d5130503 msr dbgdtrtx_el0, x3 4: d5130503 msr dbgdtrtx_el0, x3 8: d5330503 mrs x3, dbgdtrrx_el0 c: d5330503 mrs x3, dbgdtrrx_el0 10: d5180003 msr midr_el1, x3 ; note: writing to a read-only register. Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during disassembly the constraints are use to disambiguate between the two. An exact constraint match is always prefered over partial ones if available. As always the warnings can be suppressed with -w and also be made errors using warnings as errors. binutils/ PR binutils/21446 * doc/binutils.texi (-M): Document AArch64 options. gas/ PR binutils/21446 * testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test. * testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise. * testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise. * testsuite/gas/aarch64/sysreg-diagnostic.s: New. * testsuite/gas/aarch64/sysreg-diagnostic.l: New. * testsuite/gas/aarch64/sysreg-diagnostic.d: New. include/ PR binutils/21446 * opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New. opcodes/ PR binutils/21446 * aarch64-asm.c (opintl.h): Include. (aarch64_ins_sysreg): Enforce read/write constraints. * aarch64-dis.c (aarch64_ext_sysreg): Likewise. * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here. (F_REG_READ, F_REG_WRITE): New. * aarch64-opc.c (aarch64_print_operand): Generate notes for AARCH64_OPND_SYSREG. (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h. (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0, mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1, id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1, id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1, id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1, mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1, id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1, id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1, id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1, csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2, rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0, mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1, mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1, pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0. * aarch64-tbl.h (aarch64_opcode_table): Add constraints to msr (F_SYS_WRITE), mrs (F_SYS_READ).	8 years ago
Tamar Christina	7d02540ab7	Allow non-fatal errors to be emitted and for disassembly notes be placed on AArch64 This patch adds a new platform option "notes" that can be used to indicate if disassembly notes should be placed in the disassembly as comments. These notes can contain information about a failing constraint such as reading from a write-only register. The disassembly will not be blocked because of this but -M notes will emit a comment saying that the operation is not allowed. For assembly this patch adds a new non-fatal status for errors. This is essentially a warning. The reason for not creating an actual warning type is that this causes the interaction between the ordering of warnings and errors to be problematic. Currently the error buffer is almost always filled because of the way operands are matched during assembly. An earlier template may have put an error there that would only be displayed if no other template matches or generates a higher priority error. But by definition a warning is lower priority than a warning, so the error (which is incorrect if another template matched) will supersede the warning. By treating warnings as errors and only later relaxing the severity this relationship keeps working and the existing reporting infrastructure can be re-used. binutils/ PR binutils/21446 * doc/binutils.texi (-M): Document AArch64 options. * NEWS: Document notes and warnings. gas/ PR binutils/21446 * config/tc-aarch64.c (print_operands): Indicate no notes. (output_operand_error_record): Support non-fatal errors. (output_operand_error_report, warn_unpredictable_ldst, md_assemble): Likewise. include/ PR binutils/21446 * opcode/aarch64.h (aarch64_operand_error): Add non_fatal. (aarch64_print_operand): Support notes. opcodes/ PR binutils/21446 * aarch64-dis.c (no_notes: New. (parse_aarch64_dis_option): Support notes. (aarch64_decode_insn, print_operands): Likewise. (print_aarch64_disassembler_options): Document notes. * aarch64-opc.c (aarch64_print_operand): Support notes.	8 years ago

1 2 3 4 5 ...

2322 Commits (af39b1c216ffb11e6ca8e8607b00749e0fc1ab41)