binutils-gdb

Commit Graph

Author	SHA1	Message	Date
H.J. Lu	a63027e547	Move entries in ChangeLog-9103 to appropriate */ChangeLog-9103.	21 years ago
H.J. Lu	faa7ef872d	Move entries to appropriate ChangeLog files.	21 years ago
Mark Kettenis	bc4bd9abb2	include/opcode/ChangeLog: * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and adjust them accordingly. gas/ChangeLog: * config/tc-i386.c (output_insn): Handle VIA PadLock instructions similar to other instructions now that they're marked as ImmExt.	21 years ago
Andreas Schwab	418a8fcaa2	Fix typo.	21 years ago
Jan Beulich	373ff435a8	include/opcode/ 2005-04-01 Jan Beulich <jbeulich@novell.com> * i386.h (i386_optab): Add rdtscp. opcodes/ 2005-04-01 Jan Beulich <jbeulich@novell.com> * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for easier future additions.	21 years ago
H.J. Lu	4cc91dba12	gas/testsuite/ 2005-03-29 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run segment and inval-seg for i386. Run x86-64-segment and x86-64-inval-seg for x86-64. * gas/i386/intel.d: Expect movw for moving between memory and segment register. * gas/i386/naked.d: Likewise. * gas/i386/opcode.d: Likewise. * gas/i386/x86-64-opcode.d: Likewise. * gas/i386/opcode.s: Use movw for moving between memory and segment register. * gas/i386/x86-64-opcode.s: Likewise. * : Likewise. * gas/i386/inval-seg.l: New. * gas/i386/inval-seg.s: New. * gas/i386/segment.l: New. * gas/i386/segment.s: New. * gas/i386/x86-64-inval-seg.l: New. * gas/i386/x86-64-inval-seg.s: New. * gas/i386/x86-64-segment.l: New. * gas/i386/x86-64-segment.s: New. include/opcode/ 2005-03-29 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Don't allow the `l' suffix for moving moving between memory and segment register. Allow movq for moving between general-purpose register and segment register. opcodes/ 2005-03-29 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (SEG_Fixup): New. (Sv): New. (dis386): Use "Sv" for 0x8c and 0x8e.	21 years ago
Jan Beulich	9ae09ff9cf	gas/testsuite/ 2005-02-09 Jan Beulich <jbeulich@novell.com> * gas/i386/intelok.s: Remove comments disabling alternative forms of fbld, fbstp, and fldcw. * gas/i386/intelok.d: Expect two instances of fbld, fbstp, and fldcw. include/opcode/ 2005-02-09 Jan Beulich <jbeulich@novell.com> PR gas/707 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and fnstsw.	21 years ago
Alexandre Oliva	90219bd0f3	bfd/ChangeLog: 2004-12-10 Alexandre Oliva <aoliva@redhat.com> * elf32-frv.c (elf32_frv_relocate_section): Force local binding for TLSMOFF. * reloc.c: Add R_FRV_TLSMOFF. * elf32-frv.c (elf32_frv_howto_table): Likewise. (frv_reloc_map, frv_reloc_type_lookup): Map it. (elf32_frv_relocate_section): Handle it. (elf32_frv_check_relocs): Likewise. * libbfd.h, bfd-in2.h: Rebuilt. 2004-11-26 Alexandre Oliva <aoliva@redhat.com> * elf32-frv.c (_frvfdpic_emit_got_relocs_plt_entries): Don't crash when given an undefweak TLS symbol. Fix constant TLS PLT entries such that they return the constant in gr9. (_frvfdpic_relax_tls_entries): Don't crash for undefweak TLS symbols. (_frvfdpic_size_got_plt): Set _cooked_size of dynamic sections. too, such that they shrink on relaxation. (elf32_frvfdpic_finish_dynamic_sections): Check __ROFIXUP_END__ as marking the position right past the _GLOBAL_OFFSET_TABLE_ value. (_frvfdpic_assign_plt_entries): Shrink constant TLS PLT entries if we can guarantee the use of 16-bit constants. 2004-11-10 Alexandre Oliva <aoliva@redhat.com> Introduce TLS support for FR-V FDPIC. * reloc.c: Add TLS relocations. * elf32-frv.c (elf32_frv_howto_table): Add TLS relocations. (elf32_frv_rel_tlsdesc_value_howto): New. (elf32_frv_rel_tlsoff_howto): New. (frv_reloc_map): Add new mappings. (struct frvfdpic_elf_link_hash_table): Add pointer to summary reloc information. (frvfdpic_dynamic_got_plt_info): New. (frvfdpic_plt_tls_ret_offset): New. (ELF_DYNAMIC_INTERPRETER, DEFAULT_STACK_SIZE): Move earlier. (struct _frvfdpic_dynamic_got_info): Likewise. Add TLS members. (struct _frvfdpic_dynamic_got_plt_info): Likewise. (FRVFDPIC_SYM_LOCAL): Regard symbols defined in the absolute section as local. (struct frvfdpic_relocs_info): Add TLS fields. (frvfdpic_relocs_info_hash): Warning clean up. (frvfdpic_relocs_info_find): Initialize tlsplt_entry. (frvfdpic_pic_merge_early_relocs_info): Merge TLS fields. (FRVFDPIC_TLS_BIAS): Define. (tls_biased_base): New. (_frvfdpic_emit_got_relocs_plt_entries): Deal with TLS relocations. (frv_reloc_type_lookup): Likewise. (frvfdpic_info_to_howto_rel): Likewise. (elf32_frv_relocate_section): Likewise. (_frv_create_got_section): Create the PLT section here. (elf32_frvfdpic_create_dynamic_sections): Not here. (_frvfdpic_count_nontls_entries): Move out of... (_frvfdpic_count_got_plt_entries): ... here. (_frvfdpic_count_tls_entries): Likewise. Add TLS support. (_frvfdpic_count_relocs_fixups): Likewise. Add relaxation support. (_frvfdpic_relax_tls_entries): New. (_frvfdpic_compute_got_alloc_data): Add TLS support. (_frvfdpic_get_tlsdesc_entry): New. (_frvfdpic_assign_got_entries): Add TLS support. (_frvfdpic_assign_plt_entries): Likewise. (_frvfdpic_reset_got_plt_entries): New. (_frvfdpic_size_got_plt): Move out of... (elf32_frvfdpic_size_dynamic_sections): ... here. (_frvfdpic_relax_got_plt_entries): New. (elf32_frvfdpic_relax_section): New. (elf32_frvfdpic_finish_dynamic_sections): Add TLS sanity check. (elf32_frv_check_relocs): Add TLS support. (bfd_elf32_bfd_relax_section): Define for FDPIC. * libbfd.h, bfd-in2.h: Rebuilt. cpu/ChangeLog: 2004-11-10 Alexandre Oliva <aoliva@redhat.com> * frv.cpu: Add support for TLS annotations in loads and calll. * frv.opc (parse_symbolic_address): New. (parse_ldd_annotation): New. (parse_call_annotation): New. (parse_ld_annotation): New. (parse_ulo16, parse_uslo16): Use parse_symbolic_address. Introduce TLS relocations. (parse_d12, parse_s12, parse_u12): Likewise. (parse_uhi16): Likewise. Fix constant checking on 64-bit host. (parse_call_label, print_at): New. gas/ChangeLog: * config/tc-frv.c (md_apply_fix3): Mark TLS symbols as such. 2004-12-10 Alexandre Oliva <aoliva@redhat.com> * config/tc-frv.c (frv_pic_ptr): Add tlsmoff support. 2004-11-10 Alexandre Oliva <aoliva@redhat.com> * cgen.c (gas_cgen_parse_operand): Handle CGEN_PARSE_OPERAND_SYMBOLIC. * config/tc-frv.c (md_cgen_lookup_reloc): Handle TLS relocations. (frv_force_relocation): Likewise. Fix handling of PIC relocations. (md_apply_fix3): Likewise. include/elf/ChangeLog: 2004-12-10 Alexandre Oliva <aoliva@redhat.com> * frv.h: Add R_FRV_TLSMOFF. 2004-11-10 Alexandre Oliva <aoliva@redhat.com> * frv.h: Add TLS relocations. include/opcode/ChangeLog: 2004-11-10 Alexandre Oliva <aoliva@redhat.com> * cgen.h (enum cgen_parse_operand_type): Add CGEN_PARSE_OPERAND_SYMBOLIC. ld/testsuite/ChangeLog: * ld-frv/fdpic.exp: Add -mfdpic to ASFLAGS. * ld-frv/tls.exp: Likewise. 2004-11-26 Alexandre Oliva <aoliva@redhat.com> * ld-frv/tls-3.s: New. * ld-frv/tls-static-3.d: New. * ld-frv/tls-dynamic-3.d: New. * ld-frv/tls-pie-3.d: New. * ld-frv/tls-shared-3.d: New. * ld-frv/tls-relax-static-3.d: New. * ld-frv/tls-relax-dynamic-3.d: New. * ld-frv/tls-relax-pie-3.d: New. * ld-frv/tls-relax-shared-3.d: New. * ld-frv/tls.exp: Run the new tests. * ld-frv/tls-dynamic-2.d: Adjust for improved relaxation. * ld-frv/tls-relax-dynamic-2.d: Likewise. * ld-frv/tls-relax-initial-shared-2.d: Likewise. 2004-11-10 Alexandre Oliva <aoliva@redhat.com> * ld-frv/tls-1-dep.s: New. * ld-frv/tls-1-shared.lds: New. * ld-frv/tls-1.s: New. * ld-frv/tls-2.s: New. * ld-frv/tls-dynamic-1.d: New. * ld-frv/tls-dynamic-2.d: New. * ld-frv/tls-initial-shared-2.d: New. * ld-frv/tls-pie-1.d: New. * ld-frv/tls-relax-dynamic-1.d: New. * ld-frv/tls-relax-dynamic-2.d: New. * ld-frv/tls-relax-initial-shared-2.d: New. * ld-frv/tls-relax-pie-1.d: New. * ld-frv/tls-relax-shared-1.d: New. * ld-frv/tls-relax-shared-2.d: New. * ld-frv/tls-relax-static-1.d: New. * ld-frv/tls-shared-1-fail.d: New. * ld-frv/tls-shared-1.d: New. * ld-frv/tls-shared-2.d: New. * ld-frv/tls-static-1.d: New. * ld-frv/tls.exp: New. * ld-frv/fdpic-pie-1.d: Adjust for 64-bit host. * ld-frv/fdpic-pie-2.d: Likewise. * ld-frv/fdpic-pie-6.d: Likewise. * ld-frv/fdpic-pie-7.d: Likewise. * ld-frv/fdpic-pie-8.d: Likewise. * ld-frv/fdpic-shared-1.d: Likewise. * ld-frv/fdpic-shared-2.d: Likewise. * ld-frv/fdpic-shared-3.d: Likewise. * ld-frv/fdpic-shared-4.d: Likewise. * ld-frv/fdpic-shared-5.d: Likewise. * ld-frv/fdpic-shared-6.d: Likewise. * ld-frv/fdpic-shared-7.d: Likewise. * ld-frv/fdpic-shared-8.d: Likewise. * ld-frv/fdpic-shared-local-2.d: Likewise. * ld-frv/fdpic-shared-local-8.d: Likewise. * ld-frv/fdpic-static-1.d: Likewise. * ld-frv/fdpic-static-2.d: Likewise. * ld-frv/fdpic-static-6.d: Likewise. * ld-frv/fdpic-static-7.d: Likewise. * ld-frv/fdpic-static-8.d: Likewise. opcodes/ChangeLog: 2004-11-10 Alexandre Oliva <aoliva@redhat.com> * frv-asm.c: Rebuilt. * frv-desc.c: Rebuilt. * frv-desc.h: Rebuilt. * frv-dis.c: Rebuilt. * frv-ibld.c: Rebuilt. * frv-opc.c: Rebuilt. * frv-opc.h: Rebuilt.	22 years ago
Fred Fish	239cb185bc	2005-01-21 Fred Fish <fnf@specifixinc.com> * mips.h: Change INSN_ALIAS to INSN2_ALIAS. Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.	22 years ago
Fred Fish	dc9a9f39cc	2005-01-19 Fred Fish <fnf@specifixinc.com> * mips.h (struct mips_opcode): Add new pinfo2 member. (INSN_ALIAS): New define for opcode table entries that are specific instances of another entry, such as 'move' for an 'or' with a zero operand. (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.	22 years ago
Ian Lance Taylor	98e7aba8e2	* mips.h (CPU_RM9000): Define. (OPCODE_IS_MEMBER): Handle CPU_RM9000.	22 years ago
Jan Beulich	37edbb65ad	gas/ 2004-11-25 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (optimize_imm): Adjust immediates to only those permissible for the selected instruction suffix. (process_suffix): For DefaultSize instructions, suppressing the guessing of a 'q' suffix if the instruction doesn't support it is pointless, because only an 'l' suffix can be guessed in this place. gas/testsuite/ 2004-11-25 Jan Beulich <jbeulich@novell.com> * gas/i386/x86-64-inval.[sl]: Remove sahf/lahf. include/opcode/ 2004-11-25 Jan Beulich <jbeulich@novell.com> * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves to/from test registers are illegal in 64-bit mode. Add missing NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix (previously one had to explicitly encode a rex64 prefix). Re-enable lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings support it there. Add cmpxchg16b as per Intel's 64-bit documentation.	22 years ago
Jan Beulich	5c6af06e4c	gas/ 2004-11-23 Jan Beulich <jbeulich@novell.com> * config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to indicate the MMX extensions added by both SSE and 3DNow!A. (Cpu3dnowA): Declare. (CpuUnknownFlags): Update. * config/tc-i386.c (cpu_sub_arch_name): Declare. (cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies 3DNow!. Athlon additionally implies 3DNow!A. Several new entries (those starting with a dot are for sub-arch specification). (set_cpu_arch): Handle sub-arch specifications. (parse_insn): Distinguish between instructions not supported because of insufficient CPU features and because of 64-bit mode. * doc/c-i386.texi: Describe enhanced .arch directive. include/opcode/ 2004-11-23 Jan Beulich <jbeulich@novell.com> * i386.h (i386_optab): paddq and psubq, even in their MMX form, are available only with SSE2. Change the MMX additions introduced by SSE and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A instructions by their now designated identifier (since combining i686 and 3DNow! does not really imply 3DNow!A).	22 years ago
Alan Modra	f5c7edf4d6	include/opcode/ * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. gas/ * config/tc-msp430.c (struct rcodes_s, MSP430_RLC, msp430_rcodes, struct hcodes_s, msp430_hcodes): From include/opcode/msp430.h.	22 years ago
Nick Clifton	7499d566bb	Add support fpr MAXQ processor	22 years ago
H.J. Lu	bcb9eebe75	2004-11-05 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Put back "movzb".	22 years ago
Hans-Peter Nilsson	94bb3d3867	* cris.h (enum cris_insn_version_usage): Tweak formatting and comments. Remove member cris_ver_sim. Add members cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. (struct cris_support_reg, struct cris_cond15): New types. (cris_conds15): Declare. (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. (NOP_Z_BITS): Define in terms of NOP_OPCODE. (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and SIZE_FIELD_UNSIGNED.	22 years ago
Jan Beulich	9306ca4a20	gas/ 2004-11-04 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (set_intel_syntax): Allow % in symbol names when intel syntax and no register prefix, allow $ in symbol names when intel syntax. (set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX. (intel_float_operand): Add fourth return value indicating math control operations. Make classification more precise. (md_assemble): Complain if memory operand of mov[sz]x has no size specified. (parse_insn): Translate word operands to floating point instructions operating on integers as well as control instructions to short ones as expected by AT&T syntax. Translate 'd' suffix to short one only for floating point instructions operating on non-integer operands. (match_template): Remove fldcw special case. Adjust q-suffix handling to permit it on fild/fistp/fisttp in AT&T mode. (process_suffix): Don't guess DefaultSize insns' suffix from stackop_size for certain floating point control instructions. Guess suffix for branch and [ls][gi]dt based on flag_code. Split error messages for Intel and AT&T syntax, and make the condition more strict for the former. Adjust suppressing of generation of operand size overrides. (intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE, OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add more error checking. * config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines. gas/testsuite/ 2004-11-04 Jan Beulich <jbeulich@novell.com> * gas/i386/i386.exp: Execute new tests intelbad and intelok. * gas/i386/intelbad.[sl]: New test to check for various things not permitted in Intel mode. * gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d: Adjust for change to segment register store. * gas/i386/intelok.[sd]: New test to check various Intel mode specific things get handled correctly. * gas/i386/x86_64.[sd]: Remove unsupported constructs referring to 'high' and 'low' parts of an operand, which the parser previously accepted while neither telling that it's not supported nor that it ignored the remainder of the line following these supposed keywords. include/opcode/ 2004-11-04 Jan Beulich <jbeulich@novell.com> * i386.h (sldx_Suf): Remove. (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. (q_FP): Define, implying no REX64. (x_FP, sl_FP): Imply FloatMF. (i386_optab): Split reg and mem forms of moving from segment registers so that the memory forms can ignore the 16-/32-bit operand size distinction. Adjust a few others for Intel mode. Remove FP uses from all non-floating-point instructions. Unite 32- and 64-bit forms of movsx, movzx, and movd. Adjust floating point operations for the above changes to the FP macros. Add DefaultSize to floating point control insns operating on larger memory ranges. Remove left over comments hinting at certain insns being Intel-syntax ones where the ones actually meant are already gone. opcodes/ 2004-11-04 Jan Beulich <jbeulich@novell.com> * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define. (indirEb): Remove. (Mp): Use f_mode rather than none at all. (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode replaces what previously was x_mode; x_mode now means 128-bit SSE operands. (dis386): Make far jumps and calls have an 'l' prefix only in AT&T mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq. pinsrw's second operand is Edqw. (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt, fldenv, frstor, fsave, fstenv all should also have suffixes in Intel mode when an operand size override is present or always suffixing. More instructions will need to be added to this group. (putop): Handle new macro chars 'C' (short/long suffix selector), 'I' (Intel mode override for following macro char), and 'J' (for adding the 'l' prefix to far branches in AT&T mode). When an alternative was specified in the template, honor macro character when specified for Intel mode. (OP_E): Handle new _mode values. Correct pointer specifications for memory operands. Consolidate output of index register. (OP_G): Handle new _mode values. (OP_I): Handle const_1_mode. (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate respective opcode prefix bits have been consumed. (OP_EM, OP_EX): Provide some default handling for generating pointer specifications.	22 years ago
Nick Clifton	48c9f030c9	Add support for CRX co-processor opcodes	22 years ago
Nick Clifton	0dd132b63c	Apply Paul Brook's patch to implement armv6k instructions	22 years ago
Marek Michalkiewicz	23794b24aa	* gas/config/tc-avr.c: Add support for	22 years ago
Alan Modra	2a309db040	opcodes/ * ppc-opc.c (L): Make this field not optional. include/opcode/ * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.	22 years ago
Nick Clifton	b18c562e39	Apply Dmitry Diky's patches to add relaxation to msp430.	22 years ago
Nick Clifton	45d313cd66	O_JSR): Do not allow VECIND addressing for non-SX processors.	22 years ago
Michal Ludvig	30d1c83669	Added new instructions for next version of VIA PadLock core.	22 years ago
H.J. Lu	9a45f1c2c4	2004-07-22 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.	22 years ago
Nick Clifton	543613e933	For DefaultSize instructions, don't guess a 'q' suffix if the instruction doesn't support it.	22 years ago
Richard Earnshaw	b781e55836	* arm.h: Remove all old content. Replace with architecture defines from gas/config/tc-arm.c.	22 years ago
Andreas Schwab	8577e690b5	binutils/testsuite/: * binutils-all/m68k/movem.s: New file. * binutils-all/m68k/objdump.exp: New file. include/opcode/: * m68k.h: Fix comment. opcodes/: * m68k-dis.c (m68k_valid_ea): Check validity of all codes.	22 years ago
Nick Clifton	1fe1f39c06	Add new port: crx-elf	22 years ago
Alan Modra	1d9f512f33	include/opcode/ * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. opcodes/ * i386-dis.c (x_mode): Comment. (two_source_ops): File scope. (float_mem): Correct fisttpll and fistpll. (float_mem_mode): New table. (dofloat): Use it. (OP_E): Correct intel mode PTR output. (ptr_reg): Use open_char and close_char. (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for operands. Set two_source_ops. gas/testsuite/ * gas/i386/prescott.s: Remove fisttpd and fisttpq. * gas/i386/prescott.d: Update.	22 years ago
Nick Clifton	be8c092bb0	Reorganise m68k instruction decoding and improve handling of MAC/EMAC	22 years ago
Nick Clifton	6b6e92f432	Add support for 521x,5249,547x,548x.	22 years ago
Nick Clifton	fd99574ba5	Add support for ColdFire MAC instructions and tidy up support for other m68k variants.	22 years ago
H.J. Lu	3922a64ca2	Reorder it.	22 years ago
H.J. Lu	83afed5481	Correct the ChangeLog entry.	22 years ago
Alan Modra	fdd12ef3c6	opcodes/ * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle PPC_OPERANDS_GPR_0. * ppc-opc.c (RA0): Define. (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0. (RAOPT): Rename from RAO. Update all uses. (powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi", "stsdx", "stsdi", "lmd" and "stmd" insns. include/opcode/ * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. gas/testsuite/ Update gas/ppc/. ld/testsuite/ Update ld-powerpc/.	22 years ago
Michal Ludvig	1f45d98889	2004-03-12 Michal Ludvig <mludvig@suse.cz> * i386.h (i386_optab): Added xstore as an alias for xstorerng.	22 years ago
Michal Ludvig	0f10071e3d	2004-03-12 Michal Ludvig <mludvig@suse.cz> * gas/config/tc-i386.c (output_insn): Handle PadLock instructions. * gas/config/tc-i386.h (CpuPadLock): New define. (CpuUnknownFlags): Added CpuPadLock. * include/opcode/i386.h (i386_optab): Added xstore/xcrypt insns. * opcodes/i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines. (dis386_twobyte): Opcode 0xa7 is PADLOCK_0. (padlock_table): New struct with PadLock instructions. (print_insn): Handle PADLOCK_SPECIAL.	22 years ago
Nick Clifton	3255318a04	Add support for relaxing the 32bit ldc/stc instructions.	23 years ago
Nick Clifton	ca9a79a174	Add support for relaxation of bit manipulation instructions.	23 years ago
Nick Clifton	875a0b1471	(BITOP): Dissallow operations on @aa:16 and @aa:32 except for the H8S.	23 years ago
Alan Modra	c9e214e571	Split ChangeLog files.	23 years ago
Nick Clifton	3e60263266	Add ColfFire v4 support	23 years ago
Hans-Peter Nilsson	906e88d4fb	* mmix.h (JMP_INSN_BYTE): Define.	23 years ago
Chris Demetriou	5f74bc130d	[ bfd/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * archures.c (bfd_mach_mipsisa64r2): New define. * bfd-in2.h: Regenerate. * aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2. * cpu-mips.c (I_mipsisa64r2): New enum value. (arch_info_struct): Add entry for I_mipsisa64r2. * elfxx-mips.c (_bfd_elf_mips_mach) (_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2. (mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case. (mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2. [ binutils/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2. [ gas/Changelog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2): New CPUs. configure: Regenerate. * config/tc-mips.c (imm2_expr): New variable. (md_assemble, mips16_ip): Initialize imm2_expr. (ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2. (macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands. (macro): Handle M_DEXT and M_DINS. (validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands. (mips_ip): Likewise. (OPTION_MIPS64R2): New define. (md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2). OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2. (md_parse_option): Handle OPTION_MIPS64R2. (s_mipsset): Handle setting "mips64r2" ISA. (mips_cpu_info_table): Add mips64r2. (md_show_usage): Document -mips64r2 option. * doc/as.texinfo: Docuemnt -mips64r2 option. * doc/c-mips.texi: Likewise. [ gas/testsuite/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * gas/mips/cp0-names-mips64r2.d: New file. * gas/mips/cp0sel-names-mips64r2.d: New file. * gas/mips/elf_arch_mips64r2.d: New file. * gas/mips/hwr-names-mips64r2.d: New file. * gas/mips/mips32r2-ill-fp64.l: New file. * gas/mips/mips32r2-ill-fp64.s: New file. * gas/mips/mips64r2-ill.l: New file. * gas/mips/mips64r2-ill.s: New file. * gas/mips/mips64r2.d: New file. * gas/mips/mips64r2.s: New file. * gas/mips/mips.exp: Define "mips64r2" arch, and run new tests. [ include/elf/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * mips.h (E_MIPS_ARCH_64R2): New define. [ include/opcode/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * mips.h: Document +E, +F, +G, +H, and +I operand types. Update documentation of I, +B and +C operand types. (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines. (M_DEXT, M_DINS): New enum values. [ ld/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * ldmain.c (get_emulation): Ignore "-mips64r2". [ ld/testsuite/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * ld-mips-elf/mips-elf-flags.exp: Add tests for combinations with MIPS64r2. [ opcodes/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * mips-dis.c (mips_arch_choices): Add entry for "mips64r2" (print_insn_args): Add handing for +E, +F, +G, and +H. * mips-opc.c (I65): New define for MIPS64r2. (mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins", "dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh", and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to be supported on MIPS64r2.	23 years ago
Nick Clifton	8ad30312ff	Add binutils support for v850e1 processor	23 years ago
Alan Modra	68d23d2157	* ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other PPC_OPCODE_* defines.	23 years ago
Jason Eckhardt	be6389fdef	include/opcode/ChangeLog: 2003-08-16 Jason Eckhardt <jle@rice.edu> * i860.h (fmov.ds): Expand as famov.ds. (fmov.sd): Expand as famov.sd. (pfmov.ds): Expand as pfamov.ds. gas/testsuite/ChangeLog: 2003-08-16 Jason Eckhardt <jle@rice.edu> * gas/i860/pseudo-ops01.{s,d}: New files. * gas/i860/i860.exp: Execute the new test above. * gas/i860/README.i860: Mention that pseudo-ops need more testing and remove the align fill defect from the list.	23 years ago
Michael Meissner	10e05405ac	Convert cgen to C-90	23 years ago

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271 Commits (a63027e547181bee6b09e1c4441df4934e38edcd)