binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Alan Modra	d87bef3a7b	Update year range in copyright notice of binutils files The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.	3 years ago
Peter Bergner	79e24d0a6c	PowerPC: Add support for RFC02653 - Dense Math Facility gas/ * config/tc-ppc.c (pre_defined_registers): Add dense math registers. (md_assemble): Check dmr specified in correct operand. * testsuite/gas/ppc/outerprod.s <dmsetaccz, dmxvbf16ger2, dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp, dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp, dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp, dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp, dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8, dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxmfacc, dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp, pmdmxvi8ger4spp>: Add new tests. * testsuite/gas/ppc/outerprod.d: Likewise. * testsuite/gas/ppc/rfc02653.s: New test. * testsuite/gas/ppc/rfc02653.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. include/ * opcode/ppc.h (PPC_OPERAND_DMR): Define. Renumber following PPC_OPERAND defines. opcodes/ * ppc-dis.c (print_insn_powerpc): Prepend 'dm' when printing DMR regs. * ppc-opc.c (insert_p2, (extract_p2, (insert_xa5, (extract_xa5, insert_xb5, (extract_xb5): New functions. (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): Disallow operand overlap only on Power10. (DMR, DMRAB, P1, P2, XA5p, XB5p, XDMR_MASK, XDMRDMR_MASK, XX2ACC_MASK, XX2DMR_MASK, XX3DMR_MASK): New defines. (powerpc_opcodes): Add dmmr, dmsetaccz, dmsetdmrz, dmxor, dmxvbf16ger2, dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp, dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp, dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp, dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp, dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8, dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxextfdmr256, dmxxextfdmr512, dmxxinstdmr256, dmxxinstdmr512, dmxxmfacc, dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp, pmdmxvi8ger4spp.	4 years ago
Alan Modra	61a457e5da	e200 LSP support It has bothered me for a long time that we have disabled LSP (and SPE) tests. Also the LSP test comment indicating there is something wrong with get_powerpc_dialect. I don't think there is. Decoding of a VLE instruction depends on whether the processor is in VLE mode (some processors support both VLE and standard PPC) which we flag per section with SHF_PPC_VLE for decoding when disassembling. Background: Some versions of powerpc e200 have "Lightweight Signal Processing" support, examples being e200z215 and e200z425. As far as I can tell, LSP and SPE are mutually exclusive. This seems to be borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw" have the same encoding. So none of the processor descriptions in ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we want disassembly to work. I also could not find anything to suggest that the LSP insns are enabled only in VLE mode, which means the LSP insns should not be in vle_opcodes. Fix all this by moving the LSP insns to their own table, and add a new e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from -mvle. (Yes, I know, as I said above some of the e200z4 processors have LSP. Others have SPE. It's hard to choose good options. Think of z2 as meaning earlier, z4 as later.) Also add -mlsp to allow adding the LSP insn set. include/ * opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare. (LSP_OP_TO_SEG): Define. binutils/ * doc/binutils.texi: Update ppc docs. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash. * doc/c-ppc.texi: Document e200 and lsp. * testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2. * testsuite/gas/ppc/lsp.d: Likewise, disassembly too. * testsuite/gas/ppc/ppc.exp: Don't xfail lsp test. opcodes/ * ppc-dis.c (ppc_opts): Add e200z2 and lsp. Don't set PPC_OPCODE_LSP for e200z4 or vle. (ppc_parse_cpu): Mutually exclude LSP and SPE. (LSP_OPCD_SEGS): Define. (lsp_opcd_indices): New array. (disassemble_init_powerpc): Init lsp_opcd_indices. (lookup_lsp): New function. (print_insn_powerpc): Call it. * ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout. (vle_opcodes): Move LSP opcodes to.. (lsp_opcodes): ..here, and sort. (lsp_num_opcodes): New.	4 years ago
Peter Bergner	29a6701e53	ppc: Document the -mfuture and -Mfuture options and make them usable The -mfuture and -Mfuture options which are used for adding potential new ISA instructions were not documented. They also lacked a bitmask so new instructions could not be enabled by those options. Fixed. binutils/ * doc/binutils.texi: Document -Mfuture. gas/ * config/tc-ppc.c: Document -mfuture * doc/c-ppc.texi: Likewise. include/ * opcode/ppc.h (PPC_OPCODE_FUTURE): Define. opcodes/ * ppc-dis.c (ppc_opts) <future>: Use it. * ppc-opc.c (FUTURE): Define.	4 years ago
Dmitry Selyutin	59f08271dd	ppc/svp64: introduce non-zero operand flag svstep and svshape instructions subtract 1 before encoding some of the operands. Obviously zero is not supported for these operands. Whilst PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be incremented, there is no flag which marks the fact that zero values are not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this purpose.	4 years ago
Dmitry Selyutin	33ae8a3ae3	ppc/svp64: support LibreSOC architecture This patch adds support for LibreSOC machine and SVP64 extension flag for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit Prefixed instruction format implementing SV. Funded by NLnet through EU Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly submitted via the OpenPOWER Foundation ISA Working Group via the newly-created External RFC Process. For more details, visit https://libre-soc.org.	4 years ago
Dmitry Selyutin	8e5eb8e1b0	ppc: extend opindex to 16 bits With the upcoming SVP64 extension[0] to PowerPC architecture, it became evident that PowerPC operand indices no longer fit 8 bits. This patch switches the underlying type to uint16_t, also introducing a special typedef so that any future extension goes even smoother. [0] https://libre-soc.org include/ * opcode/ppc.h (ppc_opindex_t): New typedef. (struct powerpc_opcode): Use it. (PPC_OPINDEX_MAX): Define. gas/ * write.h (struct fix): Increase size of fx_pcrel_adjust. Reorganise. * config/tc-ppc.c (insn_validate): Use ppc_opindex_t for operands. (md_assemble): Likewise. (md_apply_fix): Likewise. Mask fx_pcrel_adjust with PPC_OPINDEX_MAX. (ppc_setup_opcodes): Adjust opcode index assertion. opcodes/ * ppc-dis.c (skip_optional_operands): Use ppc_opindex_t for operand pointer. (lookup_powerpc, lookup_prefix, lookup_vle, lookup_spe2): Likewise. (print_insn_powerpc): Likewise.	4 years ago
Alan Modra	dc3ff92676	Delete PowerPC macro insn support Let's hope this stays dead, but it's here as a patch separate from those that removed use of powerpc_macros just in case it needs to be resurrected. include/ * opcode/ppc.h (struct powerpc_macro): Delete declaration. (powerpc_macros, powerpc_num_macros): Likewise.. opcodes/ * ppc-opc.c (powerpc_macros, powerpc_num_macros): Delete. gas/ * config/tc-ppc.c (ppc_macro): Delete function. (ppc_macro_hash): Delete. (ppc_setup_opcodes, md_assemble): Delete macro support.	4 years ago
Alan Modra	42952a9605	PowerPC64 extended instructions in powerpc_macros The extended instructions implemented in powerpc_macros aren't used by the disassembler. That means instructions like "sldi r3,r3,2" appear in disassembly as "rldicr r3,r3,2,61", which is annoying since many other extended instructions are shown. Note that some of the instructions moved out of the macro table to the opcode table won't appear in disassembly, because they are aliases rather than a subset of the underlying raw instruction. If enabled, rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many occurrences in the case of clrlsldi if n <= b was added to the extract functions.) The patch also fixes a small bug in opcode sanity checking. include/ * opcode/ppc.h (PPC_OPSHIFT_SH6): Define. opcodes/ * ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn), (insert_crdn, extract_crdn, insert_rrdn, extract_rrdn), (insert_sldn, extract_sldn, insert_srdn, extract_srdn), (insert_erdb, extract_erdb, insert_csldn, extract_csldb), (insert_irdb, extract_irdn): New functions. (ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb): Define and add associated powerpc_operands entries. (powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi", "sldi", "extldi", "clrlsldi", "insrdi" and corresponding record (ie. dot suffix) forms. (powerpc_macros): Delete same from here. gas/ * config/tc-ppc.c (insn_validate): Don't modify value passed to operand->insert for PPC_OPERAND_PLUS1 when calculating mask. Handle PPC_OPSHIFT_SH6. * testsuite/gas/ppc/prefix-reloc.d: Update. * testsuite/gas/ppc/simpshft.d: Update. ld/ * testsuite/ld-powerpc/elfv2so.d: Update. * testsuite/ld-powerpc/notoc.d: Update. * testsuite/ld-powerpc/notoc3.d: Update. * testsuite/ld-powerpc/tlsdesc2.d: Update. * testsuite/ld-powerpc/tlsget.d: Update. * testsuite/ld-powerpc/tlsget2.d: Update. * testsuite/ld-powerpc/tlsopt5.d: Update. * testsuite/ld-powerpc/tlsopt6.d: Update.	4 years ago
Alan Modra	a2c5833233	Update year range in copyright notice of binutils files The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out /po/.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.	4 years ago
Alan Modra	3dfb1b6d34	Remove bfd_stdint.h If we require C99 for binutils then stdint.h is available. bfd/ * .gitignore: Delete bfd_stdint.h entry. * Makefile.am (bfdinclude_HEADERS): Delete bfd_stdint.h. (BUILD_HFILES, LOCAL_H_DEPS): Likewise. * bfd-in.h: Include stdint.h in place of bfd_stdint.h. * configure.ac: Don't invoke GCC_HEADER_STDINT. * configure.com: Don't create bfd_stdint.h. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in2.h: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. binutils/ * coffdump.c: Include stdint.h in place of bfd_stdint.h. * dwarf.c: Likewise. gas/ * config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h. * config/tc-crx.c: Likewise. * config/tc-nds32.h: Likewise. include/ * cgen/basic-modes.h: Include stdint.h in place of bfd_stdint.h. * elf/nfp.h: Likewise. * opcode/aarch64.h: Likewise. * opcode/cgen.h: Likewise. * opcode/nfp.h: Likewise. * opcode/ppc.h: Likewise. ld/ * elf-hints-local.h: Include stdint.h in place of bfd_stdint.h. * emultempl/nds32elf.em: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise. * testsuite/ld-elf/pr18718.c: Likewise. * testsuite/ld-elf/pr18720a.c: Likewise. * testsuite/ld-elf/pr25749-1.c: Likewise. * testsuite/ld-elf/pr25749-1a.c: Likewise. * testsuite/ld-elf/pr25749-1b.c: Likewise. * testsuite/ld-elf/pr25749-1c.c: Likewise. * testsuite/ld-elf/pr25749-1d.c: Likewise. * testsuite/ld-elf/pr25749-2.c: Likewise. * testsuite/ld-elf/pr25754-1a.c: Likewise. * testsuite/ld-elf/pr25754-2a.c: Likewise. * testsuite/ld-elf/pr25754-3a.c: Likewise. * testsuite/ld-elf/pr25754-4a.c: Likewise. * testsuite/ld-elf/pr25754-5a.c: Likewise. * testsuite/ld-elf/pr25754-6a.c: Likewise. opcodes/ * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h. * aarch64-dis.h: Likewise. * aarch64-opc.c: Likewise. * avr-dis.c: Likewise. * csky-dis.c: Likewise. * nds32-asm.c: Likewise. * nds32-dis.c: Likewise. * nfp-dis.c: Likewise. * riscv-dis.c: Likewise. * s12z-dis.c: Likewise. * wasm32-dis.c: Likewise.	5 years ago
Alan Modra	250d07de5c	Update year range in copyright notice of binutils files	5 years ago
Alan Modra	aa3c112fab	Power10 Reduced precision outer product operations include/ * opcode/ppc.h (PPC_OPERAND_ACC): Define. Renumber following PPC_OPERAND defines. opcodes/ * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): New functions. (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK, YMSK2, XA6a, XA6ap, XB6a entries. (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define. (PPCVSX4): Define. (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16. (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp, pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8, pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2, pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp, pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp, pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn, pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn. gas/ * config/tc-ppc.c (pre_defined_registers): Add accumulators. (md_assemble): Check acc specified in correct operand. * testsuite/gas/ppc/outerprod.d, * testsuite/gas/ppc/outerprod.s, * testsuite/gas/ppc/vsx4.d, * testsuite/gas/ppc/vsx4.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them.	6 years ago
Alan Modra	7c1f422735	PowerPC Rename powerxx to power10 Now that ISA3.1 is out we can finish with the powerxx silliness. bfd/ * elf64-ppc.c: Rename powerxx to power10 throughout. gas/ * config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10 renaming. * testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in place of -mfuture/-Mfuture. * testsuite/gas/ppc/prefix-pcrel.d: Likewise. * testsuite/gas/ppc/prefix-reloc.d: Likewise. gold/ * powerpc.cc: Rename powerxx to power10 throughout. include/ * elf/ppc64.h: Update comment. * opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX. ld/ * testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in place of -mfuture/-Mfuture. * testsuite/ld-powerpc/notoc2.d: Likewise. * testsuite/ld-powerpc/powerpc.exp: Likewise. * testsuite/ld-powerpc/tlsgd.d: Likewise. * testsuite/ld-powerpc/tlsie.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power10" entry. (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming. * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.	6 years ago
Alan Modra	b3adc24a07	Update year range in copyright notice of binutils files	6 years ago
Peter Bergner	dd7efa7915	PowerPC add initial -mfuture instruction support This patch adds initial 64-bit insn assembler/disassembler support. The only instruction added is "pnop" along with the automatic aligning of prefix instruction so they do not cross 64-byte boundaries. include/ * dis-asm.h (WIDE_OUTPUT): Define. * opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare. (PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX), (PPC_PREFIX_P, PPC_PREFIX_SEG): Define. opcodes/ * ppc-dis.c (ppc_opts): Add "future" entry. (PREFIX_OPCD_SEGS): Define. (prefix_opcd_indices): New array. (disassemble_init_powerpc): Initialize prefix_opcd_indices. (lookup_prefix): New function. (print_insn_powerpc): Handle 64-bit prefix instructions. * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), (PMRR, POWERXX): Define. (prefix_opcodes): New instruction table. (prefix_num_opcodes): New constant. binutils/ * objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes. (struct insn_label_list): New. (insn_labels, free_insn_labels): New variables. (ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs. (ppc_frob_label, ppc_new_dot_label): Move functions earlier in file and call ppc_record_label. (md_assemble): Handle 64-bit prefix instructions. Align labels that are on the same line as a prefix instruction. * config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to later in the file. (md_start_line_hook): Define. (ppc_start_line_hook): Declare. * testsuite/gas/ppc/prefix-align.d, * testsuite/gas/ppc/prefix-align.s: New test. * testsuite/gas/ppc/ppc.exp: Run new test.	8 years ago
Alan Modra	96a86c01d1	PR24390, Don't decode mtfsb field as a cr field "mtfsb0 4cr7+lt" doesn't make all that much sense, but unfortunately glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit. So for backwards compatibility accept cr field expressions when assembling mtfsb operands, but disassemble to a plain number. PR 24390 include/ opcode/ppc.h (PPC_OPERAND_CR_REG): Comment. opcodes/ * ppc-opc.c (BTF): Define. (powerpc_opcodes): Use for mtfsb. ppc-dis.c (print_insn_powerpc): Print fields with both PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. gas/ * testsuite/gas/ppc/476.d: Update mtfsb. testsuite/gas/ppc/a2.d: Likewise.	7 years ago
Alan Modra	827041555a	Update year range in copyright notice of binutils files	7 years ago
Alan Modra	d1a3c973fa	PR24028, PPC_INT_FMT PPC_INT_FMT is redundant now that bfd.h pulls in inttypes.h if available. Apparently MacOS Mojave defines int64_t as long long even though long is also 64 bits, which confuses the logic selecting PPC_INT_FMT (and BFD_PRI64 too). Hopefully inttypes.h is available on Mojave. PR 24028 include/ * opcode/ppc.h (PPC_INT_FMT): Delete. opcodes/ * ppc-dis.c (print_insn_powerpc): Replace PPC_INT_FMT uses with PRId64/PRIx64.	7 years ago
Alan Modra	bb6bf75e7a	PowerPC @l , @h and @ha warnings, plus VLE e_li This patch started off just adding the warnings in tc-ppc.c about incorrect usage of @l, @h and @ha in instructions that don't have 16-bit D-form fields. That unfortunately showed up three warnings in ld/testsuite/ld-powerpc/vle-multiseg.s on instructions like e_li r3, IV_table@l+0x00 which was being assembled to 8: 70 60 00 00 e_li r3,0 a: R_PPC_ADDR16_LO IV_table The ADDR16_LO reloc is of course completely bogus on e_li, which has a split 20-bit signed integer field in bits 0x1f7fff, the low 11 bit in 0x7ff, the next 5 bits in 0x1f0000, and the high 4 bits in 0x7800. Applying an ADDR16_LO reloc to the instruction potentially changes the e_li instruction to e_add2i., e_add2is, e_cmp16i, e_mull2i, e_cmpl16i, e_cmph16i, e_cmphl16i, e_or2i, e_and2i., e_or2is, e_lis, e_and2is, or some invalid encodings. Now there is a relocation that suits e_li, R_PPC_VLE_ADDR20, which was added 2017-09-05 but I can't see code in gas to generate the relocation. In any case, VLE_ADDR20 probably doesn't have the correct semantics for @l since ideally you'd want an @l to pair with @h or @ha to generate a 32-bit constant. Thus @l should only produce a 16-bit value, I think. So we need some more relocations to handle e_li it seems, or as I do in this patch, modify the behaviour of existing relocations when applied to e_li instructions. include/ * opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define. bfd/ * elf32-ppc.c (ppc_elf_howto_raw <R_PPC_VLE_ADDR20>): Correct mask and shift value. (ppc_elf_vle_split16): Use E_OPCODE_MASK. Handle e_li specially. gas/ * config/tc-ppc.c (md_assemble): Adjust relocs for VLE before TLS tweaks. Handle e_li. Warn on unexpected operand field for lo16/hi16/ha16 relocs.	7 years ago
Alan Modra	9cf7e5687f	Use operand->extract to provide defaults for optional PowerPC operands Most optional operands to powerpc instructions use a default value of zero, but there are a few exceptions. Those have been handled by PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table for the default value, smuggled in the shift field. This patch changes that to using the operand extract function to provide non-zero defaults. I've also moved the code determining whether optional operands are provided or omitted, to the point the first optional operand is seen, and allowed for the possibility of optional base register operands in a future patch. The patch does change the error you get on invalid assembly like ld 3,4 You'll now see "missing operand" rather than "syntax error; end of line, expected `('". gas/ * config/tc-ppc.c (md_assemble): Delay counting of optional operands until one is encountered. Allow for the possibility of optional base regs, ie. PPC_OPERAND_PARENS. Call ppc_optional_operand_value with extra args. include/ * opcode/ppc.h (struct powerpc_operand): Correct "insert" comment. Mention use of "extract" function to provide default value. (PPC_OPERAND_OPTIONAL_VALUE): Delete. (ppc_optional_operand_value): Rewrite to use extract function. opcodes/ * ppc-dis.c (operand_value_powerpc): Init "invalid". (skip_optional_operands): Count optional operands, and update ppc_optional_operand_value call. * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg. (extract_vlensi): Likewise. (extract_fxm): Return default value for missing optional operand. (extract_ls, extract_raq, extract_tbr): Likewise. (insert_sxl, extract_sxl): New functions. (insert_esync, extract_esync): Remove Power9 handling and simplify. (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE flag and extra entry. (powerpc_operands <SXL>): Likewise, and use insert_sxl and extract_sxl.	8 years ago
Alex Chadwick	fa758a7046	PowerPC Improve support for Gekko & Broadway This is a relatively straightforward patch to improve support for the IBM Gekko and IBM Broadway processors. Broadway is functionally equivalent to the IBM 750CL, while Gekko's functionality is a subset of theirs. The patch simplifies this reality and adds -mgekko and -mbroadway as aliases for -m750cl. I didn't feel it was worth wasting a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of simplified mnemonics for special purpose register access. Notably, Broadway adds 4 additional IBAT and DBAT registers but these are not assigned sequential SPR numbers. gas/ * config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway. * doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * testsuite/gas/ppc/broadway.d, * testsuite/gas/ppc/broadway.s: New test for broadway. * testsuite/gas/ppc/ppc.exp: Run new test. include/ * opcode/ppc.h (PPC_OPCODE_750): Adjust comment. opcodes/ * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. (powerpc_init_dialect): Handle bfd_mach_ppc_750. * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to support disjointed BAT. (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. (XSPRGQR_MASK, GEKKO, BROADWAY): Define. (powerpc_opcodes): Add 750cl extended mnemonics for spr access.	8 years ago
Peter Bergner	98553ad33e	Remove fake operand handling for extended mnemonics. opcodes/ * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba, insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions. (insert_bab, extract_bab, insert_btab, extract_btab, insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions. (BAT, BBA VBA RBS XB6S): Delete macros. (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros. (BB, BD, RBX, XC6): Update for new macros. (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset, crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp, e_crnot, e_crclr, e_crset, e_crmove>: Likewise. * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands. include/ * opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro. gas/ * config/tc-ppc.c (md_assemble): Delete handling of fake operands. * testsuite/gas/ppc/common.s (crmove, cror, or., or, nor., nor): Add test of extended mnemonics. * testsuite/gas/ppc/common.d: Likewise. Don't match instruction offset. * testsuite/gas/ppc/spe.s (evor, evnor): Add test of extended mnemonics. * testsuite/gas/ppc/spe.d: Likewise. Don't match instruction offset.	8 years ago
Peter Bergner	2ceb7719f7	Cleanup ppc code dealing with opcode dumps. include/ * opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned. (vle_num_opcodes): Likewise. (spe2_num_opcodes): Likewise. opcodes/ * ppc-opc.c (powerpc_num_opcodes): Likewise. (vle_num_opcodes): Likewise. (spe2_num_opcodes): Likewise. * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite initialization loop. (disassemble_init_powerpc) <vle_opcd_indices>: Likewise. (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize only once. gas/ * config/tc-ppc.c (ppc_setup_opcodes) <powerpc_opcodes>: Rewrite code to dump the entire opcode table. (ppc_setup_opcodes) <spe2_opcodes>: Likewise. (ppc_setup_opcodes) <vle_opcodes>: Likewise. Fix calculation of opcode index.	8 years ago
Alan Modra	219d1afa89	Update year range in copyright notice of binutils files	8 years ago
Peter Bergner	0f873fd58b	Use consistent types for holding instructions, instruction masks, etc. include/ * opcode/ppc.h (PPC_INT_FMT): Define. (struct powerpc_opcode) <opcode>: Update type. (struct powerpc_opcode) <mask>: Likewise. (struct powerpc_opcode) <bitm>: Likewise. (struct powerpc_opcode) <insert>: Likewise. (struct powerpc_opcode) <extract>: Likewise. (ppc_optional_operand_value): Likewise. gas/ * config/tc-ppc.c (last_insn): Update type. (insn_validate) <omask, mask>: Likewise. (ppc_setup_opcodes) <mask, right_bit>: Likewise. <PRINT_OPCODE_TABLE>: Update types and printf format specifiers. (ppc_insert_operand): Update return and argument types and remove unneeded type casts. <min, max, right, tmp>: Update type. (md_assemble): Remove unneeded type casts. <insn, val, tmp_insn>: Update type. opcodes/ * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space. (operand_value_powerpc): Update return and argument type. <value, top>: Update type. (skip_optional_operands): Update argument type. (lookup_powerpc): Likewise. (lookup_vle): Likewise. <table_opcd, table_mask, insn2>: Update type. (lookup_spe2): Update argument type. <table_opcd, table_mask, insn2>: Update type. (print_insn_powerpc) <insn, value>: Update type. Use PPC_INT_FMT for printing instructions and operands. * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary, insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat, insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp, extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo, extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm, extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls, insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6, extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi, insert_ral, extract_ral, insert_ram, extract_ram, insert_raq, extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs, insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n, extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w, insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr, extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr, insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6, extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s, insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi, extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui, extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0, extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0, insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0, extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8, insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even, extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2, extract_off_spe2, insert_Ddd, extract_Ddd): Update types. (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15, BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX, DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK, SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST, VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET, VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA, VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK, XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK, XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK, XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB, XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.	8 years ago
Alexander Fedotov	7408194835	[PowerPC VLE] Add SPE2 and EFS2 instructions support include/ * opcode/ppc.h: (spe2_opcodes, spe2_num_opcodes): New. (PPC_OPCODE_SPE2): New define. (PPC_OPCODE_EFS2): Likewise. (SPE2_XOP): Likewise. (SPE2_XOP_TO_SEG): Likewise. opcodes/ * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "e200z4" entry. New entries efs2 and spe2. Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry. (SPE2_OPCD_SEGS): New macro. (spe2_opcd_indices): New. (disassemble_init_powerpc): Handle SPE2 opcodes. (lookup_spe2): New function. (print_insn_powerpc): call lookup_spe2. * ppc-opc.c (insert_evuimm1_ex0): New function. (extract_evuimm1_ex0): Likewise. (insert_evuimm_lt8): Likewise. (extract_evuimm_lt8): Likewise. (insert_off_spe2): Likewise. (extract_off_spe2): Likewise. (insert_Ddd): Likewise. (extract_Ddd): Likewise. (DD): New operand. (EVUIMM_LT8): Likewise. (EVUIMM_LT16): Adjust. (MMMM): New operand. (EVUIMM_1): Likewise. (EVUIMM_1_EX0): Likewise. (EVUIMM_2): Adjust. (NNN): New operand. (VX_OFF_SPE2): Likewise. (BBB): Likewise. (DDD): Likewise. (VX_MASK_DDD): New mask. (HH): New operand. (VX_RA_CONST): New macro. (VX_RA_CONST_MASK): Likewise. (VX_RB_CONST): Likewise. (VX_RB_CONST_MASK): Likewise. (VX_OFF_SPE2_MASK): Likewise. (VX_SPE_CRFD): Likewise. (VX_SPE_CRFD_MASK VX): Likewise. (VX_SPE2_CLR): Likewise. (VX_SPE2_CLR_MASK): Likewise. (VX_SPE2_SPLATB): Likewise. (VX_SPE2_SPLATB_MASK): Likewise. (VX_SPE2_OCTET): Likewise. (VX_SPE2_OCTET_MASK): Likewise. (VX_SPE2_DDHH): Likewise. (VX_SPE2_DDHH_MASK): Likewise. (VX_SPE2_HH): Likewise. (VX_SPE2_HH_MASK): Likewise. (VX_SPE2_EVMAR): Likewise. (VX_SPE2_EVMAR_MASK): Likewise. (PPCSPE2): Likewise. (PPCEFS2): Likewise. (vle_opcodes): Add EFS2 and some missing SPE opcodes. (powerpc_macros): Map old SPE instructions have new names with the same opcodes. Add SPE2 instructions which just are mapped to SPE2. (spe2_opcodes): Add SPE2 opcodes. gas/ * config/tc-ppc.c: (md_parse_option): Add mspe2 switch. (md_show_usage): Document -mspe2. (ppc_setup_opcodes): Handle spe2_opcodes. * doc/as.texinfo: Document -mspe2. * doc/c-ppc.texi: Likewise. * testsuite/gas/ppc/efs.d: New file. * testsuite/gas/ppc/efs.s: Likewise. * testsuite/gas/ppc/efs2.d: Likewise. * testsuite/gas/ppc/efs2.s: Likewise. * testsuite/gas/ppc/ppc.exp: Run new tests. * testsuite/gas/ppc/spe.d: New file. * testsuite/gas/ppc/spe.s: Likewise. * testsuite/gas/ppc/spe2-checks.d: Likewise. * testsuite/gas/ppc/spe2-checks.l: Likewise. * testsuite/gas/ppc/spe2-checks.s: Likewise. * testsuite/gas/ppc/spe2.d: Likewise. * testsuite/gas/ppc/spe2.s: Likewise. * testsuite/gas/ppc/spe_ambiguous.d: Likewise. * testsuite/gas/ppc/spe_ambiguous.s: Likewise.	9 years ago
Alexander Fedotov	e3c2f928b8	[PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction support include/ * opcode/ppc.h (PPC_OPCODE_LSP): New define. opcodes/ * ppc-opc.c (insert_evuimm2_ex0): New function. (extract_evuimm2_ex0): Likewise. (insert_evuimm4_ex0): Likewise. (extract_evuimm4_ex0): Likewise. (insert_evuimm8_ex0): Likewise. (extract_evuimm8_ex0): Likewise. (insert_evuimm_lt16): Likewise. (extract_evuimm_lt16): Likewise. (insert_rD_rS_even): Likewise. (extract_rD_rS_even): Likewise. (insert_off_lsp): Likewise. (extract_off_lsp): Likewise. (RD_EVEN): New operand. (RS_EVEN): Likewise. (RSQ): Adjust. (EVUIMM_LT16): New operand. (HTM_SI): Adjust. (EVUIMM_2_EX0): New operand. (EVUIMM_4): Adjust. (EVUIMM_4_EX0): New operand. (EVUIMM_8): Adjust. (EVUIMM_8_EX0): New operand. (WS): Adjust. (VX_OFF): New operand. (VX_LSP): New macro. (VX_LSP_MASK): Likewise. (VX_LSP_OFF_MASK): Likewise. (PPC_OPCODE_LSP): Likewise. (vle_opcodes): Add LSP opcodes. * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry. gas/ * testsuite/gas/ppc/lsp-checks.d, * testsuite/gas/ppc/lsp-checks.l, * testsuite/gas/ppc/lsp-checks.s: New test. * testsuite/gas/ppc/lsp.d, * testsuite/gas/ppc/lsp.s: New test. * testsuite/gas/ppc/ppc.exp: Run new tests.	9 years ago
Alan Modra	c03dc33b60	Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500 PPC_OPCODE_* renumbered to fill the gaps left by previous patches, and reordered chronologically just because. I kept PPC_OPCODE_TMR because presumably it might be used in future APUinfo for e6500. include/ * opcode/ppc.h (PPC_OPCODE_): Renumber and order chronologically. (PPC_OPCODE_SPE): Comment on this and other bits used for APUinfo. opcodes/ ppc-dis.c (ppc_opts): Formatting. Set PPC_OPCODE_TMR for e6500. * ppc-opc.c (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.	9 years ago
Alan Modra	ef85eab0ec	Bye bye PPC_OPCODE_HTM and -mhtm The -mhtm option is fairly useless too. include/ * opcode/ppc.h (PPC_OPCODE_HTM): Delete. gas/ * config/tc-ppc.c (md_show_usage): Delete mention of -mhtm. * testsuite/gas/ppc/htm.d: Pass -mpower8 and -Mpower8. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_HTM and "htm". * ppc-opc.c (PPCHTM): Define as PPC_OPCODE_POWER8.	9 years ago
Alan Modra	9570835e55	Bye Bye PPC_OPCODE_VSX3 This bit is also useless as it can be replaced with PPC_OPCODE_POWER9. Defining the VSX2 and VSX3 selection based on cpu bits also lets the assembler/disassembler distinguish between the power7 VSX opcodes and the power8 ones. Note that this change means -mvsx now reverts back to just adding the power7 VSX insns. include/ * opcode/ppc.h (PPC_OPCODE_VSX3): Delete. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_VSX3. * ppc-opc.c (PPCVSX2): Define as PPC_OPCODE_POWER8. (PPCVSX3): Define as PPC_OPCODE_POWER9.	9 years ago
Alan Modra	9a85b496ac	Bye bye PPC_OPCODE_ALTIVEC2 This bit is worse than useless. Using it prevents the assembler and disassembler distinguishing between opcodes added for power8 and those added for power9. include/ * opcode/ppc.h (PPC_OPCODE_ALTIVEC2): Delete. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2. * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8\|PPC_OPCODE_E6500. (PPCVEC3): Define as PPC_OPCODE_POWER9.	9 years ago
Alan Modra	52be03fd13	PowerPC -Mraw disassembly This adds -Mraw for PowerPC objdump, a disassembler option to display the underlying machine instruction rather than aliases. For example, "rlwinm" always rather than "rotlwi" when the instruction is performing a simple rotate. binutils/ * doc/binutils.texi (objdump): Document PowerPC -M options. gas/ * config/tc-ppc.c (md_parse_option): Reject -mraw. include/ * opcode/ppc.h (PPC_OPCODE_RAW): Define. (PPC_OPCODE_): Make them all unsigned long long constants. opcodes/ ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add "raw" option. (lookup_powerpc): Don't special case -1 dialect. Handle PPC_OPCODE_RAW. (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first lookup_powerpc call, pass it on second.	9 years ago
Alan Modra	7e0de605cb	PowerPC register expression checks This stops powerpc gas blithely accepting such nonsense as "addi %f4,%cr3,%r31". PR 21118 gas/ * NEWS: Mention powerpc register checks. * config/tc-ppc.c (struct pd_reg): Make value a short. Add flags. (pre_defined_registers): Delete fpscr and pmr entries. Set register type in flags. (cr_names): Set type in flags. (reg_name_search): Return pointer to struct pd_reg rather than value. (register_name): Adjust to suit. Set X_md from flags. (ppc_parse_name): Likewise. (ppc_optimize_expr): New function. (md_assemble): Verify expresion reg flags match operand. * config/tc-ppc.h (md_optimize_expr): Define. (ppc_optimize_expr): Declare. include/ * opcode/ppc.h (PPC_OPERAND_): Reassign values, regs first. (PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define. opcodes/ ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.	9 years ago
Alan Modra	2571583aed	Update year range in copyright notice of all files.	9 years ago
Alan Modra	08dc996fed	PR20744, Incorrect PowerPC VLE relocs VLE 16A and 16D relocs were functionally swapped. PR 20744 include/ * opcode/ppc.h: Define VLE insns using 16A and 16D relocs. bfd/ * elf32-ppc.h (struct ppc_elf_params): Add vle_reloc_fixup field. * elf32-ppc.c: Include opcode/ppc.h. (ppc_elf_howto_raw): Correct dst_mask for R_PPC_VLE_LO16A, R_PPC_VLE_LO16D, R_PPC_VLE_HI16A, R_PPC_VLE_HI16D, R_PPC_VLE_HA16A, R_PPC_VLE_HA16D, R_PPC_VLE_SDAREL_LO16A, R_PPC_VLE_SDAREL_LO16D, R_PPC_VLE_SDAREL_HI16A, R_PPC_VLE_SDAREL_HI16D, R_PPC_VLE_SDAREL_HA16A, and R_PPC_VLE_SDAREL_HA16D relocs. (ppc_elf_link_hash_table_create): Update default_params init. (ppc_elf_vle_split16): Correct shift and mask. Add params. Report or fix insn/reloc mismatches. (ppc_elf_relocate_section): Pass input_section, offset and fixup to ppc_elf_vle_split16. binutils/ * NEWS: Mention PowerPC VLE relocation error. gas/ * config/tc-ppc.c: Delete VLE insn defines. (md_assemble): Swap use_a_reloc and use_d_reloc. * testsuite/gas/ppc/vle-reloc.d: Update. ld/ * emultempl/ppc32elf.em (params): Update initializer. Handle --vle-reloc-fixup command line arg.	10 years ago
Alan Modra	a5721ba270	Disallow 3-operand cmp[l][i] for ppc64 cmp[l][o] get an optional L field only when generating 32-bit code. dcbf, tlbie and tlbiel keep their optional L field, ditto for R field of tbegin. cmprb, tsr., wlcr[all] and mtsle all change to a compulsory L field. L field of dcbf and wclr is 2 bits. PR 20641 include/ * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define. opcodes/ * ppc-opc.c (L): Make compulsory. (LOPT): New, optional form of L. (HTM_R): Define as LOPT. (L0, L1): Delete. (L32OPT): New, optional for 32-bit L. (L2OPT): New, 2-bit L for dcbf. (SVC_LEC): Update. (L2): Define. (insert_l0, extract_l0, insert_l1, extract_l2): Delete. (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT. <dcbf>: Use L2OPT. <tlbiel, tlbie>: Use LOPT. <wclr, wclrall>: Use L2. gas/ * config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32. * testsuite/gas/ppc/power8.s: Provide tbegin. operand. * testsuite/gas/ppc/power9.d: Update cmprb disassembly.	10 years ago
Andrew Jenner	dfdaec14b0	Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions. bfd/ * elf32-ppc.c (is_branch_reloc): Recognise VLE branch relocations. (ppc_elf_howto_raw): Fix dst_mask of R_PPC_VLE_REL15. (ppc_elf_vle_split16): Clear field before inserting. opcodes/ * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and 'e_cmplwi' to 'e_cmpli' instead. (OPVUPRT, OPVUPRT_MASK): Define. (powerpc_opcodes): Add E200Z4 insns. (vle_opcodes): Add context save/restore insns. include/ * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.	10 years ago
Trevor Saunders	1fe0971e41	add more extern C opcodes/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * nds32-asm.h: Add extern "C". * sh-opc.h: Likewise. bfd/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * elf32-hppa.h: Add extern "C". * elf32-nds32.h: Likewise. * elf32-tic6x.h: Likewise. include/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * elf/mips.h: Likewise. * elf/sh.h: Likewise. * opcode/d10v.h: Likewise. * opcode/d30v.h: Likewise. * opcode/ia64.h: Likewise. * opcode/mips.h: Likewise. * opcode/ppc.h: Likewise. * opcode/sparc.h: Likewise. * opcode/tic6x.h: Likewise. * opcode/v850.h: Likewise.	10 years ago
Alan Modra	6f2750feaf	Copyright update for binutils	10 years ago
Peter Bergner	a680de9a98	Add assembler, disassembler and linker support for power9. include/opcode/ * ppc.h (PPC_OPCODE_POWER9): New define. (PPC_OPCODE_VSX3): Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. Add PPC_OPCODE_VSX3 to the vsx entry. (powerpc_init_dialect): Set default dialect to power9. * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, extract_l1 insert_xtq6, extract_xtq6): New static functions. (insert_esync): Test for illegal L operand value. (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, PPCVSX3): New defines. (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu, fcmpo, ftdiv, ftsqrt>: Use XBF_MASK. <mcrxr>: Use XBFRARB_MASK. <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq., bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc., cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first, cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx, lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll, lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw, modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last, rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx, stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx, subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh, vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd, vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d, vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq, vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd, vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait, xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp, xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp, xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz, xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp, xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp, xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo, xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo, xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo, xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp, xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp, xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp, xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw, xxinsertw, xxperm, xxpermr, xxspltib>: New instructions. <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9. <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands. include/elf/ * ppc.h (R_PPC_REL16DX_HA): New reloction. * ppc64.h (R_PPC64_REL16DX_HA): Likewise. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA. (ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA. (ppc_elf_addr16_ha_reloc): Likewise. (ppc_elf_check_relocs): Likewise. (ppc_elf_relocate_section): Likewise. (is_insn_dq_form): Handle lxv and stxv instructions. * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA. (ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA. (ppc64_elf_ha_reloc): Likewise. (ppc64_elf_check_relocs): Likewise. (ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. * reloc.c (BFD_RELOC_PPC_REL16DX_HA): New. elfcpp/ * powerpc.h (R_POWERPC_REL16DX_HA): Define. gas/ * doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * config/tc-ppc.c (md_show_usage): Likewise. (md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA. (md_apply_fix): Likewise. (ppc_handle_align): Handle power9's group ending nop. gas/testsuite/ * gas/ppc/altivec3.s: New test. * gas/ppc/altivec3.d: Likewise. * gas/ppc/vsx3.s: Likewise. * gas/ppc/vsx3.d: Likewise. * gas/ppc/power9.s: Likewise. * gas/ppc/power9.d: Likewise. * gas/ppc/ppc.exp: Run them. * gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests. * gas/ppc/power8.d: Likewise. * gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ... <lxvd2x, stxvd2x>: ...to this. * gas/ppc/vsx.d: Likewise. gold/ * gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function. (Powerpc_relocate_functions::addr16dx_ha): Likewise. (Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Likewise. ld/testsuite/ * ld-powerpc/addpcis.d: New test. * ld-powerpc/addpcis.s: New test. * ld-powerpc/powerpc.exp: Run it.	11 years ago
Nick Clifton	b6518b3871	Fix compile time warnings generated when compiling with clang. bfd * bout.c (b_out_slurp_reloc_table): Cast constant to unsigned in order to avoid problems with left shifting negative values. (abs32code): Likewise. * mach-o.c (FILE_ALIGN): Likewise. * coff-rs6000.c (xcoff_debug_sections): Delete unused static array. * elf32-visium.c (visium_reloc_map): Likewise. * elf32-arm.c (elf32_arm_final_link_relocate): Remove useless calls to abs function. * elf32-frv.c (_frvfdpic_relax_tls_entries): Likewise. * elf32-score.c (score_elf_final_link_relocate): Likewise. * elf32-score7.c (score_elf_final_link_relocate): Likewise. * elf32-i860.c (i860_howto_pc26_reloc): Use multiplication instead of shifting to create a negative mask. * elf32-msp430.c (elf_backend_special_sections): Define. * elfxx-mips.c (got_ofst_reloc_p): Delete unused function. (got_hi16_reloc_p): Delete unused function. * ppcboot.c (ppcboot_bfd_print_private_bfd_data): Fix test of partition name. gas * config/tc-ppc.c (insn_validate): Cast PPC_OPSHIFT_INV to an int. opcode * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left shifting. ld * emultempl/elf32.em (ehdr_start_empty): New static variable. (before_allocation): Use it to initialise ehdr_start_save. * emultempl/pe.em (write_build_id): Remove useless double parenthesis. * emultempl/pep.em (write_build_id): Likewise. opcodes * bfin-dis.c (fmtconst): Remove unnecessary call to the abs function. * tic30-dis.c (print_branch): Likewise. * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed value before left shifting. * fr30-ibld.c (fr30_cgen_extract_operand): Likewise. * hppa-dis.c (print_insn_hppa): Likewise. * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static array. * msp430-dis.c (msp430_singleoperand): Likewise. (msp430_doubleoperand): Likewise. (print_insn_msp430): Likewise. * nds32-asm.c (parse_operand): Likewise. * sh-opc.h (MASK): Likewise. * v850-dis.c (get_operand_value): Likewise.	11 years ago
Alan Modra	ef5a96d564	Remove ppc860, ppc750cl, ppc7450 insns from common ppc. Back in the day support for these processors was added, we probably didn't want to waste PPC_OPCODE bits on minor variations. I've had a complaint that disassembly of mfspr/mtspr was wrong for power8. This patch fixes that problem. Note that since -m860/-m850/-m821 are new gas options enabling the mpc8xx specific mfspr/mtspr variants it is possible that this change will break some mpc8xx assembly code. ie. you might need to modify makefiles to pass -m860 to gas. include/opcode/ * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define. opcodes/ * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_. ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry. gas/ * config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860. * doc/c-ppc.texi (PowerPC-Opts): Likewise. gas/testsuite/ * gas/ppc/titan.d: Correct mfmcsrr0 disassembly.	11 years ago
Peter Bergner	11a0cf2ec0	Allow for optional operands with non-zero default values. ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand with the value of either a 0 or 1. It also defines an extended mnemonic with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1". I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the problem is, optional operands that are ommitted always default to the value 0, which is wrong in this case. I have added support for allowing non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE that specifies that the default operand value to be used is stored in the SHIFT field of the operand field immediately following this one. This fixes the rfebb issue. I also fixed the mftb and mfcr instructions so they use the same mechanism. This allows us to flag invalid uses of mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd]. include/opcode/ * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New. (ppc_optional_operand_value): New inline function. opcodes/ * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. * ppc-opc.c (FXM4): Add non-zero optional value. (TBR): Likewise. (SXL): Likewise. (insert_fxm): Handle new default operand value. (extract_fxm): Likewise. (insert_tbr): Likewise. (extract_tbr): Likewise. gas/ * config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value. Allow for optional operands without insert functions. gas/testsuite/ * gas/ppc/power8.d: Fixup rfebb test results. * gas/ppc/a2.s: Fix invalid mfcr test. * gas/ppc/a2.d: Likewise.	11 years ago
Alan Modra	b90efa5b79	ChangeLog rotatation and copyright year update	11 years ago
Alan Modra	4b95cf5c0c	Update copyright years	12 years ago
Peter Bergner	5817ffd1f8	include/opcode/ * ppc.h (PPC_OPCODE_POWER8): New define. (PPC_OPCODE_HTM): Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries. * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK, XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines. (SH6): Update. <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.", "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.", "treclaim.", "tsr.">: Add POWER8 HTM opcodes. <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes. gas/ * doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * config/tc-ppc.c (md_show_usage): Likewise. (ppc_handle_align): Handle power8's group ending nop. gas/testsuite/ * gas/ppc/htm.d: New test. * gas/ppc/htm.s: Likewise. * gas/ppc/power8.d: Likewise. * gas/ppc/power8.s: Likewise. * gas/ppc/ppc.exp: Run them.	13 years ago
Alan Modra	776fc41826	include/opcode/ * ppc.h (ppc_parse_cpu): Update prototype. opcodes/ * ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits set from ppc_opts.sticky in it. Delete "retain_mask". (powerpc_init_dialect): Choose default dialect from info->mach before parsing -M options. Handle more bfd_mach_ppc variants. Update common default to power7. gas/ * config/tc-ppc.c (sticky): New var. (md_parse_option, ppc_machine): Update ppc_parse_cpu calls. gas/testsuite/ * gas/ppc/astest2.d: Pass -Mppc to objdump. ld/testsuite/ * ld-powerpc/plt1.d: Update for default "at" branch hints. * ld-powerpc/tlsexe.d: Likewise. * ld-powerpc/tlsexetoc.d: Likewise. * ld-powerpc/tlsopt1.d: Likewise. * ld-powerpc/tlsopt1_32.d: Likewise. * ld-powerpc/tlsopt2.d: Likewise. * ld-powerpc/tlsopt2_32.d: Likewise. * ld-powerpc/tlsopt4.d: Likewise. * ld-powerpc/tlsopt4_32.d: Likewise. * ld-powerpc/tlsso.d: Likewise. * ld-powerpc/tlstocso.d: Likewise.	14 years ago
James Lemke	b9c361e0ad	Add support for PowerPC VLE.	14 years ago
Alan Modra	aea77599d0	include/opcode/ * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR. opcodes/ * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500". * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New. (PPCVEC2, PPCTMR, E6500): New short names. (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt, mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx, lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl, lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl, lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC optional operands on sync instruction for E6500 target. bfd/ * archures.c: Add bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add entryies for bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500. gas/ * config/tc-ppc.c (md_show_usage): Document -me5500 and -me6500. (ppc_handle_align): Add termination nop opcode for e500mc family. * doc/as.texinfo: Document options -me5500 and -me6500. * doc/c-ppc.texi: Likewise. gas/testsuite/ * gas/ppc/e500mc64_nop.s: New test case for e500mc family termination nops. * gas/ppc/e500mc64_nop.d: Likewise. * gas/ppc/e5500_nop.s: Likewise. * gas/ppc/e5500_nop.d: Likewise. * gas/ppc/e6500_nop.s: Likewise. * gas/ppc/e6500_nop.d: Likewise. * gas/ppc/e6500.s: New. * gas/ppc/e6500.d: Likewise. * gas/ppc/ppc.exp: Run e6500, e500mc64_nop, e5500_nop, and e6500_nop.	14 years ago

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92 Commits (94dd9fb7482cc292f6ea7e641340563ca5536fcc)