binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Yufeng Zhang	49eec19300	gas/ * config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg; call aarch64_sys_reg_deprecated_p and warn about the deprecated system registers. gas/testsuite/ * gas/aarch64/deprecated.d: New file. * gas/aarch64/deprecated.l: New file. * gas/aarch64/deprecated.s: New file. * gas/aarch64/sysreg-1.s: Add tests. * gas/aarch64/sysreg-1.d: Add tests. include/opcode/ * aarch64.h (aarch64_sys_reg): New typedef. (aarch64_sys_regs): Change to define with the new type. (aarch64_sys_reg_deprecated_p): Declare. opcodes/ * aarch64-opc.c (F_DEPRECATED): New macro. (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with F_DEPRECATED. (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on AARCH64_OPND_SYSREG.	13 years ago
Yufeng Zhang	68a6428382	gas/ * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1. gas/testsuite/ * gas/aarch64/alias.s: Add tests. * gas/aarch64/alias.d: Update. * gas/aarch64/no-aliases.d: Update. * gas/aarch64/diagnostic.s: Add tests. * gas/aarch64/diagnostic.l: Update. * gas/aarch64/illegal.s: Add tests. * gas/aarch64/illegal.l: Update. include/opcode/ * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. (enum aarch64_opnd): Add AARCH64_OPND_COND1. opcodes/ * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'. (convert_from_csel): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1. (aarch64_print_operand): Handle AARCH64_OPND_COND1. * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of COND for cinc, cset, cinv, csetm and cneg. (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1. * aarch64-asm-2.c: Re-generated. * aarch64-dis-2.c: Ditto. * aarch64-opc-2.c: Ditto.	13 years ago
Alan Modra	e8910a83af	Replace DT_PPC_TLSOPT with DT_PPC_OPT. This removes the DT_PPC_TLSOPT/DT_PPC64_TLSOPT dynamic tag and replaces it with DT_PPC_OPT/DT_PPC64_OPT tag to provide the same functionality and more. This isn't backwards compatible, but the TLSOPT tag hasn't been used since the tls optimisation support was never submitted to glibc. /include/elf/ * ppc.h (DT_PPC_TLSOPT): Delete. (DT_PPC_OPT, PPC_OPT_TLS): Define. * ppc64.h (DT_PPC64_TLSOPT): Delete. (DT_PPC64_OPT, PPC64_OPT_TLS, PPC64_OPT_MULTI_TOC): Define. bfd/ * elf32-ppc.c (ppc_elf_size_dynamic_sections): Use new DT_PPC_OPT tag to specify tls optimisation. * elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise. (ppc64_elf_finish_dynamic_sections): Specify whether multiple toc pointers are used via DT_PPC64_OPT. binutils/ * readelf.c (get_ppc_dynamic_type): Replace PPC_TLSOPT with PPC_OPT. (get_ppc64_dynamic_type): Replace PPC64_TLSOPT with PPC64_OPT.	13 years ago
Alan Modra	6911b7dcb8	Add ELFv2 .localentry support. This defines the ELF symbol st_other field used to encode the number of instructions between a function "global entry" and its "local entry", and adds support related to the local entry offset. include/elf/ * ppc64.h (STO_PPC64_LOCAL_BIT, STO_PPC64_LOCAL_MASK): Define. (ppc64_decode_local_entry, ppc64_encode_local_entry): New functions. (PPC64_LOCAL_ENTRY_OFFSET, PPC64_SET_LOCAL_ENTRY_OFFSET): Define. bfd/ * elf64-ppc.c (struct ppc_stub_hash_entry): Add "other". (stub_hash_newfunc): Init new ppc_stub_hash_entry field, and one we forgot, "plt_ent". (ppc64_elf_add_symbol_hook): Check ELFv1 objects don't have st_other bits only valid in ELFv2. (ppc64_elf_merge_symbol_attribute): New function. (ppc_type_of_stub): Add local_off param to test branch range. (ppc_build_one_stub): Adjust destinations for ELFv2 locals. (ppc_size_one_stub, toc_adjusting_stub_needed): Similarly. (ppc64_elf_size_stubs): Pass local_off to ppc_type_of_stub. Set "other" field. (ppc64_elf_relocate_section): Adjust destination for ELFv2 local calls. gas/ * config/tc-ppc.c (md_pseudo_table): Add .localentry. (ppc_elf_localentry): New function. (ppc_force_relocation): Force relocs on all branches to localenty symbols. (ppc_fix_adjustable): Don't reduce such symbols to section+offset. binutils/ * readelf.c (get_ppc64_symbol_other): New function. (get_symbol_other): Use it for EM_PPC64.	13 years ago
Alan Modra	ee67d69a3f	Add .abiversion related support for ELFv2 Defines bits in ELF e_flags to differentiate ELFv2 objects from ELFv2, adds .abiversion directive to explicitly choose the ABI, and code to check and automatically select ABI. include/elf/ * ppc64.h (EF_PPC64_ABI): Define. bfd/ * elf64-ppc.c (abiversion, set_abiversion): New functions. (ppc64_elf_get_synthetic_symtab): Handle ELFv2 objects without .opd. (struct ppc_link_hash_table): Add opd_abi. (ppc64_elf_check_relocs): Check no .opd with ELFv2. (ppc64_elf_merge_private_bfd_data): New function. (ppc64_elf_print_private_bfd_data): New function. (ppc64_elf_tls_setup): Set htab->opd_abi. (ppc64_elf_size_dynamic_sections): Don't emit OPD related dynamic tags for ELFv2. (ppc_build_one_stub): Use R_PPC64_IRELATIVE for ELFv2 ifunc. (ppc64_elf_finish_dynamic_symbol): Likewise binutils/ * readelf.c (get_machine_flags): Display ABI version for EM_PPC64. gas/ * config/tc-ppc.c: Include elf/ppc64.h. (ppc_abiversion): New variable. (md_pseudo_table): Add .abiversion. (ppc_elf_abiversion, ppc_elf_end): New functions. * config/tc-ppc.h (md_end): Define.	13 years ago
Alan Modra	f9c6b9078c	Report overflow on PowerPC64 @h and @ha relocations. This changes the behaviour of @h and @ha on PowerPC64 to report errors on 32-bit overflow. The motivation for this change is that on PowerPC64, most uses of @h and @ha modifiers and their corresponding relocations are to build up 32-bit offsets. We'd like to know when such offsets overflow. Only rarely do people use @h or @ha with the high 32-bit modifiers to build a 64-bit constant. Those uses will now need to use two new modifiers, @high and @higha, if the constant isn't known at assembly time. For now, we won't report overflow at assembly time.. This also fixes an error when applying some of the HIGHER and HIGHEST relocations. include/elf/ * ppc64.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA, R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA, R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): New. (IS_PPC64_TLS_RELOC): Match new tls relocs. bfd/ * reloc.c (BFD_RELOC_PPC64_ADDR16_HIGH, BFD_RELOC_PPC64_ADDR16_HIGHA, BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA, BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): New. * elf64-ppc.c (ppc64_elf_howto_raw): Add entries for new relocs. Make all _HA and _HI relocs report signed overflow. (ppc64_elf_reloc_type_lookup): Handle new relocs. (must_be_dyn_reloc, ppc64_elf_check_relocs): Likewise. (dec_dynrel_count, ppc64_elf_relocate_section): Likewise. (ppc64_elf_relocate_section): Don't apply 0x8000 adjust to R_PPC64_TPREL16_HIGHER, R_PPC64_TPREL16_HIGHEST, R_PPC64_DTPREL16_HIGHER, and R_PPC64_DTPREL16_HIGHEST. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (SEX16): Don't mask. (REPORT_OVERFLOW_HI): Define as zero. (ppc_elf_suffix): Support @high, @higha, @dtprel@high, @dtprel@higha, @tprel@high, and @tprel@higha modifiers. (md_assemble): Ignore X_unsigned when applying 16-bit insn fields. Add (disabled) code to check @h and @ha reloc overflow for powerpc64. Handle new relocs. (md_apply_fix): Similarly. elfcpp/ * powerpc.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA, R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA, R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): Define. gold/ * powerpc.cc (Target_powerpc::Scan::check_non_pic): Handle new relocs. (Target_powerpc::Scan::global, local): Likewise. (Target_powerpc::Relocate::relocate): Likewise. Check for overflow on all ppc64 @h and @ha relocs.	13 years ago
Pedro Alves	4e22507533	Fix up a couple oddities in GDB's signal names and strings. - The Mach exception/signals escaped the TARGET_ -> GDB_ prefix change done a while ago, but there's no real reason for that. I grepped for TARGET_EXC and fixed all found, which unsurprisingly, means darwin-nat.c needed fixing. I think the change there is as obvious and trivial as it can get, so I'd be quite surprised if this broke anything there somehow. - GDB_SIGNAL_LAST's description string was unnecessarily inconsistent with the enum name. Built on x86_64 Fedora 17. gdb/ 2013-10-22 Pedro Alves <palves@redhat.com> * include/gdb/signals.def (TARGET_EXC_BAD_ACCESS): Rename to GDB_EXC_BAD_ACCESS. (TARGET_EXC_BAD_INSTRUCTION): Rename to GDB_EXC_BAD_INSTRUCTION. (TARGET_EXC_ARITHMETIC): Rename to GDB_EXC_ARITHMETIC. (TARGET_EXC_EMULATION): Rename to GDB_EXC_EMULATION. (TARGET_EXC_SOFTWARE): Rename to GDB_EXC_SOFTWARE. (TARGET_EXC_BREAKPOINT): Rename to GDB_EXC_BREAKPOINT. (GDB_SIGNAL_LAST): Change description string. * common/signals.c (gdb_signal_from_host, do_gdb_signal_to_host): Adjust to signal renaming. * darwin-nat.c (darwin_decode_message): Likewise.	13 years ago
Chao-ying Fu	387a82f124	2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX. (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL. For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +, +\|. For MIPS, update extension character sequences after +. (ASE_MSA): New define. (ASE_MSA64): New define. For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +, +\|. For microMIPS, update extension character sequences after +.	13 years ago
Chao-ying Fu	63b8b2af80	2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> * mips.h (enum): Add Tag_GNU_MIPS_ABI_MSA. (enum): Add Val_GNU_MIPS_ABI_MSA_ANY and Val_GNU_MIPS_ABI_MSA_128.	13 years ago
Sean Keys	0e1c243401	* Removed short_hand field from opcode table and refactored assembler/disassember accordingly. Testsuite checkout OK.	13 years ago
Steve Ellcey	f303dcc05d	2013-09-17 Doug Gilmore <Doug.Gilmore@imgtec.com> * mips.h (EF_MIPS_FP64): New e_flags bit.	13 years ago
Nick Clifton	9aff4b7ac1	PR binutils/15834 Fix typos: --- bfd/bfdio.c \| 2 +- bfd/elf32-spu.c \| 2 +- bfd/elfnn-aarch64.c \| 2 +- binutils/od-xcoff.c \| 2 +- config/tcl.m4 \| 2 +- gas/config/tc-ia64.c \| 2 +- gas/config/tc-sparc.c \| 2 +- gas/config/tc-z80.c \| 12 ++++++------ gas/doc/c-i386.texi \| 6 +++--- gas/doc/c-m32r.texi \| 2 +- gas/testsuite/gas/d10v/instruction_packing.d \| 2 +- gas/testsuite/gas/z80/atend.d \| 2 +- gold/object.h \| 2 +- include/gdb/remote-sim.h \| 2 +- include/opcode/ChangeLog \| 2 +- include/opcode/i960.h \| 2 +- ld/testsuite/ld-mips-elf/mips16-pic-1.inc \| 2 +- opcodes/aarch64-asm.c \| 2 +- opcodes/aarch64-dis.c \| 2 +- opcodes/msp430-dis.c \| 2 +-	13 years ago
DJ Delorie	21290977cb	merge from gcc	13 years ago
Richard Sandiford	e423441da4	include/opcode/ * mips.h: Remove references to "+I" and imm2_expr. gas/ * config/tc-mips.c (imm2_expr): Delete. (md_assemble, match_insn, imm2_expr.X_op, mips_ip): Update accordingly.	13 years ago
Richard Sandiford	5e0dc5bae9	include/opcode/ * mips.h (M_DEXT, M_DINS): Delete. opcodes/ * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases. Use +H rather than +C for the real "dext". * mips-opc.c (mips_builtin_opcodes): Likewise. gas/ * config/tc-mips.c (report_bad_range, report_bad_field): Delete. (macro): Remove M_DEXT and M_DINS handling. gas/testsuite/ * gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS error messages to have the same form as the EXT and INS ones. * gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d, gas/mips/micromips.d, gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect "dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".	13 years ago
Richard Sandiford	0f35dbc4d9	include/opcode/ * mips.h (OP_OPTIONAL_REG): New mips_operand_type. (mips_optional_operand_p): New function. opcodes/ * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros. * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG and OPTIONAL_MAPPED_REG. * mips-opc.c (decode_mips_operand): Likewise. * mips16-opc.c (decode_mips16_operand): Likewise. * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG. gas/ * config/tc-mips.c (operand_reg_mask, match_operand): Handle OP_OPTIONAL_REG. (mips_ip, mips16_ip): Use mips_optional_operand_p to check for optional operands.	13 years ago
Nick Clifton	4046d87a36	* elf32-rl78.c (rl78_elf_merge_private_bfd_data): Complain if G10 flag bits do not match. (rl78_elf_print_private_bfd_data): Describe G10 flag. * readelf.c (get_machine_flags): Handle RL78 G10 flag. * config/tc-rl78.c (elf_flags): New variable. (enum options): Add OPTION_G10. (md_longopts): Add mg10. (md_parse_option): Parse -mg10. (rl78_elf_final_processing): New function. * config/tc-rl78.c (tc_final_processing): Define. * doc/c-rl78.texi: Document -mg10 option. * rl78.c (E_FLAG_RL78_G10): Define. * lib/ld-lib.exp (check_shared_lib_support): Note that the RL78 does not support shared library generation.	13 years ago
DJ Delorie	3c6331b4a5	merge from gcc	13 years ago
Eric Botcazou	d6787ef95c	gas/ * config/tc-sparc.c (sparc_arch_types): Add leon. (sparc_arch): Move sparc4 around and add leon. (sparc_target_format): Document -Aleon. * doc/c-sparc.texi: Likewise. include/ * opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON. opcodes/ * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for bfd_mach_sparc. * sparc-opc.c (MASK_LEON): Define. (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON. (letandleon): New macro. (v9andleon): Likewise. (sparc_opc): Add leon. (umac): Enable for letandleon. (smac): Likewise. (casa): Enable for v9andleon. (cas): Likewise. (casl): Likewise.	13 years ago
Richard Sandiford	14daeee3ae	include/opcode/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips.h: Document new VU0 operand characters. (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types. (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R) (OP_REG_R5900_ACC): New mips_reg_operand_types. (INSN2_VU0_CHANNEL_SUFFIX): New macro. (mips_vu0_channel_mask): Declare. opcodes/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (print_vu0_channel): New function. (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (print_insn_args): Handle '#'. (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX. * mips-opc.c (mips_vu0_channel_mask): New constant. (decode_mips_operand): Handle new VU0 operand types. (VU0, VU0CH): New macros. (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E" for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2. Use "+6" rather than "G" for QMFC2 and QMTC2. gas/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * config/tc-mips.c (MAX_OPERANDS): Bump to 6. (RWARN): Bump to 0x8000000. (RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R) (RTYPE_R5900_ACC): New register types. (RTYPE_MASK): Include them. (R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New macros. (reg_names): Include them. (mips_parse_register_1): New function, split out from... (mips_parse_register): ...here. Add a channels_ptr parameter. Look for VU0 channel suffixes when nonnull. (reg_lookup): Update the call to mips_parse_register. (mips_parse_vu0_channels): New function. (OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types. (mips_operand_token): Add a "channels" field to the union. Extend the comment above "ch" to OT_DOUBLE_CHAR. (mips_parse_base_start): Match -- and ++. Handle channel suffixes. (mips_parse_argument_token): Handle channel suffixes here too. (validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX. Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits. Handle '#' formats. (md_begin): Register $vfN and $vfI registers. (operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (match_vu0_suffix_operand): New function. (match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (macro): Use "+7" rather than "E" for LDQ2 and STQ2. (mips_lookup_insn): New function. (mips_ip): Use it. Allow "+K" operands to be elided at the end of an instruction. Handle '#' sequences. gas/testsuite/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric coprocessor registers. * gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d, gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d, gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests. * gas/mips/mips.exp: Run them.	13 years ago
Richard Sandiford	3ccad066ac	include/opcode/ * mips.h (mips_pcrel_operand): Inherit from mips_int_operand. (mips_int_operand_min, mips_int_operand_max): New functions. (mips_decode_pcrel_operand): Use mips_decode_int_operand. opcodes/ * mips-formats.h (PCREL): Reorder parameters and update the definition to match new mips_pcrel_operand layout. (JUMP, JALX, BRANCH): Update accordingly. * mips16-opc.c (decode_mips16_operand): Likewise. gas/ * config/tc-mips.c (match_int_operand): Use mips_int_operand_min and mips_int_operand_max. (mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED): Delete. (mips16_immed_operand, mips16_immed_in_range_p): New functions. (mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand instead of mips16_immed_operand.	13 years ago
Richard Sandiford	fc76e73056	include/opcode/ * mips.h (mips_decode_reg_operand): New function. (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL) (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4) (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI): New macros. (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D) (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T) (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S) (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z) (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D) (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD) (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG) (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP) (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP) (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other macros to cover the gaps. (INSN2_MOD_SP): Replace with... (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros. (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z) (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y) (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z) (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X): Delete. opcodes/ * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): New macros. (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete. (mips_builtin_opcodes): Use the new position-based read-write flags instead of field-based ones. Use UDI for "udi..." instructions. * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete. (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags. (WR_SP, RD_16): New macros. (RD_SP): Redefine as an INSN2_* flag. (MOD_SP): Redefine in terms of RD_SP and WR_SP. (mips16_opcodes): Use the new position-based read-write flags instead of field-based ones. Use RD_16 for "nop". Move RD_SP to pinfo2 field. * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj) (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D) (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete. (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP. (micromips_opcodes): Use the new position-based read-write flags instead of field-based ones. * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand. (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead of field-based flags. gas/ * config/tc-mips.c (MAX_OPERANDS): New macro. (mips_operand_array): New structure. (mips_operands, mips16_operands, micromips_operands): New arrays. (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map) (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map) (micromips_to_32_reg_q_map): Delete. (insn_operands, insn_opno, insn_extract_operand): New functions. (validate_mips_insn): Take a mips_operand_array as argument and use it to build up a list of operands. Extend to handle INSN_MACRO and MIPS16. (validate_mips16_insn): New function. (validate_micromips_insn): Take a mips_operand_array as argument. Handle INSN_MACRO. (md_begin): Initialize mips_operands, mips16_operands and micromips_operands. Call validate_mips_insn and validate_micromips_insn for macro instructions too. Call validate_mips16_insn for MIPS16 instructions. (insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask): New functions. (gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use them. Handle INSN_UDI. (get_append_method): Use gpr_read_mask.	13 years ago
Richard Sandiford	265459441c	include/opcode/ * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31) (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH) (MIPS16_INSN_COND_BRANCH): Delete. opcodes/ * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags. (WR_SP): Replace with... (MOD_SP): ...this. (mips16_opcodes): Update accordingly. * mips-dis.c (print_insn_mips16): Likewise. gas/ * config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same flags for MIPS16 and non-MIPS16 instructions. (gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block. (gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too. (gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling. (can_swap_branch_p, get_append_method): Use the same flags for MIPS16 and non-MIPS16 instructions. Fix formatting.	13 years ago
H.J. Lu	7e8b059be6	Support Intel MPX gas/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386.c (BND_PREFIX): New. (struct _i386_insn): Add new field bnd_prefix. (add_bnd_prefix): New. (cpu_arch): Add MPX. (i386_operand_type): Add regbnd. (md_assemble): Handle BND prefixes. (parse_insn): Likewise. (output_branch): Likewise. (output_jump): Likewise. (build_modrm_byte): Handle regbnd. (OPTION_MADD_BND_PREFIX): New. (md_longopts): Add entry for 'madd-bnd-prefix'. (md_parse_option): Handle madd-bnd-prefix option. (md_show_usage): Add description for madd-bnd-prefix option. * doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix. gas/testsuite/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/i386/mpx-add-bnd-prefix.s: New. * gas/i386/mpx-add-bnd-prefix.d: New. * gas/i386/mpx-inval-1.l: New. * gas/i386/mpx-inval-1.s: New. * gas/i386/mpx.d: New. * gas/i386/mpx.s: New. * gas/i386/x86-64-mpx-add-bnd-prefix.d: New. * gas/i386/x86-64-mpx-add-bnd-prefix.s: New. * gas/i386/x86-64-mpx-addr32.d: New. * gas/i386/x86-64-mpx-addr32.s: New. * gas/i386/x86-64-mpx-inval-1.l: New. * gas/i386/x86-64-mpx-inval-1.s: New. * gas/i386/x86-64-mpx-inval-2.l: New. * gas/i386/x86-64-mpx-inval-2.s: New. * gas/i386/x86-64-mpx.d: New. * gas/i386/x86-64-mpx.s: New. * gas/i386/nops.d: Adjust to MPX changes. * gas/i386/nops.s: Likewise. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-nops.s: Likewise. * gas/i386/ilp32/x86-64-nops.d: Likewise. * gas/i386/i386.exp: Run new MPX tests. include/opcode/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386.h (BND_PREFIX_OPCODE): New. opcodes/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis.c (BND_Fixup): New. (Ebnd): New. (Ev_bnd): New. (Gbnd): New. (BND): New. (v_bnd_mode): New. (bnd_mode): New. (MOD enum): Add new entries. (PREFIX enum): Likewise. (dis tables): Replace XX with BND for near branch and call instructions. (prefix_table): Add new entries. (mod_table): Likewise. (names_bnd): New. (intel_names_bnd): New. (att_names_bnd): New. (BND_PREFIX): New. (prefix_name): Handle BND_PREFIX. (print_insn): Initialize names_bnd. (intel_operand_size): Handle new modes. (OP_E_register): Likewise. (OP_E_memory): Likewise. (OP_G): Likewise. * i386-gen.c (cpu_flag_init): Add CpuMPX. (cpu_flags): Add CpuMPX. (operand_type_init): Add RegBND. (opcode_modifiers): Add BNDPrefixOk. (operand_types): Add RegBND. * i386-init.h: Regenerate. * i386-opc.h (CpuMPX): New. (CpuUnused): Comment out. (i386_cpu_flags): Add cpumpx. (BNDPrefixOk): New. (i386_opcode_modifier): Add bndprefixok. (RegBND): New. (i386_operand_type): Add regbnd. * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets. Add MPX instructions and bnd prefix. * i386-reg.tbl: Add bnd0-bnd3 registers. * i386-tbl.h: Regenerate.	13 years ago
Nick Clifton	eb1d270862	PR binutils/15728 * basic-ops.h: (SUBWORDSIQI) Make declaration static. * (SUBWORDSIHI): Likewise. * (SUBWORDDIQI): Likewise. * (SUBWORDDIHI): Likewise. * (SUBWORDDISI): Likewise.	13 years ago
Maciej W. Rozycki	d929bc19b9	include/elf/ * mips.h (Tag_GNU_MIPS_ABI_FP): Remove comment. (Val_GNU_MIPS_ABI_FP_ANY, Val_GNU_MIPS_ABI_FP_DOUBLE, Val_GNU_MIPS_ABI_FP_SINGLE, Val_GNU_MIPS_ABI_FP_SOFT, Val_GNU_MIPS_ABI_FP_64): New enum. bfd/ * elfxx-mips.c (mips_elf_merge_obj_attributes): Replace hardcoded magic numbers with enum values. binutils/ * readelf.c (display_mips_gnu_attribute): Replace hardcoded magic numbers with enum values. gdb/ * mips-tdep.c (mips_gdbarch_init): Replace hardcoded magic numbers with enum values.	13 years ago
Richard Sandiford	c3c0747817	include/opcode/ * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and OP_SAVE_RESTORE_LIST. (decode_mips16_operand): Declare. opcodes/ * mips16-opc.c: Include mips-formats.h. (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New static arrays. (decode_mips16_operand): New function. * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete. (print_insn_arg): Handle OP_ENTRY_EXIT list. Abort for OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Change interface. Use mips_operand structures. Delete GET_OP_S. Move GET_OP definition to... (print_insn_mips16): ...here. Call init_print_arg_state. Update the call to print_mips16_insn_arg.	13 years ago
Richard Sandiford	ab90248154	include/opcode/ * mips.h (mips_operand_type, mips_reg_operand_type): New enums. (mips_operand, mips_int_operand, mips_mapped_int_operand) (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand) (mips_pcrel_operand): New structures. (mips_insert_operand, mips_extract_operand, mips_signed_operand) (mips_decode_int_operand, mips_decode_pcrel_operand): New functions. (decode_mips_operand, decode_micromips_operand): Declare. opcodes/ * mips-formats.h: New file. * mips-opc.c: Include mips-formats.h. (reg_0_map): New static array. (decode_mips_operand): New function. * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h. (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map) (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map) (int_c_map): New static arrays. (decode_micromips_operand): New function. * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map) (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map) (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2) (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map) (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map) (micromips_imm_b_map, micromips_imm_c_map): Delete. (print_reg): New function. (mips_print_arg_state): New structure. (init_print_arg_state, print_insn_arg): New functions. (print_insn_args): Change interface and use mips_operand structures. Delete GET_OP_S. Move GET_OP definition to... (print_insn_mips): ...here. Update the call to print_insn_args. (print_insn_micromips): Use print_insn_args. gas/ * config/tc-mips.c (validate_mips_insn): Move further up file. Add insn_bits and decode_operand arguments. Use the mips_operand fields to work out which bits an operand occupies. Detect double definitions. (validate_micromips_insn): Move further up file. Call into validate_mips_insn.	13 years ago
Richard Sandiford	cc537e567a	include/opcode/ * mips.h: Document MIPS16 "I" opcode. opcodes/ * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands in macros. gas/ * config/tc-mips.c (mips16_ip): Handle "I".	13 years ago
Maciej W. Rozycki	ba92f88752	include/elf/ * mips.h (EF_MIPS_NAN2008): New macro. bfd/ * elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Handle EF_MIPS_NAN2008. (_bfd_mips_elf_print_private_bfd_data): Likewise. binutils/ * readelf.c (get_machine_flags): Handle EF_MIPS_NAN2008. gas/ * config/tc-mips.c (mips_flag_nan2008): New variable. (options): Add OPTION_NAN enum value. (md_longopts): Handle it. (md_parse_option): Likewise. (s_nan): New function. (mips_elf_final_processing): Handle EF_MIPS_NAN2008. (md_show_usage): Add -mnan. * doc/as.texinfo (Overview): Add -mnan. * doc/c-mips.texi (MIPS Opts): Document -mnan. (MIPS NaN Encodings): New node. Document .nan directive. (MIPS-Dependent): List the new node. gas/testsuite/ * gas/mips/nan-2008-1.d: New test. * gas/mips/nan-2008-2.d: New test. * gas/mips/nan-2008-3.d: New test. * gas/mips/nan-2008-4.d: New test. * gas/mips/nan-legacy-1.d: New test. * gas/mips/nan-legacy-2.d: New test. * gas/mips/nan-legacy-3.d: New test. * gas/mips/nan-legacy-4.d: New test. * gas/mips/nan-legacy-5.d: New test. * gas/mips/nan-error-1.l: New list test. * gas/mips/nan-error-2.l: New list test. * gas/mips/nan-2008-override.s: New test source. * gas/mips/nan-2008.s: New test source. * gas/mips/nan-legacy-override.s: New test source. * gas/mips/nan-legacy.s: New test source. * gas/mips/nan-error-1.s: New test source. * gas/mips/nan-error-2.s: New test source. * gas/mips/mips.exp: Run the new tests. ld/testsuite/ * ld-mips-elf/nan-2008.d: New test. * ld-mips-elf/nan-legacy.d: New test. * ld-mips-elf/nan-mixed-1.d: New test. * ld-mips-elf/nan-mixed-2.d: New test. * ld-mips-elf/nan-2008.s: New test source. * ld-mips-elf/nan-legacy.s: New test source.	13 years ago
Tristan Gingold	868d184013	include/coff/ 2013-07-10 Tristan Gingold <gingold@adacore.com> * rs6000.h (external_core_dumpx): New structure. (external_ld_info32): Ditto. binutils/ 2013-07-10 Tristan Gingold <gingold@adacore.com> * od-xcoff.c (OPT_LDINFO): Define. (options): Add ldinfo. (xcoff_help): Mention ldinfo. (xcoff_dump): Rename to ... (xcoff_dump_obj): ... this. Add a break. (dump_dumpx_core): New function. (xcoff_dump_core): Likewise. (xcoff_dump): Likewise. * doc/binutils.texi (objdump): Mention ldinfo.	13 years ago
Tristan Gingold	ee4dff511c	2013-07-08 Tristan Gingold <gingold@adacore.com> * ia64.h (STB_VMS_WEAK, STB_VMS_SYSTEM): Add.	13 years ago
Richard Sandiford	f2ae14a1cc	include/opcode/ * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): Rename to... (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) (M_USD_AB): ...these. opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD and SD A(B) macros up. * micromips-opc.c (micromips_opcodes): Likewise. gas/ * config/tc-mips.c (gprel16_reloc_p): New function. (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are BFD_RELOC_UNUSED. (offset_high_part, small_offset_p): New functions. (nacro): Use them. Remove _OB and _DOB cases. For single- register load and store macros, handle the 16-bit offset case first. If a 16-bit offset is not suitable for the instruction we're generating, load it into the temporary register using ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the M_L_DAB code once the address has been constructed. For double load and store macros, again handle the 16-bit offset case first. If the second register cannot be accessed from the same high part as the first, load it into AT using ADDRESS_ADDI_INSN. Fix the handling of LD in cases where the first register is the same as the base. Also handle the case where the offset is not 16 bits and the second register cannot be accessed from the same high part as the first. For unaligned loads and stores, fuse the offbits == 12 and old "ab" handling. Apply this handling whenever the second offset needs a different high part from the first. Construct the offset using ADDRESS_ADDI_INSN where possible, for offbits == 16 as well as offbits == 12. Use offset_reloc when constructing the individual loads and stores. (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc and offset_reloc before matching against a particular opcode. Handle elided 'A' constants. Allow 'A' constants to use relocation operators. gas/testsuite/ * gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for truncated constants. * gas/mips/ldstla-32-shared.d: Likewise. * gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding 16-bit constants to the base. * gas/mips/micromips@mcu.d: Likewise. * gas/mips/micromips@cache.d: Likewise. * gas/mips/micromips@pref.d: Likewise. * gas/mips/micromips.d, gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise. Allow the full 16-bit offset range to be used for SB, LB and LBU in USH and ULH sequences. Fix the expected output for LD and SD when the two LW and SW offsets need different high parts. * gas/mips/eva.s: Test PREFE with relocation operators. * gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit constants. Update after eva.s change. * gas/mips/micromips@eva.d: Likewise. * gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s, gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d, gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s, gas/mips/ulh-reloc.d: New tests. * gas/mips/mips.exp: Run them.	13 years ago
Richard Sandiford	5c324c169b	include/opcode/ * mips.h: Remove documentation of "[" and "]". Update documentation of "k" and the MDMX formats. opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400 MDMX-like instructions. * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when printing "Q" operands for INSN_5400 instructions. gas/ * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling. (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions. Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions. gas/testsuite/ * gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test. * gas/mips/mips.exp: Run it.	13 years ago
Richard Sandiford	23e69e47b4	include/opcode/ * mips.h: Update documentation of "+s" and "+S". opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and "+S" for "cins". * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments. Combine cases. gas/ * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p". Require the msb to be <= 31 for "+s". Check that the size is <= 31 for both "+s" and "+S".	13 years ago
Richard Sandiford	27c5c572c9	include/opcode/ * mips.h: Document "+i". opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for "jalx". * mips16-opc.c (mips16_opcodes): Likewise. * micromips-opc.c (micromips_opcodes): Likewise. * mips-dis.c (print_insn_args, print_mips16_insn_arg) (print_insn_mips16): Handle "+i". (print_insn_micromips): Likewise. Conditionally preserve the ISA bit for "a" but not for "+i". gas/ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn): (mips_ip, mips16_ip): Handle "+i".	13 years ago
Richard Sandiford	e76ff5abe3	include/opcode/ * mips.h: Remove "mi" documentation. Update "mh" documentation. (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): Delete. (INSN2_WRITE_GPR_MHI): Rename to... (INSN2_WRITE_GPR_MH): ...this. opcodes/ * micromips-opc.c (WR_mhi): Rename to.. (WR_mh): ...this. (micromips_opcodes): Update "movep" entry accordingly. Replace "mh,mi" with "mh". * mips-dis.c (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (print_micromips_insn): Remove "mi" case. Print both registers in the pair for "mh". gas/ * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete. (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (mips_lookup_reg_pair): New function. (gpr_write_mask, macro): Adjust after above renaming. (validate_micromips_insn): Remove "mi" handling. (mips_ip): Likewise. Parse both registers in a pair for "mh".	13 years ago
Richard Sandiford	fa7616a4c7	include/opcode/ * mips.h: Remove documentation of "+D" and "+T". opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries. * micromips-opc.c (micromips_opcodes): Likewise. * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D" and "+T" handling. Check for a "0" suffix when deciding whether to use coprocessor 0 names. In that case, also check for ",H" selectors. gas/ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn) (mips_ip): Remove "+D" and "+T" handling. gas/testsuite/ * gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names for LWC0 and SWC0.	13 years ago
Andreas Krebbel	fb798c50b2	2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> opcodes/ * s390-opc.c (J12_12, J24_24): New macros. (INSTR_MII_UPI): Rename to INSTR_MII_UPP. (MASK_MII_UPI): Rename to MASK_MII_UPP. * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction. include/elf/ * s390.h: Add new relocs R_390_PC12DBL, R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL. gas/testsuite/ * gas/s390/zarch-zEC12.s: Change bprp second operand and add variants requiring relocations. * gas/s390/zarch-zEC12.d: Likewise. gas/ * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new relocs. bfd/ * elf32-s390.c: Add new relocation definitions R_390_PC12DBL, R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL. (elf_s390_reloc_type_lookup, elf_s390_check_relocs) (elf_s390_gc_sweep_hook, elf_s390_relocate_section): Support new relocations. * elf64-s390.c: See elf32-s390.c * bfd-in2.h: Add new relocs to enum bfd_reloc_code_real. * libbfd.h: Add new reloc strings.	13 years ago
Tristan Gingold	9d3056cd1d	2013-07-02 Tristan Gingold <gingold@adacore.com> * internal.h (C_STTLS, C_GTLS): Define. * xcoff.h (XMC_TL, XMC_TU, XMC_TE): Define.	13 years ago
Yufeng Zhang	a6bb11b2df	[AArch64, ILP32] 3/6 Support for ELF32 relocs and refactor reloc handling bfd/ * bfd-in2.h: Re-generated. * elfnn-aarch64.c (HOWTO64, HOWTO32): New define. (IS_AARCH64_TLS_RELOC): Change to be based on the bfd reloc enumerators. (IS_AARCH64_TLSDESC_RELOC): Likewise. (PG, PG_OFFSET): Cast literal to bfd_vma. (elf64_aarch64_howto_table): Removed. (elf64_aarch64_howto_dynrelocs): Removed. (elf64_aarch64_tls_howto_table): Removed. (elf64_aarch64_tlsdesc_howto_table): Removed. (elfNN_aarch64_howto_table): New table to host all howto entires.. (R_AARCH64_): Replaced by AARCH64_R () and AARCH64_R_STR (). (elfNN_aarch64_bfd_reloc_from_howto): New function. (elfNN_aarch64_bfd_reloc_from_type): Ditto. (struct elf_aarch64_reloc_map): New. (elf_aarch64_reloc_map): New table. (elfNN_aarch64_howto_from_bfd_reloc): New function. (elfNN_aarch64_howto_from_type): Update to look up the new table elfNN_aarch64_howto_table. (struct elf64_aarch64_reloc_map): Remove. (elf64_aarch64_reloc_map): Remove. (elfNN_aarch64_reloc_type_lookup): Change to call elfNN_aarch64_howto_from_bfd_reloc. (elfNN_aarch64_reloc_name_lookup): Change to look up the new table elfNN_aarch64_howto_table. (aarch64_resolve_relocation): Refactor to switch on the bfd reloc enumerators. (bfd_elf_aarch64_put_addend): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (aarch64_tls_transition_without_check): Likewise. (aarch64_reloc_got_type): Likewise. (aarch64_can_relax_tls): Likewise. (aarch64_tls_transition): Likewise. (elfNN_aarch64_tls_relax): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. (aarch64_tls_transition): Change to return a bfd reloc enumerator. libbfd.h: Re-generated. * reloc.c: Re-order the AArch64 bfd reloc enumerators. (BFD_RELOC_AARCH64_RELOC_START) (BFD_RELOC_AARCH64_RELOC_END) (BFD_RELOC_AARCH64_LD_GOT_LO12_NC) (BFD_RELOC_AARCH64_LD32_GOT_LO12_NC) (BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC) (BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC) (BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC) (BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC) (BFD_RELOC_AARCH64_IRELATIVE): New relocs. gas/ * config/tc-aarch64.c (reloc_table): Replace BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC. (md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC, BFD_RELOC_AARCH64_LD32_GOT_LO12_NC, BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC, BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC, BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC. (aarch64_force_relocation): Likewise. gas/testsuite/ * gas/aarch64/ilp32-basic.d: New file. * gas/aarch64/ilp32-basic.s: New file. include/elf/ * aarch64.h: Add ELF32 reloc codes and remove fake ELF64 ones. (R_AARCH64_IRELATIVE): New reloc.	13 years ago
Richard Sandiford	18870af79b	include/opcode/ * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT. Use "source" rather than "destination" for microMIPS "G". gas/ * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.	13 years ago
Maciej W. Rozycki	833794fc12	bfd/ * elfxx-mips.h (_bfd_mips_elf_insn32): New prototype. * elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member. (STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros. (MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise. (MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise. (micromips_insn32_o32_exec_plt0_entry): New variable. (micromips_insn32_o32_exec_plt_entry): Likewise. (_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode. (mips_elf_estimate_stub_size): Likewise. (_bfd_mips_elf_size_dynamic_sections): Likewise. (_bfd_mips_elf_finish_dynamic_symbol): Likewise. (mips_finish_exec_plt): Likewise. (_bfd_mips_elf_relax_section): Likewise. (_bfd_mips_elf_insn32): New function. (_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT. gas/ * config/tc-mips.c (mips_set_options): Add insn32 member. (mips_opts): Initialize it. (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode. (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values. (md_longopts): Add "minsn32" and "mno-insn32" options. (is_size_valid): Handle insn32 mode. (md_assemble): Pass instruction string down to macro. (brk_fmt): Add second dimension and insn32 mode initializers. (mfhl_fmt): Likewise. (BRK_FMT, MFHL_FMT): Handle insn32 mode. (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding. (macro_build_jalr, move_register): Handle insn32 mode. (macro_build_branch_rs): Likewise. (macro): Handle insn32 mode. <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases. (mips_ip): Handle insn32 mode. (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32. (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops. (mips_handle_align): Handle insn32 mode. (md_show_usage): Add -minsn32 and -mno-insn32. * doc/as.texinfo (Target MIPS options): Add -minsn32 and -mno-insn32 options. (-minsn32, -mno-insn32): New options. * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32 options. (MIPS assembly options): New node. Document .set insn32 and .set noinsn32. (MIPS-Dependent): List the new node. gas/testsuite/ * gas/mips/micromips-insn32.d: New test. * gas/mips/micromips-noinsn32.d: Likewise. * gas/mips/micromips.l: Rename to... * gas/mips/micromips-warn.l: ... this. * gas/mips/micromips.d: Update accordingly. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips.l: New list test. * gas/mips/micromips.s: Add conditionals. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum values. ld/ * emultempl/mipself.em (insn32): New variable. (mips_create_output_section_statements): Handle insn32 mode. (PARSE_AND_LIST_PROLOGUE): New macro. (PARSE_AND_LIST_LONGOPTS): Likewise. (PARSE_AND_LIST_OPTIONS): Likewise. * gen-doc.texi: Set MIPS. * ld.texinfo: Likewise. (Options specific to MIPS targets): New section. (ld and MIPS family): New node. (Top, Machine Dependent): List the new node. opcodes/ * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc" and "movep" macros.	13 years ago
Maciej W. Rozycki	1bbce13264	bfd/ * elfxx-mips.h (_bfd_mips_elf_get_synthetic_symtab): New prototype. * elf32-mips.c (elf_backend_plt_sym_val): Remove macro. (bfd_elf32_get_synthetic_symtab): New macro. * elfxx-mips.c (plt_entry): New structure. (mips_elf_link_hash_entry): Add use_plt_entry member. (mips_elf_link_hash_table): Rename plt_entry_size member to plt_mips_entry_size. Add plt_comp_entry_size, plt_mips_offset, plt_comp_offset, plt_got_index entries and plt_header_is_comp members. (STUB_LW_MICROMIPS, STUB_MOVE_MICROMIPS): New macros. (STUB_LUI_MICROMIPS, STUB_JALR_MICROMIPS): Likewise. (STUB_ORI_MICROMIPS, STUB_LI16U_MICROMIPS): Likewise. (STUB_LI16S_MICROMIPS): Likewise. (MICROMIPS_FUNCTION_STUB_NORMAL_SIZE): Likewise. (MICROMIPS_FUNCTION_STUB_BIG_SIZE): Likewise. (micromips_o32_exec_plt0_entry): New variable. (mips16_o32_exec_plt_entry): Likewise. (micromips_o32_exec_plt_entry): Likewise. (mips_elf_link_hash_newfunc): Initialize use_plt_entry. (mips_elf_output_extsym): Update to use gotplt_union's plist member rather than offset. (mips_elf_gotplt_index): Likewise. Remove the VxWorks restriction. Use MIPS_ELF_GOT_SIZE to calculate GOT address. (mips_elf_count_got_symbols): Update to use gotplt_union's plist member rather than offset. (mips_elf_calculate_relocation): Handle MIPS16/microMIPS PLT entries. (_bfd_mips_elf_create_dynamic_sections): Don't set PLT sizes here. (mips_elf_make_plt_record): New function. (_bfd_mips_elf_check_relocs): Update comment. Record occurences of JAL relocations that might need a PLT entry. (_bfd_mips_elf_adjust_dynamic_symbol): Update to use gotplt_union's plist member rather than offset. Set individual PLT entry sizes here. Handle MIPS16/microMIPS PLT entries. Don't set the symbol's value in the symbol table for PLT references here. Don't set the PLT or PLT GOT section sizes here. (mips_elf_estimate_stub_size): Handle microMIPS stubs. (mips_elf_allocate_lazy_stub): Likewise. (mips_elf_lay_out_lazy_stubs): Likewise. Define a _MIPS_STUBS_ magic symbol. (mips_elf_set_plt_sym_value): New function. (_bfd_mips_elf_size_dynamic_sections): Set PLT header size and PLT and PLT GOT section sizes here. Set the symbol values in the symbol table for PLT references here. Handle microMIPS annotation of the _PROCEDURE_LINKAGE_TABLE_ magic symbol. (_bfd_mips_elf_finish_dynamic_symbol): Update to use gotplt_union's plist member rather than offset. Handle MIPS16/microMIPS PLT entries. Handle microMIPS stubs. (_bfd_mips_vxworks_finish_dynamic_symbol): Update to use gotplt_union's plist member rather than offset. Use MIPS_ELF_GOT_SIZE to calculate GOT address. (mips_finish_exec_plt): Handle microMIPS PLT. Return status. (_bfd_mips_elf_finish_dynamic_sections): Handle result from mips_finish_exec_plt. (_bfd_mips_elf_link_hash_table_create): Update to use gotplt_union's plist member rather than offset. (_bfd_mips_elf_get_synthetic_symtab): New function. include/elf/ * mips.h (ELF_ST_IS_MIPS_PLT): Respect STO_MIPS16 setting. (ELF_ST_SET_MIPS_PLT): Likewise. gdb/ * mips-tdep.c (mips_elf_make_msymbol_special): Handle MIPS16 and microMIPS synthetic symbols. ld/ * emulparams/elf32btsmip.sh: Arrange for .got.plt to be placed as close to .plt as possible. * scripttempl/elf.sc: Handle $INITIAL_READWRITE_SECTIONS and $PLT_NEXT_DATA variables. ld/testsuite/ * ld-mips-elf/jalx-2.dd: Update for microMIPS PLT support. * ld-mips-elf/pic-and-nonpic-3a.dd: Update for the _MIPS_STUBS_ magic symbol. * ld-mips-elf/pic-and-nonpic-3b.dd: Likewise. * ld-mips-elf/pic-and-nonpic-6-n32.dd: Likewise. * ld-mips-elf/pic-and-nonpic-6-n64.dd: Likewise. * ld-mips-elf/pic-and-nonpic-6-o32.dd: Likewise. * ld-mips-elf/stub-dynsym-1-10000.d: Likewise. * ld-mips-elf/stub-dynsym-1-2fe80.d: Likewise. * ld-mips-elf/stub-dynsym-1-7fff.d: Likewise. * ld-mips-elf/stub-dynsym-1-8000.d: Likewise. * ld-mips-elf/stub-dynsym-1-fff0.d: Likewise. * ld-mips-elf/tlslib-o32.d: Likewise. opcodes/ * mips-dis.c (is_mips16_plt_tail): New function. (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address word. (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.	13 years ago
Richard Sandiford	c3678916c6	include/opcode/ * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS. gas/ * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.	13 years ago
Nick Clifton	34c911a458	* msp430-decode.opc: New. * msp430-decode.c: New/generated. * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c. (MAINTAINER_CLEANFILES): Likewise. Add rule to build msp430-decode.c frommsp430decode.opc using the opc2c program. * Makefile.in: Regenerate. * configure.in: Add msp430-decode.lo to msp430 architecture files. * configure: Regenerate. * msp430-decode.h: New.	13 years ago
Will Newton	8847944f8c	aarch64: Revert AArch64 ifunc changes. The AArch64 ifunc patch introduced a regression caused by incorrect PLT layout. Revert it until a fix is verified. bfd/ChangeLog: 2013-06-19 Will Newton <will.newton@linaro.org> * configure: Regenerated. * configure.in: Remove aarch64 dependency on elf-ifunc.c. * elf64-aarch64.c: Remove objalloc.h include. (elf64_aarch64_howto_dynrelocs): Remove R_AARCH64_IRELATIVE howto. (struct elf64_aarch64_link_hash_table): Remove ifunc related members. (elf_aarch64_local_htab_hash): Remove function. (elf_aarch64_local_htab_eq): Remove function. (elf_aarch64_get_local_sym_hash): Remove function. (elf64_aarch64_link_hash_table_create): Remove local hash table initialization. (elf64_aarch64_final_link_relocate): Remove sym argument and handling of ifunc symbols. (elf64_aarch64_relocate_section): Don't pass sym argument to elf64_aarch64_final_link_relocate. (elf64_aarch64_gc_sweep_hook): Remove handling of ifunc symbols. (elf64_aarch64_adjust_dynamic_symbol): Likewise. (elf64_aarch64_check_relocs): Likewise. (elf64_aarch64_post_process_headers): Remove call to _bfd_elf_set_osabi. (elf64_aarch64_is_function_type): New function. (elf64_aarch64_allocate_dynrelocs): Remove handling of ifunc symbols. (elf_aarch64_allocate_local_dynrelocs): Remove function. (elf64_aarch64_size_dynamic_sections): Remove call to elf_aarch64_allocate_local_dynrelocs. (elf64_aarch64_create_small_pltn_entry): Remove info argument. Remove creation of R_AARCH64_IRELATIVE dynamic relocs. (elf64_aarch64_finish_dynamic_symbol): Remove handling of ifunc symbols. (elf_aarch64_finish_local_dynamic_symbol): Remove function. (elf64_aarch64_finish_dynamic_sections): Remove call to elf_aarch64_finish_local_dynamic_symbol. (elf64_aarch64_add_symbol_hook): Remove function. include/elf/ChangeLog: 2013-06-19 Will Newton <will.newton@linaro.org> * aarch64.h: Remove R_AARCH64_IRELATIVE. ld/ChangeLog: 2013-06-19 Will Newton <will.newton@linaro.org> * emulparams/aarch64elf.sh: Remove IREL_IN_PLT. ld/testsuite/ChangeLog: 2013-06-19 Will Newton <will.newton@linaro.org> * ld-aarch64/aarch64-elf.exp: Remove ifunc tests. * ld-ifunc/ifunc.exp: Disable ifunc tests on AArch64. * ld-aarch64/ifunc-1-local.d: Remove. * ld-aarch64/ifunc-1-local.s: Likewise. * ld-aarch64/ifunc-1.d: Likewise. * ld-aarch64/ifunc-1.s: Likewise. * ld-aarch64/ifunc-10.d: Likewise. * ld-aarch64/ifunc-10.s: Likewise. * ld-aarch64/ifunc-11.d: Likewise. * ld-aarch64/ifunc-11.s: Likewise. * ld-aarch64/ifunc-12.d: Likewise. * ld-aarch64/ifunc-12.s: Likewise. * ld-aarch64/ifunc-13.d: Likewise. * ld-aarch64/ifunc-13a.s: Likewise. * ld-aarch64/ifunc-13b.s: Likewise. * ld-aarch64/ifunc-14a.d: Likewise. * ld-aarch64/ifunc-14a.s: Likewise. * ld-aarch64/ifunc-14b.d: Likewise. * ld-aarch64/ifunc-14b.s: Likewise. * ld-aarch64/ifunc-14c.d: Likewise. * ld-aarch64/ifunc-14c.s: Likewise. * ld-aarch64/ifunc-14d.d: Likewise. * ld-aarch64/ifunc-14e.d: Likewise. * ld-aarch64/ifunc-14f.d: Likewise. * ld-aarch64/ifunc-15.d: Likewise. * ld-aarch64/ifunc-15.s: Likewise. * ld-aarch64/ifunc-16.d: Likewise. * ld-aarch64/ifunc-16.s: Likewise. * ld-aarch64/ifunc-17a.d: Likewise. * ld-aarch64/ifunc-17a.s: Likewise. * ld-aarch64/ifunc-17b.d: Likewise. * ld-aarch64/ifunc-17b.s: Likewise. * ld-aarch64/ifunc-18a.d: Likewise. * ld-aarch64/ifunc-18a.s: Likewise. * ld-aarch64/ifunc-18b.d: Likewise. * ld-aarch64/ifunc-18b.s: Likewise. * ld-aarch64/ifunc-19a.d: Likewise. * ld-aarch64/ifunc-19a.s: Likewise. * ld-aarch64/ifunc-19b.d: Likewise. * ld-aarch64/ifunc-19b.s: Likewise. * ld-aarch64/ifunc-2-local.d: Likewise. * ld-aarch64/ifunc-2-local.s: Likewise. * ld-aarch64/ifunc-2.d: Likewise. * ld-aarch64/ifunc-2.s: Likewise. * ld-aarch64/ifunc-20.d: Likewise. * ld-aarch64/ifunc-20.s: Likewise. * ld-aarch64/ifunc-3.s: Likewise. * ld-aarch64/ifunc-3a.d: Likewise. * ld-aarch64/ifunc-3b.d: Likewise. * ld-aarch64/ifunc-4.d: Likewise. * ld-aarch64/ifunc-4.s: Likewise. * ld-aarch64/ifunc-4a.d: Likewise. * ld-aarch64/ifunc-5-local.s: Likewise. * ld-aarch64/ifunc-5.s: Likewise. * ld-aarch64/ifunc-5a-local.d: Likewise. * ld-aarch64/ifunc-5a.d: Likewise. * ld-aarch64/ifunc-5b-local.d: Likewise. * ld-aarch64/ifunc-5b.d: Likewise. * ld-aarch64/ifunc-5r-local.d: Likewise. * ld-aarch64/ifunc-6.s: Likewise. * ld-aarch64/ifunc-6a.d: Likewise. * ld-aarch64/ifunc-6b.d: Likewise. * ld-aarch64/ifunc-7.s: Likewise. * ld-aarch64/ifunc-7a.d: Likewise. * ld-aarch64/ifunc-7b.d: Likewise. * ld-aarch64/ifunc-7c.d: Likewise. * ld-aarch64/ifunc-8.d: Likewise. * ld-aarch64/ifunc-8a.s: Likewise. * ld-aarch64/ifunc-8b.s: Likewise. * ld-aarch64/ifunc-9.d: Likewise. * ld-aarch64/ifunc-9.s: Likewise.	13 years ago
Catherine Moore	7f3c40729d	2013-06-17 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Chao-Ying Fu <fu@mips.com> gas/testsuite/ * gas/mips/mips.exp: Run new tests. * gas/mips/eva.d: New. * gas/mips/eva.s: New. * gas/mips/micromips@eva.d: New. gas/ * config/tc-mips.c (mips_set_options): Add ase_eva. (mips_set_options mips_opts): Add ase_eva. (file_ase_eva): Declare. (ISA_SUPPORTS_EVA_ASE): Define. (IS_SEXT_9BIT_NUM): Define. (MIPS_CPU_ASE_EVA): Define. (is_opcode_valid): Add support for ase_eva. (macro_build): Likewise. (macro): Likewise. (validate_mips_insn): Likewise. (validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_EVA and OPTION_NO_EVA. (md_longopts): Add -meva and -mno-eva. (md_parse_option): Process new options. (mips_after_parse_args): Check for valid EVA combinations. (s_mipsset): Likewise. include/ * opcode/mips.h (OP_SH_EVAOFFSET): Define. (OP_MASK_EVAOFFSET): Define. (INSN_ASE_MASK): Delete. (ASE_EVA): Define. (M_CACHEE_AB, M_CACHEE_OB): New. (M_LBE_OB, M_LBE_AB): New. (M_LBUE_OB, M_LBUE_AB): New. (M_LHE_OB, M_LHE_AB): New. (M_LHUE_OB, M_LHUE_AB): New. (M_LLE_AB, M_LLE_OB): New. (M_LWE_OB, M_LWE_AB): New. (M_LWLE_AB, M_LWLE_OB): New. (M_LWRE_AB, M_LWRE_OB): New. (M_PREFE_AB, M_PREFE_OB): New. (M_SCE_AB, M_SCE_OB): New. (M_SBE_OB, M_SBE_AB): New. (M_SHE_OB, M_SHE_AB): New. (M_SWE_OB, M_SWE_AB): New. (M_SWLE_AB, M_SWLE_OB): New. (M_SWRE_AB, M_SWRE_OB): New. (MICROMIPSOP_SH_EVAOFFSET): Define. (MICROMIPSOP_MASK_EVAOFFSET): Define. opcodes/ * micromips-opc.c (EVA): Define. (TLBINV): Define. (micromips_opcodes): Add EVA opcodes. * mips-dis.c (mips_arch_choices): Update for ASE_EVA. (print_insn_args): Handle EVA offsets. (print_insn_micromips): Likewise. * mips-opc.c (EVA): Define. (TLBINV): Define. (mips_builtin_opcodes): Add EVA opcodes.	13 years ago
Sandra Loosemore	0c8fe7cfe2	2013-06-12 Sandra Loosemore <sandra@codesourcery.com> include/opcode/ * nios2.h (OP_MATCH_ERET): Correct eret encoding. gas/testsuite/ * gas/nios2/tret.d: Correct eret encoding.	13 years ago
Richard Sandiford	d301a56b40	gas/ 2013-06-08 Catherine Moore <clm@codesourcery.com> * config/tc-mips.c (is_opcode_valid): Build ASE mask. (is_opcode_valid_16): Pass ase value to opcode_is_member. (append_insn): Change INSN_xxxx to ASE_xxxx. include/ 2013-06-08 Catherine Moore <clm@codesourcery.com> * opcode/mips.h (mips_opcode): Add ase field. (INSN_ASE_MASK): Delete. (INSN_DSP): Rename to ASE_DSP. Provide new value. (INSN_DSPR2): Rename to ASE_DSPR2. Provide new value. (INSN_MCU): Rename to ASE_MCU. Provide new value. (INSN_MDMX): Rename to ASE_MDMX. Provide new value. (INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value. (INSN_MT): Rename to ASE_MT. Provide new value. (INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value. (INSN_VIRT): Rename to ASE_VIRT. Provide new value. (INSN_VIRT64): Rename to ASE_VIRT64. Provide new value. (opcode_is_member): Add ase argument. Check ase. opcodes/ 2013-06-08 Catherine Moore <clm@codesourcery.com> Richard Sandiford <rdsandiford@googlemail.com> * micromips-opc.c (D32, D33, MC): Update definitions. (micromips_opcodes): Initialize ase field. * mips-dis.c (mips_arch_choice): Add ase field. (mips_arch_choices): Initialize ase field. (set_default_mips_dis_options): Declare and setup mips_ase. * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, MT32, MC): Update definitions. (mips_builtin_opcodes): Initialize ase field.	13 years ago

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