78c66db84c
PR 10288
* arm-dis.c (arm_opcodes): Be more strict about decoding scaled
addressing modes.
17 years ago
22102fb0d9
[cgen]
* cpu/mep-core.cpu (fsft, ssarb): Mark as VOLATILE.
* cpu/mep-ivc2.cpu (many): Add VOLATILE to more insns that make
unspecified accesses to control registers.
[sid/component/cgen-cpu/mep]
* mep-cop1-16-decode.cxx: Regenerate.
* mep-cop1-16-decode.h: Regenerate.
* mep-cop1-16-defs.h: Regenerate.
* mep-cop1-16-model.cxx: Regenerate.
* mep-cop1-16-model.h: Regenerate.
* mep-cop1-16-sem.cxx: Regenerate.
* mep-cop1-32-decode.cxx: Regenerate.
* mep-cop1-32-decode.h: Regenerate.
* mep-cop1-32-defs.h: Regenerate.
* mep-cop1-32-model.cxx: Regenerate.
* mep-cop1-32-model.h: Regenerate.
* mep-cop1-32-sem.cxx: Regenerate.
* mep-cop1-48-decode.cxx: Regenerate.
* mep-cop1-48-decode.h: Regenerate.
* mep-cop1-48-defs.h: Regenerate.
* mep-cop1-48-model.cxx: Regenerate.
* mep-cop1-48-model.h: Regenerate.
* mep-cop1-48-sem.cxx: Regenerate.
* mep-cop1-64-decode.cxx: Regenerate.
* mep-cop1-64-decode.h: Regenerate.
* mep-cop1-64-defs.h: Regenerate.
* mep-cop1-64-model.cxx: Regenerate.
* mep-cop1-64-model.h: Regenerate.
* mep-cop1-64-sem.cxx: Regenerate.
* mep-core1-decode.cxx: Regenerate.
* mep-core1-decode.h: Regenerate.
* mep-core1-defs.h: Regenerate.
* mep-core1-model.cxx: Regenerate.
* mep-core1-model.h: Regenerate.
* mep-core1-sem.cxx: Regenerate.
* mep-cpu.h: Regenerate.
* mep-decode.cxx: Regenerate.
* mep-decode.h: Regenerate.
* mep-defs.h: Regenerate.
* mep-desc.h: Regenerate.
* mep-model.cxx: Regenerate.
* mep-model.h: Regenerate.
* mep-sem.cxx: Regenerate.
[opcodes]
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
17 years ago
922d8de8c1
<gas changes>
2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* config/tc-i386.c (cpu_arch): Add .fma4 and CPU_FMA4_FLAGS.
(build_modrm_byte): Add support to handle FMA4 instructions.
(md_show_usage): Add fma4.
<gas/testsuite changes>
2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* gas/i386/i386.exp: Add FMA4 tests.
* gas/i386/x86-64-fma4.d: Ditto.
* gas/i386/fma4.d: Ditto.
* gas/i386/x86-64-fma4.s: Ditto.
* gas/i386/fma4.s: Ditto.
<opcodes changes>
2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* i386-opc.h (CpuFMA4): Add CpuFMA4.
(i386_cpu_flags): New.
* i386-gen.c: Add CPU_FMA4_FLAGS.
* i386-opc.tbl: Add FMA4 instructions.
* i386-tbl.h: Regenerate.
* i386-init.h: Regenerate.
* i386-dis.c (OP_VEX_FMA): New. Handle FMA4.
(OP_XMM_VexW): Ditto.
(OP_EX_VexW): Ditto.
(VEXI4_Fixup): Ditto.
(VexI4, VexFMA, Vex128FMA, EXVexW, EXdVexW, XMVexW): New Macros.
(PREFIX_VEX_3A5C, PREFIX_VEX_3A5D, PREFIX_VEX_3A5E): New.
(PREFIX_VEX_3A5F, PREFIX_VEX_3A60): New.
(PREFIX_VEX_3A68, PREFIX_VEX_3A69, PREFIX_VEX_3A6A): New.
(PREFIX_VEX_3A6B, PREFIX_VEX_3A6C, PREFIX_VEX_3A6D): New.
(PREFIX_VEX_3A6E, PREFIX_VEX_3A6F, PREFIX_VEX_3A7A): New.
(PREFIX_VEX_3A7B, PREFIX_VEX_3A7C, PREFIX_VEX_3A7D): New.
(PREFIX_VEX_3A7E, PREFIX_VEX_3A7F): New.
(VEX_LEN_3A6A_P_2,VEX_LEN_3A6B_P_2, VEX_LEN_3A6E_P_2): New.
(VEX_LEN_3A6F_P_2,VEX_LEN_3A7A_P_2, VEX_LEN_3A7B_P_2): New.
(VEX_LEN_3A7E_P_2,VEX_LEN_3A7F_P_2): New.
(get_vex_imm8): New. handle FMA4.
(OP_EX_VexReg): Ditto.
17 years ago
fe56b6cece
PR 10288
* arm-dis.c (coprocessor): Print the LDC and STC versions of the
LFM and SFM instructions as comments,.
Improve consistency of formatting for instructions displayed as
comments and decimal values displayed with their hexadecimal
equivalents.
Formatting tidy ups.
Updated expected disassembler regexps.
17 years ago
05413229fd
PR 10288
* arm-dis.c (enum opcode_sentinels): New: Used to mark the
boundary between variaant and generic coprocessor instuctions.
(coprocessor): Use it.
Fix architecture version of MCRR and MRRC instructions.
(arm_opcdes): Fix patterns for STRB and STRH instructions.
(print_insn_coprocessor): Check architecture and extension masks.
Print a hexadecimal version of any decimal constant that is
outside of the range of -16 to +32.
(print_arm_address): Add a return value of the offset used in the
adress, if it is worth printing a hexadecimal version of it.
(print_insn_neon): Print a hexadecimal version of any decimal
constant that is outside of the range of -16 to +32.
(print_insn_arm): Likewise.
(print_insn_thumb16): Likewise.
(print_insn_thumb32): Likewise.
PR 10297
* arm-dis.c (UNDEFINED_INSTRUCTION): New macro for a description
of an undefined instruction.
(arm_opcodes): Use it.
(thumb_opcod): Use it.
(thumb32_opc): Use it.
Update expected disassembly regrexps in GAS and LD testsuites.
17 years ago
dab97f2471
[cgen]
* intrinsics.scm: Updates to support IVC2.
(belongs-to-group?): Check IVC2 slots.
(-slots-attribute): New.
(targets::attributes): Add SLOTS.
(target:add-well-known-intrinsics): Add CPMOV.
(md-insn): Add CPTYPE and CRET?.
(add-md-insn): Likewise.
(add-intrinsic-for-isa): Disable the duplicate tests, as IVC2 has
duplicate insns with different bit patterns.
(write-cgen-insn?): Add cret? support.
(intrinsics.h): Add vector types.
(runtime-op): Add vector support.
(intrinsic-protos.h): Let GCC define its types. Add cret? support.
* cpu/mep-core.cpu: Add CPTYPE and CRET attributes.
* cpu/mep-ivc2.cpu: Update all insns to include type information.
(h-cr-ivc2): Default to typeless.
(h-ccr-ivc2): Fix register width.
(SLOTS): Fix values and default.
(ivc2_*): Add control register names.
(crop, crqp, crpp, croc, crqc, crpc): Default to typeless.
[opcodes]
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
[sid/component/cgen-cpu/mep]
* ivc2-cop.cxx (ivc2_cphadd_w): Change to return value.
(ivc2_cpsubaca0u_b): Remove debug line.
* ivc2-cpu.h (ivc2_cpccadd_b): Change to return value.
* mep-cop1-16-decode.cxx: Regenerate.
* mep-cop1-16-sem.cxx: Regenerate.
* mep-cop1-32-decode.cxx: Regenerate.
* mep-cop1-32-sem.cxx: Regenerate.
* mep-cop1-48-decode.cxx: Regenerate.
* mep-cop1-48-sem.cxx: Regenerate.
* mep-cop1-64-decode.cxx: Regenerate.
* mep-cop1-64-sem.cxx: Regenerate.
* mep-core1-decode.cxx: Regenerate.
* mep-cpu.h: Regenerate.
* mep-decode.cxx: Regenerate.
* mep-desc.h: Regenerate.
17 years ago
378a0c07ca
[cgen]
* cpu/mep.opc (mep_cgen_insn_supported_asm): New, skip the short
version of BSR when assembling VLIW bundles. Use it in mep-asm.c
[opcodes]
* mep-asm.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
17 years ago
aece7d2e74
* po/fi.po: Updated Finish translation.
17 years ago
1998a8e033
cpu/
* m32c.opc (parse_lab_5_3): Use correct enum.
opcodes/
* m32c-asm.c: Regenerate.
17 years ago
b33bafa0d7
* score-dis.c (print_insn_score48, print_insn_score32): Move default
case label to proper lexical block.
* score7-dis.c (print_insn_score32): Likewise.
17 years ago
ce21feb4ba
* s390-opc.c (INSTR_RR_0R_OPT, INSTR_RX_0RRD_OPT, MASK_RR_0R_OPT,
MASK_RX_0RRD_OPT): New instruction formats with optional arguments.
* s390-opc.txt (nopr, nop): Use new instruction format.
17 years ago
0313a2b8d2
PR 10288
* arm-dis.c (print_insn_coprocessor): Check that a user specified
ARM architecture supports the matched instruction.
(print_insn_arm): Likewise.
(select_arm_features): New function. Fills in the fields of an
arm_feature_set structure based on a given arm machine number.
(print_insn): Initialise an arm_feature_set structure.
* objdump.c (disassemble_bytes): Set the
USER_SPECIFIED_MACHINE_TYPE flag in the disassemble_info structure
if the user has invoked the -m switch.
* doc/binutils.texi: Document the additional behaviour of
objdump's -m switch for ARM targets.
* dis-asm.h (USER_SPECIFIED_MACHINE_TYPE): New value for the flags
field of struct disassemble_info.
* gas/arm/align.s: Add labels so that COFF based targets can
correctly locate THUMB code.
* gas/arm/copro.d: Do not pass --architecture switch to objdump.
17 years ago
6db7e006e4
bfd/
* elf32-vax.c (elf_vax_plt_sym_val): New function.
(elf_backend_plt_sym_val): Define.
opcodes/
* vax-dis.c (is_function_entry): Return success for synthetic
symbols too.
(is_plt_tail): New function.
(print_insn_vax): Decode PLT entry offset longword.
17 years ago
fe2ceba101
PR 10186
* arm-dis.c (thumb32_opcodes): Fix binary value of SEV.W
instruction.
* gas/arm/thumb32.d: Fix expected binary value of SEV.W instruction.
* config/tc-arm.c (T16_32_TAB): Fix binary value of SEV.W
instruction.
17 years ago
522fe56177
PR 10173
* cr16-dis.c (print_arg): Avoid printing the 0x prefix twice.
17 years ago
1316c8b37f
PR 10263
* arm-dis.c (print_insn): Ignore is_data if the user has requested
the disassembly of data as well as instructions.
* objdump.c (disassemble_bytes): Set the DISASSEMBLE_DATA bit in
the flags field of the disassemble_info structure if the -D switch
is in operation.
* dis-asm.h (struct disassemble_info): New value for the flags
field.
17 years ago
f6475b4872
* cgen.sh: Handle multiple simultaneous runs for parallel makes.
17 years ago
f865a31d1e
Add PC-relative branch instructions to moxie port.
17 years ago
0e7c7f11f4
Print moxie addresses nicely.
17 years ago
67a648f17a
* dep-in.sed: Don't use \n in replacement part of s command.
* Makefile.am (DEP1): LC_ALL for uniq.
* Makefile.in: Regenerate.
17 years ago
06c582ac9d
* po/nl.po: Updated Dutch translation.
17 years ago
3164099e4f
2009-05-29 Tristan Gingold <gingold@adacore.com>
* ia64-gen.c (parse_resource_users, print_dependency_table,
add_dis_table_ent, finish_distable, insert_bit_table_ent,
add_dis_entry, compact_distree, gen_dis_table, completer_entries_eq,
get_prefix_len, compute_completer_bits, insert_opcode_dependencies,
insert_completer_entry, print_completer_entry, print_completer_table,
opcodes_eq, add_opcode_entry, shrink): Use ISO C syntax for functions.
17 years ago
d285268e48
[cgen]
* cpu/mep.opc (parse_signed16_range): New.
(parse_unsigned16_range): New.
* cpu/mep-ivc2.cpu (imm16p0, simm16p0): Use them.
[opcodes]
* mep-asm.c: Regenerate.
* mep-desc.c: Regenerate.
17 years ago
2f3565a392
[cgen/cpu]
* cpu/mep-ivc2.cpu (h-ccr-ivc2): Enable for C3 slots, fix
accumulator names.
(f-ivc2-ccrn-c3hi): New.
(f-ivc2-ccrn-c3lo): New.
(f-ivc2-ccrn-c3): New.
(ivc2c3ccrn): Use it.
[sid/component/cgen-cpu/mep]
* mep-cop1-32-decode.cxx: Regenerate.
* mep-cop1-32-decode.h: Regenerate.
* mep-cop1-32-sem.cxx: Regenerate.
* mep-cop1-48-sem.cxx: Regenerate.
[opcodes]
* mep-asm.c: Regenerate.
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
17 years ago
f12e7348b2
Update Indonesian translations.
Update translation templates.
17 years ago
9e097a72c9
* dep-in.sed: Don't modify .o to .lo here. Output one filename
per line with all lines having continuation backslash. Prefix
first line with "A", following lines with "B".
* Makefile.am (DEP): Don't use dep.sed here.
(DEP1): Run $MKDEP on single files, modify .o to .lo here. Use
dep.sed here on dependencies, sort and uniq.
* Makefile.in: Regenerate.
18 years ago
4f8318f890
2009-05-25 Tristan Gingold <gingold@adacore.com>
* makefile.vms (OPT): New variable.
(CFLAGS): Update compilation flags.
18 years ago
1d74713bc6
[cgen]
* cpu/mep.opc (mep_examine_ivc2_insns): Fix bug in ivc2 decoder.
(mep_config_map): Regenerate.
* cpu/mep-ivc2.cpu (h-ccr-ivc2): Add generic names as well as
ivc2-specific names.
(simm8p20): New.
(cmovc): move to after field definitions, use ivc2-specific
register names.
(cpmovi_b_P0S_P1): New.
[utils/mep]
* mepcfgtool.c (do_cgen_config_opc): Propagate endianness and VLIW
size to default configuration.
[sid/component/cgen-cpu/mep]
* mep-cop1-16-decode.cxx: Regenerate.
* mep-cop1-16-decode.h: Regenerate.
* mep-cop1-16-model.cxx: Regenerate.
* mep-cop1-16-model.h: Regenerate.
* mep-cop1-16-sem.cxx: Regenerate.
* mep-cop1-64-decode.cxx: Regenerate.
* mep-cop1-64-decode.h: Regenerate.
* mep-cop1-64-model.cxx: Regenerate.
* mep-cop1-64-model.h: Regenerate.
* mep-cop1-64-sem.cxx: Regenerate.
[opcodes]
* mep-asm.c: Regenerate.
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
18 years ago
c1e679ec0a
<gas changes>
2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* config/tc-i386.c (process_drex): Delete. Remove SSE5 support.
(build_modrm_byte): Remove DREX handling support.
(DREX_*): Delete.
(drex_byte): Delete.
(md_assemble): Remove DREX handling support.
(process_operands): Remove DREX, SSE5 support.
(i386_insn): Remove DREX.
<gas/testsuite changes>
2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* gas/i386/i386.exp: Remove SSE5 tests.
* gas/i386/x86-64-sse5.s: Delete. Remove SSE5 tests.
* gas/i386/x86-64-sse5.d: Ditto.
* gas/i386/arch-10-1.l: Remove SSE5 tests.
* gas/i386/arch-10-2.l: Ditto.
* gas/i386/arch-10-3.l: Ditto.
* gas/i386/arch-10-4.l: Ditto.
* gas/i386/arch-10.d: Ditto.
* gas/i386/arch-10.s: Ditto.
* gas/i386/arch-4.s: Delete. Remove SSE5 tests.
* gas/i386/arch-4.d: Ditto.
* gas/i386/arch-8.s: Ditto.
* gas/i386/arch-8.d: Ditto.
* gas/i386/arch-2.s: Remove SSE5 tests.
* gas/i386/arch-2.d: Remove SSE5 tests.
* gas/i386/x86-64-arch-2.s: Ditto.
<opcodes changes>
2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* i386-opc.h (Cpusse5): Delete.
(i386_cpu_flags): Delete.
* i386-gen.c: Remove CpuSSE5, Drex, Drexv and Drexc.
* i386-opc.tbl: Remove SSE5 instructions.
* i386-tbl.h: Regenerate.
* i386-init.h: Regenerate.
* i386-dis.c (OP_E_memeory, OP_E_extended): Remove drex handling.
(print_drex_arg): Delete.
(OP_DREX4): Delete.
(OP_DREX3): Delete.
(OP_DREX_ICMP): Delete.
(OP_DREX_FCMP): Delete.
(DREX_*): Delete.
(THREE_BYTE_0F24, THREE_BYTE_0F25, THREE_BYTE_0f7B): Delete.
18 years ago
2b3decb5e1
Run "make dep-am" and regenerate
18 years ago
eb9568003a
* mep-asm.c: Regenerate.
* mep-opc.c: Regenerate.
18 years ago
3526b6802e
Index: opcodes
* mep-asm.c: Regenerate.
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
Index: gas
* config/tc-mep.c (md_begin): Check coprocessor type.
(md_check_parallel64_scheduling): Use memset to initialize the buffer.
(md_check_parallel32_scheduling): Likewise.
(slot_ok): New.
(mep_check_ivc2_scheduling): New.
(mep_check_parallel_scheduling): Call it.
(mep_process_saved_insns): Add IVC2 slot support.
(md_assemble): Likewise.
18 years ago
59b1530d0b
Add missing disassembler patch for moxie.
18 years ago
45be3704c8
[cgen]
* cpu/mep-c5.cpu (f-12s20): Change to signed.
(lhucpm1): Limit to C5 mach.
(dsp0,dsp1): Rewrite as aliases so that intrinsics are generated.
* cpu/mep-core.cpu (extend-cdisp10): New.
(f-cdisp10): Change to signed, use extend-cdisp10 to sign extend.
[opcodes]
* mep-desc.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
[sid/component/cgen-cpu/mep]
* mep-core1-decode.cxx: Regenerate.
* mep-core1-decode.h: Regenerate.
* mep-decode.cxx: Regenerate.
* mep-decode.h: Regenerate.
18 years ago
52de720d5d
Add missing ChangeLog entry:
* mep-asm.c: Regenerate.
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
18 years ago
20135e4cea
Add new binutils target: moxie
18 years ago
ac5c19e6ba
gas/testsuite/
2009-04-15 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-sse5.s: Add test of protd.
* gas/i386/x86-64-sse5.d: Adjust expectations to match input.
opcodes/
2009-04-15 Jan Beulich <jbeulich@novell.com>
* i386-opc.tbl (protb, protw, protd, protq): Set opcode
extension to None.
(pshab, pshaw, pshad, pshaq): Likewise.
* i386-tbl.h: Re-generate.
18 years ago
40493983ad
[cgen]
* cpu/mep-c5.cpu: New.
* cpu/mep-core.cpu: Add C5 support.
* cpu/mep.opc: Likewise.
[opcodes]
* mep-asm.c: Regenerate.
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
[sid]
* component/cache/cache.cxx (cache_component::cache_component):
Add write_hint_pin(). Attach it to write-hint.
(cache_component::write_hint): New.
* component/cache/cache.h (write_hint_pin): New.
(write_hint): New.
* component/cgen-cpu/mep/Makefile.am: Regenerate.
* component/cgen-cpu/mep/Makefile.in: Regenerate.
* component/cgen-cpu/mep/mep-core1-decode.cxx: Regenerate.
* component/cgen-cpu/mep/mep-core1-decode.h: Regenerate.
* component/cgen-cpu/mep/mep-core1-defs.h: Regenerate.
* component/cgen-cpu/mep/mep-core1-model.cxx: Regenerate.
* component/cgen-cpu/mep/mep-core1-model.h: Regenerate.
* component/cgen-cpu/mep/mep-core1-sem.cxx: Regenerate.
* component/cgen-cpu/mep/mep-decode.cxx: Regenerate.
* component/cgen-cpu/mep/mep-decode.h: Regenerate.
* component/cgen-cpu/mep/mep-defs.h: Regenerate.
* component/cgen-cpu/mep/mep-desc.h: Regenerate.
* component/cgen-cpu/mep/mep-model.cxx: Regenerate.
* component/cgen-cpu/mep/mep-model.h: Regenerate.
* component/cgen-cpu/mep/mep-sem.cxx: Regenerate.
* component/cgen-cpu/mep/mep.cxx (mep_cpu): Connect
write-hint pin.
(do_cache): Add C5 support.
(do_cache_prefetch): Likewise.
(do_casb3, do_cash3, do_casw3): New.
* component/cgen-cpu/mep/mep.h: Add C5 support and write-hint pin.
(do_casb3, do_cash3, do_casw3): New.
* component/families/mep/Makefile.in: Regenerate.
* component/families/mep/dsu.in: Add C5 support.
* main/dynamic/mainDynamic.cxx: Add C5 support.
* main/dynamic/mepCfg.cxx: Connect write-hint pin.
* main/dynamic/mepCfg.h: Add C5 support.
18 years ago
858d7a6db2
opcodes/
* ppc-opc.c (powerpc_opcodes) <"tlbilxlpid", "tlbilxpid", "tlbilxva",
"tlbilx">: Use secondary opcode "18" as per the ISA 2.06 documentation.
Reorder entries so the extended mnemonics are listed before tlbilx.
gas/testsuite/
* gas/ppc/e500mc.d: Update to match extended mnemonics.
18 years ago
70dc4e324b
opcodes/
* ppc-dis.c (powerpc_init_dialect): Do not choose a default dialect
due to -many/-Many.
(print_insn_powerpc): Make sure we only deprecate instructions using
the original dialect and not a modified dialect due to -Many handling.
Move the handling of the condition register and default operands to
the end of the if/else if/else chain.
* ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that
instructions from newer processors are listed before older ones.
<"icblce", "sync", "eieio", "tlbld">: Deprecate for processors
that have instructions with conflicting opcodes.
18 years ago
e401b04ca7
opcodes/
* ppc-opc.c (powerpc_opcodes) <"dcbzl">: Merge the POWER4 and
E500MC entries.
18 years ago
b8f9ee44f9
2009-04-01 Christophe Lyon <christophe.lyon@st.com>
opcodes/
* arm-dis.c (print_insn): Print BE8 opcodes in little endianness.
ld/testsuite/
* ld-arm/arm-elf.exp: BE8 tests expect the same output as the
default ones.
* ld-arm/arm-be8.d: Print opcodes in little endian.
* ld-arm/farcall-thumb-arm-be8.d: Removed useless expected result.
* ld-arm/farcall-arm-arm-be8.d: Likewise.
18 years ago
d460e92e41
gas/testsuite:
* gas/arm/mapsecs.d, gas/arm/mapsecs.s: New.
opcodes:
* arm-dis.c (print_insn): Also check section matches in backwards
search for mapping symbol.
18 years ago
d34b50065a
2009-03-26 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (get_valid_dis386): Abort on unhandled table.
18 years ago
02b1cb404a
* Makefile.am (BFD32_BACKENDS): Remove elf32-score and
elf32-score7 files.
(BFD32_BACKEND_CFILES): Likewise.
(BFD64_BACKENDS): Add elf32-score and elf32-score7 files.
(BFD64_BACKENDS_CFILES): Likewise.
* Makefile.in: Regenerate.
* config.bfd: More Score targets into BFD64 list.
* configure.in: Move score vectors to 64-bit list.
* targets.c: Likewise.
* score-dis.c: Only compile when 64-bit bfds are enabled.
18 years ago
3889c459bb
bfd/
* vms-hdr.c: Don't include alloca.h.
opcodes/
* cgen-opc.c: Include alloca-conf.h rather than alloca.h.
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
18 years ago
8d25cc3de0
include/
* alloca-conf.h: Revise based on autoconf-2.61, autoconf-2.13
documentation.
bfd/
* elf32-m68hc1x.c: Include alloca-conf.h.
* xsym.c: Likewise.
* elf64-hppa.c: Likewise. Remove existing #if's handling alloca.
* som.c: Likewise.
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
binutils/
* sysdep.h: Include alloca-conf.h instead of config.h and remove
existing #if's handling alloca.
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
gas/
* as.h: Include alloca-conf.h instead of config.h and remove
existing #if's handling alloca.
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
opcodes/
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
* openrisc-opc.c: Regenerate.
ld/
* ld.h: Remove alloca handling.
18 years ago
34dd024a28
Add Spanish translation to gold.
Update Indonesian translation for opcodes.
18 years ago
69fe9ce501
include/opcode/
* ppc.h (ppc_parse_cpu): Declare.
opcodes/
* ppc-dis.c: Include "opintl.h".
(struct ppc_mopt, ppc_opts): New.
(ppc_parse_cpu): New function.
(powerpc_init_dialect): Use it.
(print_ppc_disassembler_options): Dump options from ppc_opts.
Internationalize message.
gas/
* config/tc-ppc.c (parse_cpu): Delete.
(md_parse_option, ppc_machine): Use ppc_parse_cpu.
gas/testsuite/
* gas/ppc/altivec_and_spe.d (objdump): Add -Maltivec.
* gas/ppc/common.d: Adjust for -Mcom not including -Mppc.
18 years ago
d11fd24905
Updated Spanish translations.
18 years ago
Nick Clifton
DJ Delorie
Dwarakanath Rajagopal
Alan Modra
Martin Schwidefsky
Maciej W. Rozycki
Doug Evans
Anthony Green
Tristan Gingold
Jan Beulich
Peter Bergner
Christophe Lyon
Joseph Myers
H.J. Lu