binutils-gdb

Tree: 5ea695edcd

Author	SHA1	Message	Date
Stan Shebs	7a292a7adf	import gdb-19990422 snapshot	28 years ago
Stan Shebs	c906108c21	Initial creation of sourceware repository	28 years ago
Stan Shebs	071ea11e85	Initial creation of sourceware repository	28 years ago
Doug Evans	169c74762a	* sim-core.h (SIM_CORE_SIGNAL_FN): New typedef. * sim-core.c (sim_core_signal): Make extern, always define.	29 years ago
Doug Evans	2307e0ee98	Good grief. Detailed function descriptions should accompany their definition.	29 years ago
Doug Evans	751197f231	(profile_print_core): Simplify by calling sim_core_map_to_str. * sim-core.h (sim_core_map_to_str): Declare. * sim-core.c (sim_core_map_to_str): Make non-static.	29 years ago
Andrew Cagney	fcc86d82f7	Make memory regions layered (just like existing device regions) so that overlapping regions can be defined. Allow the layer (level) of a memory region to be specified as part of an address parameter to memory options. Update simulators.	29 years ago
Doug Evans	d048b52dbb	* sim-core.h (sim_core_write_8): Define.	29 years ago
Andrew Cagney	a86809d323	Implement sim_core_{read,write}_word using sim_core_{read,write}_<N>.	29 years ago
Andrew Cagney	f45dd42b32	Add 128 bit transfers to sim core.	29 years ago
Andrew Cagney	fd89abc204	Handle core regions which start at a poorly aligned address.	29 years ago
Andrew Cagney	a34abff813	o Add modulo argument to sim_core_attach o Add sim-memopt module - memory option processing.	29 years ago
Andrew Cagney	cd0d873d0f	Preliminary suport for xor-endian suport in core module.	30 years ago
Andrew Cagney	7a418800c1	Start of implementation of a distributed (between processors) simulator core object.	30 years ago
David Edelsohn	c967f1874a	* Makefile.in (sim-options_h): Define. (sim-{module,options,trace,profile,utils}.o): Clean up dependencies. (sim-model.o): Add new rule. (cgen-{scache,trace,utils}.o): Add new rules. * aclocal.m4 (SIM_AC_OPTION_{SCACHE,DEFAULT_MODEL}): Add. * cgen-scache.c (scache_print_profile): Change `sd' arg to `cpu'. Indent output by 2 spaces. * cgen-scache.h (scache_print_profile): Update. * cgen-trace.c (trace_insn_fini): Indent output by 2 spaces. Use trace_printf, not fprintf. (trace_extract): Use trace_printf, not cgen_trace_printf. * genmloop.sh (!FAST case): Increment `insn_count'. * sim-base.h (sim_state_base): Only include scache_size if WITH_SCACHE. (sim_cpu_base): Rename member `sd' to `state' to be consistent with access macro's name. * sim-core.c (sim_core_init): Use EXTERN_SIM_CORE to define it. Change return type to SIM_RC. (sim_core_{install,uninstall}): New functions. * sim-core.h (sim_core_{install,uninstall}): Declare. (sim_core_init): Use EXTERN_SIM_CORE to define it. Change return type to SIM_RC. * sim-model.h (models,machs,model_install): Declare. * sim-module.c (modules): Add scache_install, model_install. (sim_post_argv_init): Set cpu->state backlinks. * sim-options.c (standard_options): Delete --simcache-size,--max-insns. (standard_option_handler): Likewise. * sim-profile.c (PROFILE_{HISTOGRAM,LABEL}_WIDTH): Move to sim-profile.h. (): Assume ANSI C. (profile_options): Delete --profile-simcache. (profile_option_handler): Likewise. (profile_print_insn): Change `sd' arg to `cpu'. Indent output 2 spaces. (profile_print_{memory,model}): Likewise. (profile_print_simcache): Delete. (profile_print_speed): New function. (profile_print): Rewrite. sim-profile.h (PROFILE_scache): Renamed from PROFILE_simcache. (WITH_PROFILE_SCACHE_P): Renamed from WITH_PROFILE_SIMCACHE_P. (PROFILE_DATA): Delete members simcache_{hits,misses}. (PROFILE_COUNT_SIMCACHE_{HIT,MISS}): Delete. (PROFILE_{CALLBACK,CPU_CALLBACK}): New types. (profile_print): Update prototype.	30 years ago

15 Commits (5ea695edcd4b9a6c1a6bc975bfdb1becffb267bf)