binutils-gdb

Commit Graph

Author	SHA1	Message	Date
H.J. Lu	5bc71c2a6b	x86-64: Add R_X86_64_CODE_6_GOTTPOFF For add %reg1, name@gottpoff(%rip), %reg2 and add name@gottpoff(%rip), %reg1, %reg2 add #define R_X86_64_CODE_6_GOTTPOFF 50 if the instruction starts at 6 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF. Linker can covert GOTTPOFF to add $name@tpoff, %reg1, %reg2 Rewrite fx_tcbit, fx_tcbit2 and fx_tcbit3 usage to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX, R_X86_64_CODE_4_GOTPCRELX, R_X86_64_CODE_4_GOTTPOFF, R_X86_64_CODE_4_GOTPC32_TLSDESC and R_X86_64_CODE_6_GOTTPOFF. NB: There is no need to check BFD_RELOC_X86_64_CODE_4_GOTTPOFF in md_assemble since there is only BFD_RELOC_X86_64_GOTTPOFF at this stage, which will be converted to BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_6_GOTTPOFF in i386_validate_fix. 5 relocations: #define R_X86_64_CODE_5_GOTPCRELX 46 #define R_X86_64_CODE_5_GOTTPOFF 47 #define R_X86_64_CODE_5_GOTPC32_TLSDESC 48 #define R_X86_64_CODE_6_GOTPCRELX 49 #define R_X86_64_CODE_6_GOTPC32_TLSDESC 51 are added for completeness and they are unused. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_6_GOTTPOFF. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Handle R_X86_64_CODE_6_GOTTPOFF. Issue an error for R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX and R_X86_64_CODE_6_GOTPC32_TLSDESC. (elf_x86_64_relocate_section): Handle R_X86_64_CODE_6_GOTTPOFF. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_5_GOTPCRELX, BFD_RELOC_X86_64_CODE_5_GOTTPOFF, BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC, BFD_RELOC_X86_64_CODE_6_GOTPCRELX, BFD_RELOC_X86_64_CODE_6_GOTTPOFF and BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. elfcpp/ * x86_64.h (R_X86_64_CODE_5_GOTPCRELX): New. (R_X86_64_CODE_5_GOTTPOFF): Likewise. (R_X86_64_CODE_5_GOTPC32_TLSDESC): Likewise. (R_X86_64_CODE_6_GOTPCRELX): Likewise. (R_X86_64_CODE_6_GOTTPOFF): Likewise. (R_X86_64_CODE_6_GOTPC32_TLSDESC): Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. (md_assemble): Don't check BFD_RELOC_X86_64_CODE_4_GOTTPOFF. Allow "add %reg1, foo@gottpoff(%rip), %reg2". (output_disp): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. Rewrite setting fx_tcbitX bits for BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL. (md_apply_fix): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. (i386_validate_fix): Rewrite fx_tcbitX bit checking for BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. * testsuite/gas/i386/x86-64-gottpoff.d: Updated. * testsuite/gas/i386/x86-64-gottpoff.s: Add tests for "add %reg1, foo@gottpoff(%rip), %reg2" and "add foo@gottpoff(%rip), %reg, %reg2". gold/ * x86_64.cc (Target_x86_64::optimize_tls_reloc): Handle R_X86_64_CODE_6_GOTTPOFF. (Target_x86_64::Scan::get_reference_flags): Likewise. (Target_x86_64::Scan::local): Likewise. (Target_x86_64::Scan::global): Likewise. (Target_x86_64::Relocate::relocate): Likewise. (Target_x86_64::Relocate::relocate_tls): Likewise. (Target_x86_64::Relocate::tls_ie_to_le): Handle. R_X86_64_CODE_6_GOTTPOFF. * testsuite/x86_64_ie_to_le.s: Add tests for "add %reg1, foo@gottpoff(%rip), %reg2" and "add foo@gottpoff(%rip), %reg, %reg2". * testsuite/x86_64_ie_to_le.sh: Updated. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. ld/ * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_6_GOTTPOFF tests. * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise.	3 years ago
Alan Modra	60c95acdac	Link x86-64 mark-plt-1.so with --no-as-needed Fixes FAIL: Build mark-plt-1.so where gcc is built with default --as-needed. * testsuite/ld-x86-64/x86-64.exp (Build mark-plt-1.so): Pass --no-as-needed.	3 years ago
Georg-Johann Lay	24f5deb64d	PR31124: Addendum: Remove PROVIDE of __flmap_init_label, __flmap. Supply these symbols as computed by the linker scripts, even when there are weak definitions. PR 31124 * scripttempl/avr.sc (__flmap, __flmap_init_label): Remove PROVIDE.	3 years ago
Nick Clifton	fff48b7cb0	Updated French translations for GOLD and LD	3 years ago
H.J. Lu	1b06334552	elf: Rename is_standard_elf to uses_elf_em Rename is_standard_elf to uses_elf_em for targets which use elf.em. binutils/ PR ld/31289 * testsuite/lib/binutils-common.exp (is_standard_elf): Renamed to ... (uses_elf_em): This. ld/ PR ld/31289 * testsuite/ld-elf/fatal-warnings-2a.d: Replace is_standard_elf with uses_elf_em. * testsuite/ld-elf/fatal-warnings-2b.d: Likewise. * testsuite/ld-elf/fatal-warnings-3a.d: Likewise. * testsuite/ld-elf/fatal-warnings-3b.d: Likewise. * testsuite/ld-elf/fatal-warnings-4a.d: Likewise. * testsuite/ld-elf/fatal-warnings-4b.d: Likewise.	3 years ago
Nick Clifton	9c8d5b9a4f	Remove -pie from command line of fatal-warnings 1a and 1b tests.	3 years ago
mengqinggang	a0aa6f4abd	LoongArch: ld: Add support for TLS LE symbol with addend Add support for TLS LE symbol with addend, such as: lu12i.w $t0, %le_hi20(a + 0x8) ori $t0, $t0, %le_lo12(a + 0x8)	3 years ago
H.J. Lu	eb12b17047	elf: Add is_standard_elf PR ld/31289 tests failed for fr30-elf, frv-elf, ft32-elf, iq2000-elf, mn10200-elf, ms1-elf and msp430-elf targets: FAIL: ld-elf/fatal-warnings-2a FAIL: ld-elf/fatal-warnings-2b FAIL: ld-elf/fatal-warnings-3a FAIL: ld-elf/fatal-warnings-3b FAIL: ld-elf/fatal-warnings-4a FAIL: ld-elf/fatal-warnings-4b even though PR ld/31289 targets xfail for [is_generic] targets. These targets not only don't use the generic_link_hash_table linker, but also don't use the standard ELF emulation. Add is_standard_elf for ELF targets which use the standard ELF emulation and replace [is_generic] with ![is_standard_elf] in PR ld/31289 tests. binutils/ PR ld/31289 * testsuite/lib/binutils-common.exp (is_standard_elf): New. ld/ PR ld/31289 * testsuite/lib/binutils-common.exp (is_generic): Return 1 for fr30--, frv--elf, ft32--, iq2000--, mn10200--, moxie--moxiebox, msp430--* and mt--. * testsuite/ld-elf/fatal-warnings-2a.d: Replace [is_generic] with ![is_standard_elf]. * testsuite/ld-elf/fatal-warnings-2b.d: Likewise. * testsuite/ld-elf/fatal-warnings-3a.d: Likewise. * testsuite/ld-elf/fatal-warnings-3b.d: Likewise. * testsuite/ld-elf/fatal-warnings-4a.d: Likewise. * testsuite/ld-elf/fatal-warnings-4b.d: Likewise.	3 years ago
H.J. Lu	624c610dd4	ld: Always call output_unknown_cmdline_warning Call output_unknown_cmdline_warning if there are no input files so that $ ld -z bad-option reports ld: warning: -z bad-option ignored ld: no input files instead of ld: no input files PR ld/31289 * ldmain.c (main): Call output_unknown_cmdline_warning if there are no input files.	3 years ago
H.J. Lu	3eb33b8875	ld: Improve --fatal-warnings for unknown command-line options There are 2 problems with --fatal-warnings for unknown command-line options: 1. --fatal-warnings doesn't trigger an error for an unknown command-line option when --fatal-warnings is the last command-line option. 2. When --fatal-warnings triggers an error for an unknown command-line option, the message says that the unknown command-line option is ignored. This patch queues unknown command-line option warnings and outputs queued command-line option warnings after all command-line options have been processed so that --fatal-warnings can work for unknown command-line options regardless of the order of --fatal-warnings. When --fatal-warnings is used, the linker message is changed from ld: warning: -z bad-option ignored to ld: error: unsupported option: -z bad-option The above also applies to "-z dynamic-undefined-weak" when the known "-z dynamic-undefined-weak" option is ignored. PR ld/31289 * ldelf.c (ldelf_after_parse): Use queue_unknown_cmdline_warning to warn the ignored -z dynamic-undefined-weak option. * ldmain.c (main): Call output_unknown_cmdline_warnings after calling ldemul_after_parse. * ldmisc.c (CMDLINE_WARNING_SIZE): New. (cmdline_warning_list): Likewise. (cmdline_warning_head): Likewise. (cmdline_warning_tail): Likewise. (queue_unknown_cmdline_warning): Likewise. (output_unknown_cmdline_warnings): Likewise. * ldmisc.h (queue_unknown_cmdline_warning): Likewise. (output_unknown_cmdline_warnings): Likewise. * emultempl/elf.em (gld${EMULATION_NAME}_handle_option): Use queue_unknown_cmdline_warning to warn unknown -z option. * testsuite/ld-elf/fatal-warnings-1a.d: New file. * testsuite/ld-elf/fatal-warnings-1b.d: Likewise. * testsuite/ld-elf/fatal-warnings-2a.d: Likewise. * testsuite/ld-elf/fatal-warnings-2b.d: Likewise. * testsuite/ld-elf/fatal-warnings-3a.d: Likewise. * testsuite/ld-elf/fatal-warnings-3b.d: Likewise. * testsuite/ld-elf/fatal-warnings-4a.d: Likewise. * testsuite/ld-elf/fatal-warnings-4b.d: Likewise.	3 years ago
Xi Ruoyao	36176c5d90	[PATCH v2] gas/NEWS, ld/NEWS: Announce LoongArch changes in 2.42	3 years ago
Xi Ruoyao	7b0b94b7b9	LoongArch: Fix some test failures about TLS desc and TLS relaxation There are two issues causing 11 test failures: 1. The TLS desc tests are matching the entire disassemble of a linked executable. But if ld is configured --enable-default-hash-style=gnu (note that most modern distros use this option), the layout of the linked executables will be different and the immediate operands in the linked executables will also be different. So we add "--hash-style=both" for these tests to cancel the effect of --enable-default-hash-style=gnu, like [x86_64 mark-plt tests]. 2. By default objdump disassemble uses [pseudo-instructions] so "addi.w" is outputed as "li.w", causing mismatches in TLS relaxation tests. We can turn off the pseudo-instruction usage in objdump using "-M no-aliases" to fix them. [x86_64 mark-plt tests]: `16666ccc91` [pseudo-instructions]: `17f9439038` Signed-off-by: Xi Ruoyao <xry111@xry111.site>	3 years ago
mengqinggang	32ee2b4b71	LoongArch: Do not emit R_LARCH_RELAX for two register macros For two register macros (e.g. la.local $t0, $t1, symbol) used in extreme code model, do not emit R_LARCH_RELAX relocations.	3 years ago
H.J. Lu	c873acc5fe	ld: Remove scripttempl/elf_chaos.sc scripttempl/elf_chaos.sc is unused. Remove it. * scripttempl/elf_chaos.sc: Removed.	3 years ago
H.J. Lu	dbca3300ea	Remove hosts/mipsbsd.h and scripttempl/mipsbsd.sc Remove hosts/mipsbsd.h and scripttempl/mipsbsd.sc which are unused after commit `3596d8ceb2` Author: Alan Modra <amodra@gmail.com> Date: Wed Apr 18 15:39:34 2018 +0930 Remove mips aout, coff, and pe support bfd/ * hosts/mipsbsd.h: Removed. ld/ * scripttempl/mipsbsd.sc: Removed.	3 years ago
Oleg Tolmatcev	d544a1dca2	ld: fix 32-bit mingw DLL symbol export bug I think there's a bug in ld on 32-bit Windows. Here is a tiny project for reproducing the problem: https://github.com/oltolm/ld-mingw32-bug A 32-bit DLL exports two stdcall functions "myfunc" and "myfunc64". The functions would normally get exported as "myfunc@0" and "myfunc64@0". The "DEF" file exports them as "myfunc" and "myfunc64" without the decorations. When you run the executable it shows an error message saying that it cannot find "myfunc64". I think it happens because the sorting in ld is wrong. I think it should use the exported names "myfunc" and "myfunc64", but instead it uses the decorated names "myfunc@0" or "myfunc65@0". The ordering of functions in the DLL is different depending on which names you use. My patch changes ld to use undecorated exported names for sorting and it seems to fix the problem. When I execute ctest in my project, it runs successfully.	3 years ago
H.J. Lu	8d10083c23	ld: Put all emulation options in ldlex.h For each command line option, parse_args() calls ldemul_parse_args() to check if the command line option is an emulation option. But when there is a conflict between the emulation option value and the default option value, the default command line option will be processed as if the emulation option is used. Remove PARSE_AND_LIST_PROLOGUE and move all emulation options to ldlex.h to avoid conflicts. PR ld/31247 * ldlex.h (option_values): Add all emulation options. * emulparams/elf32mcore.sh (PARSE_AND_LIST_PROLOGUE): Removed. * emulparams/plt_unwind.sh (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/aarch64elf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/alphaelf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/armelf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/avrelf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/bfin.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/cskyelf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/hppaelf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/ia64elf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/m68hc1xelf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/m68kelf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/metagelf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/mipself.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/nds32elf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/nto.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/ppc32elf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/ppc64elf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/riscvelf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/rxelf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/s390.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/scoreelf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/spuelf.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/tic6xdsbt.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/vxworks.em (PARSE_AND_LIST_PROLOGUE): Likewise. * emultempl/aix.em: Include "ldlex.h". (OPTION_XXX): Removed. (gld${EMULATION_NAME}_read_file): Replace lineno with linenumber. * emultempl/beos.em (OPTION_XXX): Removed. * emultempl/elf.em: Include "ldlex.h". Don't check PARSE_AND_LIST_PROLOGUE. (OPTION_XXX): Removed. * emultempl/msp430.em: Include "ldlex.h". (OPTION_XXX): Removed. * emultempl/pe.em (OPTION_XXX): Removed. * emultempl/pep.em (OPTION_XXX): Likewise. * emultempl/ticoff.em: Include "ldlex.h". (OPTION_XXX): Removed. * emultempl/vms.em: Include "ldlex.h". (OPTION_XXX): Removed. * emultempl/xtensaelf.em (elf32xtensa_size_opt, elf32xtensa_no_literal_movement, elf32xtensa_abi): Moved out of PARSE_AND_LIST_PROLOGUE. (PARSE_AND_LIST_PROLOGUE): Removed.	3 years ago
Nick Clifton	bfdd2ca621	Updated translations for various sub-directories	3 years ago
H.J. Lu	16666ccc91	Update x86-64: Add -z mark-plt and -z nomark-plt Pass --hash-style=both to ld for -z mark-plt tests to support linker configured with --enable-default-hash-style=gnu. * testsuite/ld-x86-64/mark-plt-1b-x32.d: Pass --hash-style=both to ld. * testsuite/ld-x86-64/mark-plt-1b.d: Likewise. * testsuite/ld-x86-64/mark-plt-1d-x32.d: Likewise. * testsuite/ld-x86-64/mark-plt-1d.d: Likewise.	3 years ago
Xi Ruoyao	6590ec8097	LoongArch: Adapt R_LARCH_{PCALA,GOT,TLS_IE,TLS_DESC}64_* handling per psABI v2.30 In LoongArch psABI v2.30, an offset (-8 for LO20 and -12 for HI12) should be applied on PC for these reloc types to avoid wrong relocation when the instruction sequence crosses a page boundary. The lld linker has already adapted the change. Make it for the bfd linker too. Link: https://github.com/loongson/la-abi-specs/releases/v2.30 Link: https://github.com/loongson-community/discussions/issues/17 Link: https://github.com/llvm/llvm-project/pull/73387 Signed-off-by: Xi Ruoyao <xry111@xry111.site>	3 years ago
Nick Clifton	e775d3a9b7	Change version to 2.42.50 and regenerate files	3 years ago
Nick Clifton	299b91cd85	Add markers for 2.42 branch	3 years ago
mengqinggang	156a2edbdb	LoongArch: Fix relaxation overflow caused by section alignment When deleting NOP instructions addend by .align at second pass, this may cause the PC decrease but the symbol address to remain unchanged due to section alignment. To solve this question, we subtract a maximux alignment of all sections like RISC-V.	3 years ago
changjiachen	2bee95b73c	LoongArch: ld: Adjusted some code order in relax.exp. ld/testsuite/ChangeLog: * ld/testsuite/ld-loongarch-elf/relax.exp: Modify test.	3 years ago
H.J. Lu	f68c9d09a3	ld: Add --enable-mark-plt configure option Add --enable-mark-plt linker configure option to mark PLT entries with DT_X86_64_PLT, DT_X86_64_PLTSZ and DT_X86_64_PLTENT dynamic tags by default. * NEWS: Mention -z mark-plt/-z nomark-plt and --enable-mark-plt. * config.in: Regenerated. * configure: Likewise. * configure.ac: Add --enable-mark-plt. (DEFAULT_LD_Z_MARK_PLT): New AC_DEFINE_UNQUOTED. * emulparams/x86-64-plt.sh (PARSE_AND_LIST_OPTIONS_X86_64_PLT): Support DEFAULT_LD_Z_MARK_PLT. * emultempl/elf-x86.em (elf_x86_64_before_parse): New function. (LDEMUL_BEFORE_PARSE): New. Set to elf_x86_64_before_parse for x86-64 targets.	3 years ago
H.J. Lu	9167304255	elf: Add elf_backend_add_glibc_version_dependency When -z mark-plt is used to add DT_X86_64_PLT, DT_X86_64_PLTSZ and DT_X86_64_PLTENT, the r_addend field of the R_X86_64_JUMP_SLOT relocation stores the offset of the indirect branch instruction. However, glibc versions which don't have this commit in glibc 2.36: commit f8587a61892cbafd98ce599131bf4f103466f084 Author: H.J. Lu <hjl.tools@gmail.com> Date: Fri May 20 19:21:48 2022 -0700 x86-64: Ignore r_addend for R_X86_64_GLOB_DAT/R_X86_64_JUMP_SLOT According to x86-64 psABI, r_addend should be ignored for R_X86_64_GLOB_DAT and R_X86_64_JUMP_SLOT. Since linkers always set their r_addends to 0, we can ignore their r_addends. Reviewed-by: Fangrui Song <maskray@google.com> won't ignore the r_addend value in the R_X86_64_JUMP_SLOT relocation. Although this commit has been backported to glibc 2.33/2.34/2.35 release branches, it is safer to require glibc 2.36 for such binaries. Extend the glibc version dependency of GLIBC_ABI_DT_RELR for DT_RELR to also add GLIBC_2.36 version dependency for -z mark-plt on the shared C library if it provides a GLIBC_2.XX symbol version. * elflink.c (elf_find_verdep_info): Moved to ... * elf-bfd.h (elf_find_verdep_info): Here. (elf_backend_data): Add elf_backend_add_glibc_version_dependency. (_bfd_elf_link_add_glibc_version_dependency): New function. (_bfd_elf_link_add_dt_relr_dependency): Likewise. * elf64-x86-64.c (elf_x86_64_add_glibc_version_dependency): Likewise. (elf_backend_add_glibc_version_dependency): New. * elflink.c (elf_link_add_dt_relr_dependency): Renamed to ... (elf_link_add_glibc_verneed): This. Modified to support other glibc dependencies. (_bfd_elf_link_add_glibc_version_dependency): Likewise. (_bfd_elf_link_add_dt_relr_dependency): Likewise. (bfd_elf_size_dynamic_sections): Call elf_backend_add_glibc_version_dependency instead of elf_link_add_dt_relr_dependency. * elfxx-target.h (elf_backend_add_glibc_version_dependency): New. (elfNN_bed): Add elf_backend_add_glibc_version_dependency. ld/ * testsuite/ld-x86-64/mark-plt-1a.rd: New file. * testsuite/ld-x86-64/mark-plt-1b.rd: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run -z mark-plt test for GLIBC_2.36 dependency.	3 years ago
H.J. Lu	2e93abb858	x86: Don't check R_386_NONE nor R_X86_64_NONE Update x86 ELF linker to skip R_386_NONE/R_X86_64_NONE when scanning relocations. bfd/ * PR ld/31047 * elf32-i386.c (elf_i386_scan_relocs): Don't check R_386_NONE. * elf64-x86-64.c (elf_x86_64_scan_relocs): Don't check R_X86_64_NONE. ld/ * PR ld/31047 * testsuite/ld-i386/i386.exp: Run PR ld/31047 test. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/pr31047.d: New file. * testsuite/ld-x86-64/pr31047-x32.d: Likewise. * testsuite/ld-x86-64/pr31047.d: Likewise. * testsuite/ld-x86-64/pr31047a.s: Likewise. * testsuite/ld-x86-64/pr31047b.s: Likewise.	3 years ago
Sergey Bugaev	950b68acd4	Add support for the aarch64-gnu target (GNU/Hurd on AArch64) Also recognized are aarch64-*-gnu tagrets, e.g. aarch64-pc-gnu or aarch64-unknown-gnu. The ld/emulparams/aarch64gnu.sh file is (for now) identical to aarch64fbsd.sh, or to aarch64linux.sh with Linux-specific logic removed; and mainly different from the generic aarch64elf.sh in that it does not set EMBEDDED=yes. Coupled with a corresponding GCC patch, this produces a toolchain that can sucessfully build working binaries targeting aarch64-gnu. Signed-off-by: Sergey Bugaev <bugaevc@gmail.com>	3 years ago
H.J. Lu	c9eb960580	ld: Adjust x86 and x86-64 tests for -z mark-plt To support -z mark-plt enabled by default, adjust x86 tests to accept non-zero r_addend for JUMP_SLOT relocation and pass -z nomark-plt to x86-64 tests if -z mark-plt changes the expected outputs. * testsuite/ld-elf/indirect-extern-access-2.rd: Allow non-zero r_addend for JUMP_SLOT relocation. * testsuite/ld-elf/pr23161d.rd: Likewise. * testsuite/ld-ifunc/ifunc-25c-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-16-x86-64-now.d: Pass -z nomark-plt to linker. * testsuite/ld-ifunc/ifunc-16-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-2-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-20-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-x86-64.d: Likewise. * testsuite/ld-ifunc/pr17154-x86-64-now.d: Likewise. * testsuite/ld-ifunc/pr17154-x86-64.d: Likewise. * testsuite/ld-x86-64/dt-relr-1a-x32.d: Likewise. * testsuite/ld-x86-64/dt-relr-1a.d: Likewise. * testsuite/ld-x86-64/dt-relr-1b-x32.d: Likewise. * testsuite/ld-x86-64/dt-relr-1b.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2a-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2a.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3a-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3a.d: Likewise. * testsuite/ld-x86-64/pr19636-2d.d: Likewise. * testsuite/ld-x86-64/pr19636-2e.d: Likewise. * testsuite/ld-x86-64/pr19636-2f.d: Likewise. * testsuite/ld-x86-64/pr19636-2l.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Pass -z nomark-plt to linker in 6 tests.	3 years ago
Alan Modra	c217aed574	PR31120, ld-scripts/fill2 fails when bfd_vma is 32 bits The ld lexer converts strings to integers without overflow checking, so I don't think there is any problem in truncating an integer that exceeds the size of a bfd_vma rather than using (bfd_vma) -1. PR 31120 * ldlex.l: Don't use bfd_scan_vma for integer conversion, use strtoull.	3 years ago
Alan Modra	fd67aa1129	Update year range in copyright notice of binutils files Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out /po/.pot which we don't update frequently.	3 years ago
mengqinggang	e493ba6255	LoongArch: Fix linker generate PLT entry for data symbol With old "medium" code model, we call a function with a pair of PCALAU12I and JIRL instructions. The assembler produces something like: 8: 1a00000c pcalau12i $t0, 0 8: R_LARCH_PCALA_HI20 g c: 4c000181 jirl $ra, $t0, 0 c: R_LARCH_PCALA_LO12 g The linker generates a "PLT entry" for data without any diagnostic. If "g" is a data symbol and ld with -shared option, it may load two instructions in the PLT. Without -shared option, loongarch_elf_adjust_dynamic_symbol can delete PLT entry. For R_LARCH_PCALA_HI20 relocation, linker only generate PLT entry for STT_FUNC and STT_GNU_IFUNC symbols.	4 years ago
Lulu Cai	06bfdc6e5e	LoongArch: Fix loongarch-elf target ld testsuite failure The loongarch-elf target does not support SHARED and PIE, so this target is skipped for some tests that require these options.	3 years ago
changjiachen	90827b4eef	LoongArch: ld: Add support for tls le relax. Add tls le relax related testsuites in ld. The new test cases are mainly tested in three aspects: 1. tls le relax function correctness test. 2. tls le relax boundary check test. 3. tls le relax function compatibility test. ld/testsuite/ChangeLog: * ld/testsuite/ld-loongarch-elf/relax.exp: Modify test. * ld/testsuite/ld-loongarch-elf/old-tls-le.s: New test. * ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s: Likewise. * ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-new.s: Likewise. * ld/testsuite/ld-loongarch-elf/relax-tls-le.s: Likewise. * ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-old.s: Likewise.	3 years ago
H.J. Lu	a6d0019eb7	ld: Mention support for Intel APX relocations in NEWS	3 years ago
H.J. Lu	a533c8df59	x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESC For add name@gottpoff(%rip), %reg mov name@gottpoff(%rip), %reg add # define R_X86_64_CODE_4_GOTTPOFF 44 and for lea name@tlsdesc(%rip), %reg add # define R_X86_64_CODE_4_GOTPC32_TLSDESC 45 if the instruction starts at 4 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF and R_X86_64_GOTPC32_TLSDESC, respectively. Linker can covert GOTTPOFF to add $name@tpoff, %reg mov $name@tpoff, %reg and GOTPC32_TLSDESC to mov $name@tpoff, %reg mov name@gottpoff(%rip), %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_assemble): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF. (output_insn): Don't add empty REX prefix with REX2 prefix. (output_disp): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_apply_fix): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC if ixp->fx_tcbit3 is set. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * testsuite/gas/i386/x86-64-gottpoff.d: New file. * testsuite/gas/i386/x86-64-gottpoff.s: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.d: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.s: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC ld/ * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC tests.	3 years ago
H.J. Lu	3d5a60de52	x86-64: Add R_X86_64_CODE_4_GOTPCRELX For mov name@GOTPCREL(%rip), %reg test %reg, name@GOTPCREL(%rip) binop name@GOTPCREL(%rip), %reg where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions, add # define R_X86_64_CODE_4_GOTPCRELX 43 if the instruction starts at 4 bytes before the relocation offset. It similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX as R_X86_64_GOTPCREL or convert the above instructions to lea name(%rip), %reg mov $name, %reg test $name, %reg binop $name, %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTPCRELX. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_convert_load_reloc): Handle R_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * write.h (fix): Add fx_tcbit3. Change fx_unused to 1 bit. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (tc_gen_reloc): Likewise. (output_disp): Set fixP->fx_tcbit3 for REX2 prefix. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTPCRELX if fixp->fx_tcbit3 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (TC_FORCE_RELOCATION_ABS): Likewise. * testsuite/gas/i386/x86-64-gotpcrel.s: Add tests for R_X86_64_CODE_4_GOTPCRELX. * testsuite/gas/i386/x86-64-localpic.s: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Updated. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTPCRELX. ld/ * testsuite/ld-x86-64/apx-load1.s: New file. * testsuite/ld-x86-64/apx-load1a.d: Likewise. * testsuite/ld-x86-64/apx-load1b.d: Likewise. * testsuite/ld-x86-64/apx-load1c.d: Likewise. * testsuite/ld-x86-64/apx-load1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run apx-load1a, apx-load1b, apx-load1c and apx-load1d.	3 years ago
Nelson Chu	73d931e560	RISC-V: PR31179, The SET/ADD/SUB fix breaks ABI compatibility with 2.41 objects * Problematic fix commit, `2029e13917` RISC-V: Clarify the behaviors of SET/ADD/SUB relocations * Bugzilla, https://sourceware.org/bugzilla/show_bug.cgi?id=31179#c5 The addend of SUB_ULEB128 should be zero if using .uleb128, but we make it non-zero by accident in assembler before. This causes troubles by applying the above commit, since the calculation is changed to support .reloc SUB relocations with non-zero addend. We encourage people to rebuild their stuff to get the non-zero addend of SUB_ULEB128, but that might need some times, so report warnings to inform people need to rebuild their stuff if --check-uleb128 is enabled. Since the failed .reloc cases for ADD/SET/SUB/ULEB128 are rarely to use, it may acceptable that stop supproting them until people rebuld their stuff, maybe half-year or a year later. Or maybe we should teach people that don't write the .reloc R_RISCV_SUB* with non-zero constant, and then report warnings/errors in assembler. bfd/ * elfnn-riscv.c (perform_relocation): Ignore the non-zero addend of R_RISCV_SUB_ULEB128. (riscv_elf_relocate_section): Report warnings to inform people need to rebuild their stuff if --check-uleb128 is enabled. So that can get the right non-zero addend of R_RISCV_SUB_ULEB128. * elfxx-riscv.h (struct riscv_elf_params): Added bool check_uleb128. ld/ * NEWS: Updated. * emultempl/riscvelf.em: Added linker risc-v target options, --[no-]check-uleb128, to enable/disable checking if the addend of uleb128 is non-zero or not. So that people will know they need to rebuild the objects with binutils 2.42 and up, to get the right zero addend of SUB_ULEB128 relocation, or they may get troubles if using .reloc. * ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * ld/testsuite/ld-riscv-elf/pr31179*: New test cases.	3 years ago
Lulu Cai	d27473e7c5	LoongArch: Add testsuit for DESC and tls transition and tls relaxation.	3 years ago
mengqinggang	ae296cc452	LoongArch: Add support for TLS LD/GD/DESC relaxation The pcalau12i + addi.d of TLS LD/GD/DESC relax to pcaddi. Relaxation is only performed when the TLS model transition is not possible.	3 years ago
mengqinggang	c3d507aba3	LoongArch: Add support for the third expression of .align for R_LARCH_ALIGN If the symbol index is not zero, the addend is used to represent the first and the third expressions of the .align. The lowest 8 bits are used to represent the first expression. Other bits are used to represent the third expression. The addend of R_LARCH_ALIGN for ".align 5, ,4" is 0x405. The addend of R_LARCH_ALIGN for ".balign 32, ,4" is 0x405.	3 years ago
Rainer Orth	333a6b1a63	ld: Add lib32 directories for 32-bit emulation on FreeBSD/amd64 GNU ld currently fails to link 32-bit executables on FreeBSD/amd64 when the linked libraries have dependencies on shared objects themselves: $ gcc -m32 -o ei ei.c -lexecinfo /var/gcc/binutils/amd64/lib/gcc/amd64-pc-freebsd14.0/13.2.0/../../../../amd64-pc-freebsd14.0/bin/ld: warning: libelf.so.2, needed by /usr/lib/../lib32/libexecinfo.so, not found (try using -rpath or -rpath-link) /var/gcc/binutils/amd64/lib/gcc/amd64-pc-freebsd14.0/13.2.0/../../../../amd64-pc-freebsd14.0/bin/ld: /usr/lib/../lib32/libexecinfo.so: undefined reference to `elf_begin@R1.0' [...] Fixed by handling FreeBSD/amd64 like Linux/x86. Tested on amd64-pc-freebsd14.0.	3 years ago
Torbjörn SVENSSON	8ea1e363b9	ld: Print 0 size in B and not in GB When using --print-memory-usage, the printed size can be zero and in that case, the unit should be B and not GB. ld/ * ldlang.c (lang_print_memory_size) Print 0 B instead of 0 GB. * testsuite/ld-scripts/print-memory-usage-1.l: Validate emplty region. * testsuite/ld-scripts/print-memory-usage-1.t: Define empty region. Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>	3 years ago
Alan Modra	4cc1f41cfa	PR31162, Memory Leak in ldwrite.c This isn't a particularly worrying memory leak, but fix it anyway. PR 31162 * ldwrite.c (build_link_order): Use bfd_alloc rather than xmalloc. Add %E to error messages.	3 years ago
mengqinggang	784d5a936a	LoongArch: Add call36 and tail36 pseudo instructions for medium code model For tail36, it is necessary to explicitly indicate the temporary register. Therefore, the compiler and users will know that the tail will use a register. call36 func pcalau18i $ra, %call36(func) jirl $ra, $ra, 0; tail36 $t0, func pcalau18i $t0, %call36(func) jirl $zero, $t0, 0;	3 years ago
mengqinggang	dc5f359ed6	LoongArch: Add new relocation R_LARCH_CALL36 R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and these two instructions must adjacent. The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs.	3 years ago
Georg-Johann Lay	d51cd0f64c	PR31177: Let region text start at __TEXT_REGION_ORIGIN___ The start of MEMORY region text currently starts hard-coded at 0. The linker can produce more exact diagnostics when it knows the exact placements of the memory regions. For some old devices, program memory starts at 0x8000, so allow to specify program memory start at __TEXT_REGION_ORIGIN__ similar to how the data region is described. If ok, please apply to master. This one is also fine to back-port. Johann -- AVR: Use __TEXT_REGION_ORIGIN__ as start for MEMORY region text. ld/ PR 31177 * scripttempl/avr.sc (__TEXT_REGION_ORIGIN__): New symbol. (MEMORY): Use as start address for the text region.	3 years ago
Georg-Johann Lay	a5a863b4b9	Addendum to PR31124 This is a small addendum to PR31124 "rodata in flash for more AVR devices". It adds some symbols so the startup code can set a lock on the FLMAP bit field as specified by the user. New symbols are introduced because otherwise, all the computations / decisions would have to be performed at run-time. It approved, please apply to master. Johann -- ld/ PR 31124 * scripttempl/avr.sc: Adjust comments. [MAYBE_FLMAP]: Add symbols __flmap_value and __flmap_value_with_lock. Remove __flmap_lsl4.	3 years ago
Alan Modra	feb1ad0aec	regen ld POTFILES	3 years ago
H.J. Lu	63fc64a8d0	Update Make const_1_mode print $1 in AT&T syntax commit `b70a487d59` Author: Cui, Lili <lili.cui@intel.com> Date: Wed Dec 13 06:07:36 2023 +0000 Make const_1_mode print $1 in AT&T syntax changes disassembler output from d1 f8 sar %eax to d1 f8 sar $1,%eax Adjust pe-x86-64-6.od accordingly. * testsuite/ld-x86-64/pe-x86-64-6.od: Adjusted.	3 years ago

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