binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Thomas Hebb	16089f320a	opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblers Currently, the get_disassembler() implementations for riscv, csky, and rl78--and mep_print_insn() for mep--access ELF variants of union fields without first checking that the bfd actually represents an ELF. This causes undefined behavior and crashes when disassembling non-ELF files (the "binary" BFD, for example). Fix that.	4 years ago
Jan Beulich	36b124126b	x86: VFPCLASSSH is Evex.LLIG This also was mistakenly flagged as Evex.128.	4 years ago
Jan Beulich	bb80cf5b42	x86: VCMPSH is Evex.LLIG These were mistakenly flagged as Evex.128. Getting the LLIG status right for insns allowing for SAE is a prereq for planned further work.	4 years ago
Jan Beulich	177e42f83d	x86: drop stray CheckRegSize from VFPCLASSPH Like VFPCLASSP{S,D} it has only a single operand allowing multiple sizes, hence there are no pairs of operands to check for consistent size.	4 years ago
Jan Beulich	2f399d995b	x86: correct and simplify NOP disassembly It's not just REX.W which is ignored with opcode 0x90. The same goes for REX.R and REX.X as well as empty REX. None of these are forms of "xchg %eax,%eax" (which would mean zero-extending %eax to %rax), so they also shouldn't be disassembled this way. While there simplify things: A single hook function suffices, thus making it unnecessary to keep two expressions in sync. And checking ins->address_mode for mode_64bit also is unnecessary, as "rex" can be non-zero only in that case anyway.	4 years ago
Andreas Krebbel	69341966de	IBM zSystems: Add support for z16 as CPU name. So far z16 was identified as arch14. After the machine has been announced we can now add the real name. gas/ChangeLog: * config/tc-s390.c (s390_parse_cpu): Add z16 as alternate CPU name. * doc/as.texi: Add z16 and arch14 to CPU string list. * doc/c-s390.texi: Add z16 to CPU string list. opcodes/ChangeLog: * s390-mkopc.c (main): Enable z16 as CPU string in the opcode table.	4 years ago
Andrew Burgess	fbbb45cef5	opcodes/i386: partially implement disassembler style support This commit adds partial support for disassembler styling in the i386 disassembler. The i386 disassembler collects the instruction arguments into an array of strings, and then loops over the array printing the arguments out later on. The problem is that by the time we print the arguments out it's not obvious what the type of each argument is. Obviously this can be fixed, but I'd like to not do that as part of this commit, rather, I'd prefer to keep this commit as small as possible to get the basic infrastructure in place, then we can improve on this, to add additional styling, in later commits. For now then, I think this commit should correctly style mnemonics, some immediates, and comments. Everything else will be printed as plain text, which will include most instruction arguments, unless the argument is printed as a symbol, by calling the print_address_func callback. Ignoring colours, there should be no other user visible changes in the output of the disassembler in either objdump or gdb. opcodes/ChangeLog: * disassembler.c (disassemble_init_for_target): Set created_styled_output for i386 based targets. * i386-dis.c: Changed throughout to use fprintf_styled_func instead of fprintf_func.	5 years ago
Andrew Burgess	49d31dc98e	opcodes/riscv: implement style support in the disassembler Update the RISC-V disassembler to supply style information. This allows objdump to apply syntax highlighting to the disassembler output (when the appropriate command line flag is used). Ignoring colours, there should be no other user visible changes in the output of the disassembler in either objdump or gdb. opcodes/ChangeLog: * disassembler.c (disassemble_init_for_target): Set created_styled_output for riscv. * riscv-dis.c: Changed throughout to use fprintf_styled_func instead of fprintf_func.	5 years ago
Andrew Burgess	60a3da00bd	objdump/opcodes: add syntax highlighting to disassembler output This commit adds the _option_ of having disassembler output syntax highlighted in objdump. This option is _off_ by default. The new command line options are: --disassembler-color=off # The default. --disassembler-color=color --disassembler-color=extended-color I have implemented two colour modes, using the same option names as we use of --visualize-jumps, a basic 8-color mode ("color"), and an extended 8bit color mode ("extended-color"). The syntax highlighting requires that each targets disassembler be updated; each time the disassembler produces some output we now pass through an additional parameter indicating what style should be applied to the text. As updating all target disassemblers is a large task, the old API is maintained. And so, a user of the disassembler (i.e. objdump, gdb) must provide two functions, the current non-styled print function, and a new, styled print function. I don't currently have a plan for converting every single target disassembler, my hope is that interested folk will update the disassemblers they are interested in. But it is possible some might never get updated. In this initial series I intend to convert the RISC-V disassembler completely, and also do a partial conversion of the x86 disassembler. Hopefully having the x86 disassembler at least partial converted will allow more people to try this out easily and provide feedback. In this commit I have focused on objdump. The changes to GDB at this point are the bare minimum required to get things compiling, GDB makes no use of the styling information to provide any colors, that will come later, if this commit is accepted. This first commit in the series doesn't convert any target disassemblers at all (the next two commits will update some targets), so after this commit, the only color you will see in the disassembler output, is that produced from objdump itself, e.g. from objdump_print_addr_with_sym, where we print an address and a symbol name, these are now printed with styling information, and so will have colors applied (if the option is on). Finally, my ability to pick "good" colors is ... well, terrible. I'm in no way committed to the colors I've picked here, so I encourage people to suggest new colors, or wait for this commit to land, and then patch the choice of colors. I do have an idea about using possibly an environment variable to allow the objdump colors to be customised, but I haven't done anything like that in this commit, the color choices are just fixed in the code for now. binutils/ChangeLog: * NEWS: Mention new feature. * doc/binutils.texi (objdump): Describe --disassembler-color option. * objdump.c (disassembler_color): New global. (disassembler_extended_color): Likewise. (disassembler_in_comment): Likewise. (usage): Mention --disassembler-color option. (long_options): Add --disassembler-color option. (objdump_print_value): Use fprintf_styled_func instead of fprintf_func. (objdump_print_symname): Likewise. (objdump_print_addr_with_sym): Likewise. (objdump_color_for_disassembler_style): New function. (objdump_styled_sprintf): New function. (fprintf_styled): New function. (disassemble_jumps): Use disassemble_set_printf, and reset disassembler_in_comment. (null_styled_print): New function. (disassemble_bytes): Use disassemble_set_printf, and reset disassembler_in_comment. (disassemble_data): Update init_disassemble_info call. (main): Handle --disassembler-color option. include/ChangeLog: * dis-asm.h (enum disassembler_style): New enum. (struct disassemble_info): Add fprintf_styled_func field, and created_styled_output field. (disassemble_set_printf): Declare. (init_disassemble_info): Add additional parameter. (INIT_DISASSEMBLE_INFO): Add additional parameter. opcodes/ChangeLog: * dis-init.c (init_disassemble_info): Take extra parameter, initialize the new fprintf_styled_func and created_styled_output fields. * disassembler.c (disassemble_set_printf): New function definition.	5 years ago
H.J. Lu	801a7eab11	x86: Remove bfd_arch_l1om and bfd_arch_k1om Remove bfd_arch_l1om and bfd_arch_k1om since L1OM/K1OM support has been removed from gas, ld and opcodes. bfd/ * Makefile.am (ALL_MACHINES): Remove cpu-l1om.lo and cpu-k1om.lo. (ALL_MACHINES_CFILES): Remove cpu-l1om.c and cpu-k1om.c. * archures.c (bfd_mach_l1om): Removed. (bfd_mach_l1om_intel_syntax): Likewise. (bfd_mach_k1om): Likewise. (bfd_mach_k1om_intel_syntax): Likewise. (bfd_k1om_arch): Likewise. (bfd_l1om_arch): Likewise. (bfd_archures_list): Remove bfd_k1om_arch and bfd_l1om_arch references. * config.bfd (targ_selvecs): Remove l1om_elf64_vec. l1om_elf64_fbsd_vec, k1om_elf64_vec and k1om_elf64_fbsd_vec. (targ_archs): Remove bfd_l1om_arch and bfd_k1om_arch. * configure.ac (k1om_elf64_vec): Removed. (k1om_elf64_fbsd_vec): Likewise. (l1om_elf64_vec): Likewise. (l1om_elf64_fbsd_vec): Likewise. * cpu-k1om.c: Removed. * cpu-l1om.c: Likewise. * elf64-x86-64.c (elf64_l1om_elf_object_p): Removed. (elf64_k1om_elf_object_p): Likewise. (l1om_elf64_vec): Removed. (l1om_elf64_fbsd_vec): Likewise. (k1om_elf64_vec): Likewise. (k1om_elf64_fbsd_vec): Likewise. (ELF_TARGET_OS): Undefine. * targets.c (_bfd_target_vector): Remove k1om_elf64_vec, k1om_elf64_fbsd_vec, l1om_elf64_vec and l1om_elf64_fbsd_vec. * Makefile.in: Regenerate. * bfd-in2.h: Likewise. * configure: Likewise. opcodes/ * configure.ac: Remove bfd_arch_l1om/bfd_arch_k1om references. * disassemble.c (disassembler): Likewise. * configure: Regenerate.	4 years ago
Richard Sandiford	025f768ffc	aarch64: Relax check for RNG system registers FEAT_RNG is an optional Armv8.5-A extension, but it can be backported to earlier architectures as well. GAS previously made the RNG registers conditional on having both armv8.5-a and +rng, but only +rng should be required. This seems to be the only feature that was handled like this. opcodes/ * aarch64-opc.c (SR_RNG): Don't require V8_5. gas/ * testsuite/gas/aarch64/rng-1.s, testsuite/gas/aarch64/rng-1.d: New test.	4 years ago
Jan Beulich	1d1595b48b	RISC-V: correct FCVT.Q.L[U] While the spec isn't explicit about this, it pointing out the similarity with the D extension ought to extend to the ignoring of a meaningless rounding mode: "Note FCVT.D.W[U] always produces an exact result and is unaffected by rounding mode." Hence the chosen encodings also ought to match. Note that to avoid breaking existing code the forms with a 3rd operand are not removed, which means there continues to be a difference to FCVT.D.W[U].	4 years ago
Nick Alcock	caf606c90d	libtool.m4: fix the NM="/nm/over/here -B/option/with/path" case My previous nm patch handled all cases but one -- if the user set NM in the environment to a path which contained an option, libtool's nm detection tries to run nm against a copy of nm with the options in it: e.g. if NM was set to "nm --blargle", and nm was found in /usr/bin, the test would try to run "/usr/bin/nm --blargle /usr/bin/nm --blargle". This is unlikely to be desirable: in this case we should run "/usr/bin/nm --blargle /usr/bin/nm". Furthermore, as part of this nm has to detect when the passed-in $NM contains a path, and in that case avoid doing a path search itself. This too was thrown off if an option contained something that looked like a path, e.g. NM="nm -B../prev-gcc"; libtool then tries to run "nm -B../prev-gcc nm" which rarely works well (and indeed it looks to see whether that nm exists, finds it doesn't, and wrongly concludes that nm -p or whatever does not work). Fix all of these by clipping all options (defined as everything including and after the first " -") before deciding whether nm contains a path (but not using the clipped value for anything else), and then removing all options from the path-modified nm before looking to see whether that nm existed. NM=my-nm now does a path search and runs e.g. /usr/bin/my-nm -B /usr/bin/my-nm NM=/usr/bin/my-nm now avoids a path search and runs e.g. /usr/bin/my-nm -B /usr/bin/my-nm NM="my-nm -p../wombat" now does a path search and runs e.g. /usr/bin/my-nm -p../wombat -B /usr/bin/my-nm NM="../prev-binutils/new-nm -B../prev-gcc" now avoids a path search: ../prev-binutils/my-nm -B../prev-gcc -B ../prev-binutils/my-nm This seems to be all combinations, including those used by GCC bootstrap (which, before this commit, fails to bootstrap when configured --with-build-config=bootstrap-lto, because the lto plugin is now using --export-symbols-regex, which requires libtool to find a working nm, while also using -B../prev-gcc to point at the lto plugin associated with the GCC just built.) Regenerate all affected configure scripts. * libtool.m4 (LT_PATH_NM): Handle user-specified NM with options, including options containing paths.	5 years ago
Jan Beulich	526ca202fc	x86: drop L1OM special case from disassembler There wasn't any real support anyway: None of the sub-architecture specific insns were ever supported.	4 years ago
liuzhensong	5fb13d7ef4	gas:LoongArch: Fix segment error in compilation due to too long symbol name. Change "char buffer[8192];" into "char buffer = (char ) malloc(1000 + 6 * len_str);" in function loongarch_expand_macro_with_format_map. gas/ * config/tc-loongarch.c include/ * opcode/loongarch.h opcodes/ * loongarch-coder.c	4 years ago
liuzhensong	e36144c932	ubsan: loongarch : signed integer shift overflow. opcodes/ * loongarch-coder.c : int32_t ret = 0; ret <<= sizeof (ret) * 8 - len; ret >>= sizeof (ret) * 8 - len; ... Avoid ubsan warning.	5 years ago
Jan Beulich	c4d0963383	x86: also fold remaining multi-vector-size shift insns By slightly relaxing the checking in operand_type_register_match() we can fold the vector shift insns with an XMM source as well. While strictly speaking an overlap in just one size (see the code comment) is not enough (both operands could have multiple sizes with just a single common one), this is good enough for all templates we have, or which could sensibly / usefully appear (within the scope of the present operand matching model). Tightening this a little would be possible, but would require broadcast related information to be passed into the function.	4 years ago
Jan Beulich	a548407ec2	x86: drop stray CheckRegSize from VEXTRACT{F,I}32X4 They have only a single operand allowing multiple sizes, hence there are no pairs of operands to check for consistent size.	4 years ago
Jan Beulich	22c3694052	x86: fold certain AVX2 templates into their AVX counterparts Like for AVX512VL we can make the handling of operand sizes a little more flexible to allow reducing the number of templates we have.	4 years ago
Tsukasa OI	41d6ac5da6	RISC-V: Cache management instructions This commit adds 'Zicbom' / 'Zicboz' instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction classes. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN, MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL, MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros. * opcode/riscv.h (enum riscv_insn_class): Add new instruction classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add cache-block management instructions.	5 years ago
Tsukasa OI	3b374308d3	RISC-V: Prefetch hint instructions and operand set This commit adds 'Zicbop' hint instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction class. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for new operand type 'f' (32-byte aligned pseudo S-type immediate for prefetch hints). (validate_riscv_insn): Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I, MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W, MASK_PREFETCH_W): New macros. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZICBOP. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add handling for new operand type. * riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.	5 years ago
Jan Beulich	13ed231a0f	x86: never set i386_cpu_flags' "unused" field Setting this field risks cpu_flags_all_zero() mistakenly returning "false" when the object passed in was e.g. the result of ANDing together two objects which had the bit set, or ANDNing together an object with the field set and one with the field clear. While there also avoid setting CpuNo64: Like Cpu64 this is driven differently anyway and hence shouldn't be set anywhere by default. Note that the moving of the two items in i386-gen.c's cpu_flags[] is only for documentation purposes (and slight reducing of overhead), as the fields are sorted anyway upon program start.	4 years ago
Jan Beulich	ad9de929c3	x86: unify CPU flag on/off processing There's no need for the arbitrary special "unknown" token: Simply recognize the leading ~ and process everything else the same, merely recording whether to set individual fields to 1 or 0. While there exclude CpuIAMCU from CPU_UNKNOWN_FLAGS - CPU_IAMCU_FLAGS override cpu_arch_flags anyway when -march=iamcu is passed, and there's no reason to have the stray flag set even if no insn actually is keyed to it.	4 years ago
Jan Beulich	c085ab00c7	x86: drop L1OM/K1OM support from gas This was only rudimentary support anyway; none of the sub-architecture specific insns were ever supported.	4 years ago
Jan Beulich	648d04db39	x86: assorted IAMCU CPU checking fixes The checks done by check_cpu_arch_compatible() were halfway sensible only at the time where only L1OM support was there. The purpose, however, has always been to prevent bad uses of .arch (turning off the base CPU "feature" flag) while at the same time permitting extensions to be enabled / disabled. In order to achieve this (and to prevent regressions when L1OM and K1OM support are removed) - set CpuIAMCU in CPU_IAMCU_FLAGS, - adjust the IAMCU check in the function itself (the other two similarly broken checks aren't adjusted as they're slated to be removed anyway), - avoid calling the function for extentions (which would never have the base "feature" flag set), - add a new testcase actually exercising ".arch iamcu" (which would also regress with the planned removal).	4 years ago
Simon Marchi	e316110609	opcodes: handle bfd_amdgcn_arch in configure script There isn't an actual opcodes implementation for the AMDGCN arch (yet), this is just the bare minimum to get $ ./configure --target=amdgcn-hsa-amdhsa --disable-gas $ make all-binutils working later in this series. opcodes/ChangeLog: * configure.ac: Handle bfd_amdgcn_arch. * configure: Re-generate. Change-Id: Ib7d7c5533a803ed8b2a293e9275f667ed781ce79	4 years ago
Alan Modra	dc3ff92676	Delete PowerPC macro insn support Let's hope this stays dead, but it's here as a patch separate from those that removed use of powerpc_macros just in case it needs to be resurrected. include/ * opcode/ppc.h (struct powerpc_macro): Delete declaration. (powerpc_macros, powerpc_num_macros): Likewise.. opcodes/ * ppc-opc.c (powerpc_macros, powerpc_num_macros): Delete. gas/ * config/tc-ppc.c (ppc_macro): Delete function. (ppc_macro_hash): Delete. (ppc_setup_opcodes, md_assemble): Delete macro support.	4 years ago
Alan Modra	8736318e4e	PowerPC SPE/SPE2 aliases in powerpc_macros * ppc-opc.c (powerpc_macros): Move "evsadd", "evssub", "evsabs", "evsnabs", "evsneg", "evsmul", "evsdiv", "evscmpgt", "evsgmplt", "evsgmpeq", "evscfui", "evscfsi", "evscfuf", "evscfsf", "evsctui", "evsctsi", "evsctuf", "evsctsf", "evsctuiz", "evsctsiz", "evststgt", "evststlt", "evststeq".. (powerpc_opcodes): ..to here. (powerpc_macros): Move "evdotphsssi", "evdotphsssia", "evdotpwsssi", and "evdotpwsssia".. (spe2_opcodes): ..to here.	4 years ago
Alan Modra	51ba92c795	PowerPC VLE extended instructions in powerpc_macros This moves VLE insn out of the macro table. "e_slwi" and "e_srwi" already exist in vle_opcodes as distinct instructions rather than encodings of e_rlwinm. opcodes/ * ppc-opc.c (vle_opcodes): Typo fix e_rlwinm operand. Add "e_inslwi", "e_insrwi", "e_rotlwi", "e_rotrwi", "e_clrlwi", "e_clrrwi", "e_extlwi", "e_extrwi", and "e_clrlslwi". (powerpc_macros): Delete same. Delete "e_slwi" and "e_srwi" too. gas/ * testsuite/gas/ppc/vle-simple-5.d: Update.	4 years ago
Alan Modra	f304c63d24	PowerPC32 extended instructions in powerpc_macros As for PowerPC64, move instructions to the main opcode table. opcodes/ * ppc-opc.c (insert_crwn, extract_crwn, insert_elwn, extract_elwn), (insert_erwn, extract_erwn, insert_erwb, extract_erwb), (insert_cslwn, extract_cslwb, insert_ilwb, extract_ilwn), (insert_irwb, extract_irwn, insert_rrwn, extract_rrwn), (insert_slwn, extract_slwn, insert_srwn, extract_srwn): New functions. (CRWn, ELWn, ERWn, ERWb, CSLWb, CSLWn, ILWn, ILWb, IRWn, IRWb), (RRWn, SLWn, SRWn): Define and add powerpc_operands entries. (MMB_MASK, MME_MASK, MSHMB_MASK): Define. (powerpc_opcodes): Add "inslwi", "insrwi", "rotrwi", "clrrwi", "slwi", "srwi", "extlwi", "extrwi", "sli", "sri" and corresponding record (ie. dot suffix) forms. (powerpc_macros): Delete same. gas/ * testsuite/gas/ppc/476.d: Update. * testsuite/gas/ppc/simpshft.d: Update.	4 years ago
Alan Modra	42952a9605	PowerPC64 extended instructions in powerpc_macros The extended instructions implemented in powerpc_macros aren't used by the disassembler. That means instructions like "sldi r3,r3,2" appear in disassembly as "rldicr r3,r3,2,61", which is annoying since many other extended instructions are shown. Note that some of the instructions moved out of the macro table to the opcode table won't appear in disassembly, because they are aliases rather than a subset of the underlying raw instruction. If enabled, rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many occurrences in the case of clrlsldi if n <= b was added to the extract functions.) The patch also fixes a small bug in opcode sanity checking. include/ * opcode/ppc.h (PPC_OPSHIFT_SH6): Define. opcodes/ * ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn), (insert_crdn, extract_crdn, insert_rrdn, extract_rrdn), (insert_sldn, extract_sldn, insert_srdn, extract_srdn), (insert_erdb, extract_erdb, insert_csldn, extract_csldb), (insert_irdb, extract_irdn): New functions. (ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb): Define and add associated powerpc_operands entries. (powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi", "sldi", "extldi", "clrlsldi", "insrdi" and corresponding record (ie. dot suffix) forms. (powerpc_macros): Delete same from here. gas/ * config/tc-ppc.c (insn_validate): Don't modify value passed to operand->insert for PPC_OPERAND_PLUS1 when calculating mask. Handle PPC_OPSHIFT_SH6. * testsuite/gas/ppc/prefix-reloc.d: Update. * testsuite/gas/ppc/simpshft.d: Update. ld/ * testsuite/ld-powerpc/elfv2so.d: Update. * testsuite/ld-powerpc/notoc.d: Update. * testsuite/ld-powerpc/notoc3.d: Update. * testsuite/ld-powerpc/tlsdesc2.d: Update. * testsuite/ld-powerpc/tlsget.d: Update. * testsuite/ld-powerpc/tlsget2.d: Update. * testsuite/ld-powerpc/tlsopt5.d: Update. * testsuite/ld-powerpc/tlsopt6.d: Update.	4 years ago
Alan Modra	b508e46bf9	PR28959, obdump doesn't disassemble mftb instruction Without a -M cpu option given, powerpc objdump defaults currently to -Mpower10 but -Many is also given. Commit `1ff6a3b8e5` regressed -Many disassembly of instructions that are encoded differently depending on cpu, such as mftb which has pre- and post-power4 encodings. PR 28959 * ppc-dis.c (lookup_powerpc): Revert 2021-05-28 change. Instead only look at deprecated PPC_OPCODE_RAW bit when -Many.	4 years ago
Maciej W. Rozycki	d17e797f5c	MIPS/opcodes: Fix alias annotation for branch instructions Correct issues with INSN2_ALIAS annotation for branch instructions: - regular MIPS BEQZ/L and BNEZ/L assembly instructions are idioms for BEQ/L and BNE/L respectively with the `rs' operand equal to $0, - microMIPS 32-bit BEQZ and BNEZ assembly instructions are idioms for BEQ and BNE respectively with the `rt' operand equal to $0, - regular MIPS BAL assembly instruction is an idiom for architecture levels of up to the MIPSr5 ISA and a machine instruction on its own from the MIPSr6 ISA up. Add missing annotation to BEQZ/L and BNEZ/L accordingly then and add a new entry for BAL for the MIPSr6 ISA, correcting a disassembly bug: $ mips-linux-gnu-objdump -m mips:isa64r6 -M no-aliases -d bal.o bal.o: file format elf32-tradlittlemips Disassembly of section .text: 00000000 <foo>: 0: 04110000 0x4110000 ... $ Add test cases accordingly. Parts for regular MIPS BEQZ/L and BNEZ/L instructions from Sagar Patel. 2022-03-06 Maciej W. Rozycki <macro@orcam.me.uk> binutils/ * testsuite/binutils-all/mips/mips1-branch-alias.d: New test. * testsuite/binutils-all/mips/mips1-branch-noalias.d: New test. * testsuite/binutils-all/mips/mips2-branch-alias.d: New test. * testsuite/binutils-all/mips/mips2-branch-noalias.d: New test. * testsuite/binutils-all/mips/mips32r6-branch-alias.d: New test. * testsuite/binutils-all/mips/mips32r6-branch-noalias.d: New test. * testsuite/binutils-all/mips/micromips-branch-alias.d: New test. * testsuite/binutils-all/mips/micromips-branch-noalias.d: New test. * testsuite/binutils-all/mips/mips-branch-alias.s: New test source. * testsuite/binutils-all/mips/micromips-branch-alias.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests. 2022-03-06 Sagar Patel <sagarmp@cs.unc.edu> Maciej W. Rozycki <macro@orcam.me.uk> opcodes/ * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions. * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and "bnez" instructions.	5 years ago
Tsukasa OI	9a9dfb6880	RISC-V: Fix mask for some fcvt instructions This commit fixes incorrect uses of mask values in 'fcvt' instruction family. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Fix incorrect uses of mask values in 'fcvt' instruction family.	5 years ago
Nick Clifton	36d285b9da	Updated Serbian translations for the bfd, gold, ld and opcodes directories	5 years ago
H.J. Lu	ce20459e16	x86: Add has_sib to struct instr_info Add has_sib to struct instr_info and use SIB info only if ins->has_sib is true. PR binutils/28892 * i386-dis.c (instr_info): Add has_sib. (get_sib): Set has_sib. (OP_E_memory): Replace havesib with ins->has_sib. (OP_VEX): Use ins->sib.index only if ins->has_sib is true.	5 years ago
Sergei Trofimovich	a532eb7277	microblaze: fix fsqrt collicion to build on glibc-2.35 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'. * microblaze-opc.h: Follow 'fsqrt' rename.	5 years ago
Nick Clifton	5fe73d4624	Update Bulgarian, French, Romaniam and Ukranian translation for some of the sub-directories	5 years ago
H.J. Lu	ad69b6b861	Regenerate Makefile.in files with automake 1.15.1 Regenerate Makefile.in files with the unmodified automake 1.15.1 to remove runstatedir = @runstatedir@ bfd/ * Makefile.in: Regenerate. binutils/ * Makefile.in: Regenerate. gas/ * Makefile.in: Regenerate. gold/ * Makefile.in: Regenerate. * testsuite/Makefile.in: Likewise. gprof/ * Makefile.in: Regenerate. ld/ * Makefile.in: Regenerate. opcodes/ * Makefile.in: Regenerate.	5 years ago
H.J. Lu	31b0378d53	Regenerate configure files with autoconf 2.69 Regenerate configure files with the unmodified autoconf 2.69 to remove --runstatedir=DIR modifiable per-process data [LOCALSTATEDIR/run] bfd/ * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gold/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.	5 years ago
Nick Clifton	f908e960c5	Change version number to 2.38.50 and regenerate files	5 years ago
Nick Clifton	a74e1cb344	Add markers for 2.38 branch	5 years ago
Mike Frysinger	ec7194506d	drop old unused stamp-h.in file This was needed by ancient versions of automake, but that hasn't been the case since at least automake-1.5, so punt this from the tree.	5 years ago
Nick Clifton	6c037fdbf0	Update the config.guess and config.sub files from the master repository and regenerate files.	5 years ago
Jan Beulich	ab31da6aff	x86: adjust struct instr_info field types Now that this lives on the stack, let's have it be a little less wasteful in terms of space. Switch boolean fields to "bool" (also when this doesn't change their size) and also limit the widths of "rex", "rex_used", "op_ad", and "op_index". Do a little bit of re-ordering as well to limit the number of padding holes.	5 years ago
Jan Beulich	71b94817f3	x86: drop index16 field There's a single use on a generally infrequently taken code path. Put the necessary conditional there instead.	5 years ago
Jan Beulich	e564475af1	x86: drop most Intel syntax register name arrays By making use of, in particular, oappend_maybe_intel() there's no need for this redundant set of static data.	5 years ago
Jan Beulich	e1f9fbb8ad	x86: fold variables in memory operand index handling There's no real need for the pseudo-boolean "haveindex" or for separate 32-bit / 64-bit index pointers. Fold them into a single "indexes" and set that uniformly to AT&T names, compensating by emitting the register name via oappend_maybe_intel().	5 years ago
Jan Beulich	2a78304e29	x86: constify disassembler static data Now that the code is intended to be largely thread-safe, we'd better not have any writable static objects.	5 years ago
Jan Beulich	fd47eb1a30	x86: drop ymmxmm_mode This enumerator is not used by any table entry.	5 years ago

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4073 Commits (5890af36e5112bcbb8d7555e63570f68466e6944)