binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Chenghua Xu	716c08de28	[MIPS/GAS] Split Loongson CAM Instructions from loongson3a bfd/ * elfxx-mips.c (print_mips_ases): Add CAM extension. binutils/ * readelf.c (print_mips_ases): Add CAM extension. gas/ * NEWS: Mention Loongson Content Address Memory (CAM) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and OPTION_NO_LOONGSON_CAM. (md_longopts): Likewise. (mips_ases): Define availability for CAM. (mips_convert_ase_flags): Map ASE_LOONGSON_CAM to AFL_ASE_LOONGSON_CAM. (mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a. (md_show_usage): Add help for -mloongson-cam and -mno-loongson-cam. * doc/as.texi: Document -mloongson-cam, -mno-loongson-cam. * doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam, .set loongson-cam and .set noloongson-cam. * testsuite/gas/mips/loongson-3a-2.d: Move cam test to ... * testsuite/gas/mips/loongson-cam.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-3a-2.s: Move cam test to ... * testsuite/gas/mips/loongson-cam.s: Here. * testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag. * testsuite/gas/mips/mips.exp: Run loongson-cam test. include/ * elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM. * opcode/mips.h (ASE_LOONGSON_CAM): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add CAM to loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-cam option. (print_mips_disassembler_options): Document -M loongson-cam. * mips-opc.c (LCAM): New macro. (mips_opcodes): Replace IL2F\|IL3A marking with LCAM for CAM instructions.	8 years ago
Alan Modra	9cf7e5687f	Use operand->extract to provide defaults for optional PowerPC operands Most optional operands to powerpc instructions use a default value of zero, but there are a few exceptions. Those have been handled by PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table for the default value, smuggled in the shift field. This patch changes that to using the operand extract function to provide non-zero defaults. I've also moved the code determining whether optional operands are provided or omitted, to the point the first optional operand is seen, and allowed for the possibility of optional base register operands in a future patch. The patch does change the error you get on invalid assembly like ld 3,4 You'll now see "missing operand" rather than "syntax error; end of line, expected `('". gas/ * config/tc-ppc.c (md_assemble): Delay counting of optional operands until one is encountered. Allow for the possibility of optional base regs, ie. PPC_OPERAND_PARENS. Call ppc_optional_operand_value with extra args. include/ * opcode/ppc.h (struct powerpc_operand): Correct "insert" comment. Mention use of "extract" function to provide default value. (PPC_OPERAND_OPTIONAL_VALUE): Delete. (ppc_optional_operand_value): Rewrite to use extract function. opcodes/ * ppc-dis.c (operand_value_powerpc): Init "invalid". (skip_optional_operands): Count optional operands, and update ppc_optional_operand_value call. * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg. (extract_vlensi): Likewise. (extract_fxm): Return default value for missing optional operand. (extract_ls, extract_raq, extract_tbr): Likewise. (insert_sxl, extract_sxl): New functions. (insert_esync, extract_esync): Remove Power9 handling and simplify. (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE flag and extra entry. (powerpc_operands <SXL>): Likewise, and use insert_sxl and extract_sxl.	8 years ago
John Darrington	7ba3ba91a3	S12Z: Move opcode header to public include directory. opcodes/ * s12z.h: Delete. * s12z-dis.c: Adjust path of included file. include/ * opcode/s12z.h: New file. gas/ * config/tc-s12z.c: Adjust path of included file.	8 years ago
claziss	b6523c37fb	[ARC] Update handling AUX-registers. Update aux-registers data-base, and accept aux-registers names with upper/lowercase names. opcode/ 2017-07-18 Claudiu Zissulescu <claziss@synopsys.com> * arc-regs.h: Update aux-registers. gas/ 2017-07-18 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (find_opcode_match): Accept uppercase aux-regs names. * testsuite/gas/arc/ld2.d: Update test. * testsuite/gas/arc/taux.d: Likewise. * testsuite/gas/arc/taux.s: Likewise. include/ 2017-07-18 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (ARC_OPCODE_ARCV1): Define.	8 years ago
Jim Wilson	eb41b24898	RISC-V: Set insn info fields correctly when disassembling. include/ * opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR) (INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE) (INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size fields. * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.	8 years ago
Andrew Jenner	b8891f8d62	Add support for the C_SKY series of processors. This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc. This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about. bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY. (BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise. * Makefile.in: Regenerated. * archures.c (enum bfd_architecture): Add bfd_arch_csky and related bfd_mach defines. (bfd_csky_arch): Declare. (bfd_archures_list): Add C-SKY. * bfd-in.h (elf32_csky_build_stubs): Declare. (elf32_csky_size_stubs): Declare. (elf32_csky_next_input_section: Declare. (elf32_csky_setup_section_lists): Declare. * bfd-in2.h: Regenerated. * config.bfd: Add C-SKY. * configure.ac: Likewise. * configure: Regenerated. * cpu-csky.c: New file. * elf-bfd.h (enum elf_target_id): Add C-SKY. * elf32-csky.c: New file. * libbfd.h: Regenerated. * reloc.c: Add C-SKY relocations. * targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare. (_bfd_target_vector): Add C-SKY target vector entries. binutils* readelf.c: Include elf/csky.h. (guess_is_rela): Handle EM_CSKY. (dump_relocations): Likewise. (get_machine_name): Likewise. (is_32bit_abs_reloc): Likewise. include * dis-asm.h (csky_symbol_is_valid): Declare. * opcode/csky.h: New file. opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c. * Makefile.in: Regenerated. * configure.ac: Add C-SKY. * configure: Regenerated. * csky-dis.c: New file. * csky-opc.h: New file. * disassemble.c (ARCH_csky): Define. (disassembler, disassemble_init_for_target): Add case for ARCH_csky. * disassemble.h (print_insn_csky, csky_get_disassembler): Declare. gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY. (TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise. * Makefile.in: Regenerated. * config/tc-csky.c: New file. * config/tc-csky.h: New file. * config/te-csky_abiv1.h: New file. * config/te-csky_abiv1_linux.h: New file. * config/te-csky_abiv2.h: New file. * config/te-csky_abiv2_linux.h: New file. * configure.tgt: Add C-SKY. * doc/Makefile.am (CPU_DOCS): Add entry for C-SKY. * doc/Makefile.in: Regenerated. * doc/all.texi: Set CSKY feature. * doc/as.texi (Overview): Add C-SKY options. (Machine Dependencies): Likewise. * doc/c-csky.texi: New file. * testsuite/gas/csky/: New test cases. ld Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations. (ecskyelf.c, ecskyelf_linux.c): New rules. * Makefile.in: Regenerated. * configure.tgt: Add C-SKY. * emulparams/cskyelf.sh: New file. * emulparams/cskyelf_linux.sh: New file. * emultempl/cskyelf.em: New file. * gen-doc.texi: Add C-SKY. * ld.texi: Likewise. (Options specific to C-SKY targets): New section. * testsuite/ld-csky/*: New tests.	8 years ago
Alex Chadwick	fa758a7046	PowerPC Improve support for Gekko & Broadway This is a relatively straightforward patch to improve support for the IBM Gekko and IBM Broadway processors. Broadway is functionally equivalent to the IBM 750CL, while Gekko's functionality is a subset of theirs. The patch simplifies this reality and adds -mgekko and -mbroadway as aliases for -m750cl. I didn't feel it was worth wasting a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of simplified mnemonics for special purpose register access. Notably, Broadway adds 4 additional IBAT and DBAT registers but these are not assigned sequential SPR numbers. gas/ * config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway. * doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * testsuite/gas/ppc/broadway.d, * testsuite/gas/ppc/broadway.s: New test for broadway. * testsuite/gas/ppc/ppc.exp: Run new test. include/ * opcode/ppc.h (PPC_OPCODE_750): Adjust comment. opcodes/ * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. (powerpc_init_dialect): Handle bfd_mach_ppc_750. * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to support disjointed BAT. (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. (XSPRGQR_MASK, GEKKO, BROADWAY): Define. (powerpc_opcodes): Add 750cl extended mnemonics for spr access.	8 years ago
Chenghua Xu	8095d2f70e	MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a The MMI instruction set has been implemented in many Loongson processors. There is a lot of software optimized for MMI. This patch splits MMI from loongson2f/3a, and adds GAS and disassembler options for MMI instructions. 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com> Maciej W. Rozycki <macro@mips.com> bfd/ * elfxx-mips.c (print_mips_ases): Add MMI extension. binutils/ * readelf.c (print_mips_ases): Add MMI extension. gas/ * NEWS: Mention MultiMedia extensions Instructions (MMI) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and OPTION_NO_LOONGSON_MMI. (md_longopts): Likewise. (mips_ases): Define availability for MMI. (mips_convert_ase_flags): Map ASE_LOONGSON_MMI to AFL_ASE_LOONGSON_MMI. (mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a. (md_show_usage): Add help for -mloongson-mmi and -mno-loongson-mmi. * doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi. * doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi, .set loongson-mmi and .set noloongson-mmi. * testsuite/gas/mips/loongson-2f.d: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-2f.s: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.s: Here. * testsuite/gas/mips/loongson-3a.d: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-3a.s: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.s: Here. * testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and loongson-3a-mmi tests. include/ * elf/mips.h (AFL_ASE_MMI): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI. * opcode/mips.h (ASE_LOONGSON_MMI): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-mmi option. (print_mips_disassembler_options): Document -M loongson-mmi. * mips-opc.c (LMMI): New macro. (mips_opcodes): Replace IL2F\|IL3A marking with LMMI for MMI instructions.	8 years ago
Tamar Christina	369c9167d4	Fix AArch64 encodings for by element instructions. Some instructions in Armv8-a place a limitation on FP16 registers that can be used as the register from which to select an element from. e.g. fmla restricts Rm to 4 bits when using an FP16 register. This restriction does not apply for all instructions, e.g. fcmla does not have this restriction as it gets an extra bit from the M field. Unfortunately, this restriction to S_H was added for all _Em operands before, meaning for a large number of instructions you couldn't use the full register file. This fixes the issue by introducing a new operand _Em16 which applies this restriction only when paired with S_H and leaves the _Em and the other qualifiers for _Em16 unbounded (i.e. using the full 5 bit range). Also the patch updates all instructions that should be affected by this. opcodes/ PR binutils/23192 * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. * aarch64-opc.c (operand_general_constraint_met_p, aarch64_print_operand): Likewise. * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, fmlal2, fmlsl2. (AARCH64_OPERANDS): Add Em2. gas/ PR binutils/23192 * config/tc-aarch64.c (process_omitted_operand, parse_operands): Add AARCH64_OPND_Em16 * testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper 16 registers. * testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise. * testsuite/gas/aarch64/advsimd-compnum.s: Likewise. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise. * testsuite/gas/aarch64/sve.d: Likewise. include/ PR binutils/23192 *opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.	8 years ago
Faraz Shahbazker	6f20c942c3	MIPS: Add Global INValidate ASE support Add support for the Global INValidate Application Specific Extension for Release 6 of the MIPS Architecture. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 187-191 bfd/ * elfxx-mips.c (print_mips_ases): Add GINV extension. binutils/ * readelf.c (print_mips_ases): Add GINV extension. gas/ * NEWS: Mention MIPS Global INValidate ASE support. * config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV. (md_longopts): Likewise. (mips_ases): Define availability for GINV. (mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV. (md_show_usage): Add help for -mginv and -mno-ginv. * doc/as.texinfo: Document -mginv, -mno-ginv. * doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and .set noginv. * testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV ASE. * testsuite/gas/mips/ase-errors-2.s: Likewise. * testsuite/gas/mips/ase-errors-1.l: Likewise. * testsuite/gas/mips/ase-errors-2.l: Likewise. * testsuite/gas/mips/ginv.d: New test. * testsuite/gas/mips/ginv-err.d: New test. * testsuite/gas/mips/ginv-err.l: New test stderr output. * testsuite/gas/mips/ginv.s: New test source. * testsuite/gas/mips/ginv-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. include/ * elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros. (AFL_ASE_MASK): Update to include AFL_ASE_GINV. * opcode/mips.h: Document "+\" operand format. (ASE_GINV): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and mips64r6 descriptors. (parse_mips_ase_option): Handle -Mginv option. (print_mips_disassembler_options): Document -Mginv. * mips-opc.c (decode_mips_operand) <+\>: New operand format. (GINV): New macro. (mips_opcodes): Define ginvi and ginvt.	8 years ago
Scott Egerton	730c31740a	MIPS: Add CRC ASE support Add support for the CRC Application Specific Extension for Release 6 of the MIPS Architecture. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 143-148 [2] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 165-170 ChangeLog: bfd/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * elfxx-mips.c (print_mips_ases): Add CRC. binutils/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * readelf.c (print_mips_ases): Add CRC. gas/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> Maciej W. Rozycki <macro@mips.com> * config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC. (md_longopts): Likewise. (md_show_usage): Add help for -mcrc and -mno-crc. (mips_ases): Define availability for CRC and CRC64. (mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC. * doc/as.texinfo: Document -mcrc, -mno-crc. * doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and .set no-crc. * testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC ASE. * testsuite/gas/mips/ase-errors-2.l: Likewise. * testsuite/gas/mips/ase-errors-1.s: Likewise. * testsuite/gas/mips/ase-errors-2.s: Likewise. * testsuite/gas/mips/crc.d: New test. * testsuite/gas/mips/crc64.d: New test. * testsuite/gas/mips/crc-err.d: New test. * testsuite/gas/mips/crc64-err.d: New test. * testsuite/gas/mips/crc-err.l: New test stderr output. * testsuite/gas/mips/crc64-err.l: New test stderr output. * testsuite/gas/mips/crc.s: New test source. * testsuite/gas/mips/crc64.s: New test source. * testsuite/gas/mips/crc-err.s: New test source. * testsuite/gas/mips/crc64-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. include/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * elf/mips.h (AFL_ASE_CRC): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_CRC. * opcode/mips.h (ASE_CRC): New macro. * opcode/mips.h (ASE_CRC64): Likewise. opcodes/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs. * mips-opc.c (CRC, CRC64): New macros. (mips_builtin_opcodes): Define crc32b, crc32h, crc32w, crc32cb, crc32ch and crc32cw for CRC. Define crc32d and crc32cd for CRC64.	8 years ago
Peter Bergner	98553ad33e	Remove fake operand handling for extended mnemonics. opcodes/ * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba, insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions. (insert_bab, extract_bab, insert_btab, extract_btab, insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions. (BAT, BBA VBA RBS XB6S): Delete macros. (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros. (BB, BD, RBX, XC6): Update for new macros. (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset, crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp, e_crnot, e_crclr, e_crset, e_crmove>: Likewise. * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands. include/ * opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro. gas/ * config/tc-ppc.c (md_assemble): Delete handling of fake operands. * testsuite/gas/ppc/common.s (crmove, cror, or., or, nor., nor): Add test of extended mnemonics. * testsuite/gas/ppc/common.d: Likewise. Don't match instruction offset. * testsuite/gas/ppc/spe.s (evor, evnor): Add test of extended mnemonics. * testsuite/gas/ppc/spe.d: Likewise. Don't match instruction offset.	8 years ago
Tamar Christina	f9830ec165	Implement Read/Write constraints on system registers on AArch64 This patch adds constraints for read and write only system registers with the msr and mrs instructions. The code will treat having both flags set and none set as the same. These flags add constraints that must be matched up. e.g. a system register with a READ only flag set, can only be used with mrs. If The constraint fails a warning is emitted. Examples of the warnings generated: test.s: Assembler messages: test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3' test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0' test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3' and disassembly notes: 0000000000000000 <main>: 0: d5130503 msr dbgdtrtx_el0, x3 4: d5130503 msr dbgdtrtx_el0, x3 8: d5330503 mrs x3, dbgdtrrx_el0 c: d5330503 mrs x3, dbgdtrrx_el0 10: d5180003 msr midr_el1, x3 ; note: writing to a read-only register. Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during disassembly the constraints are use to disambiguate between the two. An exact constraint match is always prefered over partial ones if available. As always the warnings can be suppressed with -w and also be made errors using warnings as errors. binutils/ PR binutils/21446 * doc/binutils.texi (-M): Document AArch64 options. gas/ PR binutils/21446 * testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test. * testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise. * testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise. * testsuite/gas/aarch64/sysreg-diagnostic.s: New. * testsuite/gas/aarch64/sysreg-diagnostic.l: New. * testsuite/gas/aarch64/sysreg-diagnostic.d: New. include/ PR binutils/21446 * opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New. opcodes/ PR binutils/21446 * aarch64-asm.c (opintl.h): Include. (aarch64_ins_sysreg): Enforce read/write constraints. * aarch64-dis.c (aarch64_ext_sysreg): Likewise. * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here. (F_REG_READ, F_REG_WRITE): New. * aarch64-opc.c (aarch64_print_operand): Generate notes for AARCH64_OPND_SYSREG. (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h. (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0, mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1, id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1, id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1, id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1, mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1, id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1, id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1, id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1, csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2, rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0, mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1, mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1, pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0. * aarch64-tbl.h (aarch64_opcode_table): Add constraints to msr (F_SYS_WRITE), mrs (F_SYS_READ).	8 years ago
Tamar Christina	7d02540ab7	Allow non-fatal errors to be emitted and for disassembly notes be placed on AArch64 This patch adds a new platform option "notes" that can be used to indicate if disassembly notes should be placed in the disassembly as comments. These notes can contain information about a failing constraint such as reading from a write-only register. The disassembly will not be blocked because of this but -M notes will emit a comment saying that the operation is not allowed. For assembly this patch adds a new non-fatal status for errors. This is essentially a warning. The reason for not creating an actual warning type is that this causes the interaction between the ordering of warnings and errors to be problematic. Currently the error buffer is almost always filled because of the way operands are matched during assembly. An earlier template may have put an error there that would only be displayed if no other template matches or generates a higher priority error. But by definition a warning is lower priority than a warning, so the error (which is incorrect if another template matched) will supersede the warning. By treating warnings as errors and only later relaxing the severity this relationship keeps working and the existing reporting infrastructure can be re-used. binutils/ PR binutils/21446 * doc/binutils.texi (-M): Document AArch64 options. * NEWS: Document notes and warnings. gas/ PR binutils/21446 * config/tc-aarch64.c (print_operands): Indicate no notes. (output_operand_error_record): Support non-fatal errors. (output_operand_error_report, warn_unpredictable_ldst, md_assemble): Likewise. include/ PR binutils/21446 * opcode/aarch64.h (aarch64_operand_error): Add non_fatal. (aarch64_print_operand): Support notes. opcodes/ PR binutils/21446 * aarch64-dis.c (no_notes: New. (parse_aarch64_dis_option): Support notes. (aarch64_decode_insn, print_operands): Likewise. (print_aarch64_disassembler_options): Document notes. * aarch64-opc.c (aarch64_print_operand): Support notes.	8 years ago
Tamar Christina	561a72d4dd	Modify AArch64 Assembly and disassembly functions to be able to fail and report why. This patch if the first patch in a series to add the ability to add constraints to system registers that an instruction must adhere to in order for the register to be usable with that instruction. These constraints can also be used to disambiguate between registers with the same encoding during disassembly. This patch adds a new flags entry in the sysreg structures and ensures it is filled in and read out during assembly/disassembly. It also adds the ability for the assemble and disassemble functions to be able to gracefully fail and re-use the existing error reporting infrastructure. The return type of these functions are changed to a boolean to denote success or failure and the error structure is passed around to them. This requires aarch64-gen changes so a lot of the changes here are just mechanical. gas/ PR binutils/21446 * config/tc-aarch64.c (parse_sys_reg): Return register flags. (parse_operands): Fill in register flags. gdb/ PR binutils/21446 * aarch64-tdep.c (aarch64_analyze_prologue, aarch64_software_single_step, aarch64_displaced_step_copy_insn): Indicate not interested in errors. include/ PR binutils/21446 * opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct. (aarch64_decode_insn): Accept error struct. opcodes/ PR binutils/21446 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean and take error struct. * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane, aarch64_ins_reglist, aarch64_ins_ldst_reglist, aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist, aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half, aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm, aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits, aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm, aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple, aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm, aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12, aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg, aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier, aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended, aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl, aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl, aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6, aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw, aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw, aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm, aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov, aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist, aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm, aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two, aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise. * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise. * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane, aarch64_ext_reglist, aarch64_ext_ldst_reglist, aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist, aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half, aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm, aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits, aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm, aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple, aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm, aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12, aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg, aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier, aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended, aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl, aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl, aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6, aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw, aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw, aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm, aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov, aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist, aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm, aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two, aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise. (determine_disassembling_preference, aarch64_decode_insn, print_insn_aarch64_word, print_insn_data): Take errors struct. (print_insn_aarch64): Use errors. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-gen.c (print_operand_inserter): Use errors and change type to boolean in aarch64_insert_operan. (print_operand_extractor): Likewise. * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.	8 years ago
Francois H. Theron	1678bd35a3	Fix error messages in the NFP sources when building for 32-bit targets. bfd * targets.c: Wrap nfp_elf64_vec in BFD64 ifdef. include * opcode/nfp.h: Use uint64_t instead of bfd_vma. opcodes * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.	8 years ago
Jim Wilson	e6f372ba66	RISC-V: Add missing hint instructions from RV128I. gas/ * testsuite/gas/riscv/c-zero-imm.d: Add more tests. * testsuite/gas/riscv/c-zero-imm.s: Likewise. * testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled future test for RV128 support. * testsuite/gas/riscv/c-zero-reg.s: Likewise. include/ * opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New. (MATCH_C_SRAI64, MASK_C_SRAI64): New. (MATCH_C_SLLI64, MASK_C_SLLI64): New. opcodes/ * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New. (match_c_slli64, match_srxi_as_c_srxi): New. (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli. <srli, srl, srai, sra>: Use match_srxi_as_c_srxi. <c.slli, c.srli, c.srai>: Use match_s_slli. <c.slli64, c.srli64, c.srai64>: New.	8 years ago
Peter Bergner	2ceb7719f7	Cleanup ppc code dealing with opcode dumps. include/ * opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned. (vle_num_opcodes): Likewise. (spe2_num_opcodes): Likewise. opcodes/ * ppc-opc.c (powerpc_num_opcodes): Likewise. (vle_num_opcodes): Likewise. (spe2_num_opcodes): Likewise. * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite initialization loop. (disassemble_init_powerpc) <vle_opcd_indices>: Likewise. (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize only once. gas/ * config/tc-ppc.c (ppc_setup_opcodes) <powerpc_opcodes>: Rewrite code to dump the entire opcode table. (ppc_setup_opcodes) <spe2_opcodes>: Likewise. (ppc_setup_opcodes) <vle_opcodes>: Likewise. Fix calculation of opcode index.	8 years ago
Francois H. Theron	fe944acf8f	This patch adds support to objdump for disassembly of NFP (Netronome Flow Processor) ELF files (.nffw) as well as some basic readelf support. bfd * Makefile.am: Added NFP files to build. * archures.c: Added bfd_arch_nfp * config.bfd: Added NFP support. * configure.ac: Added NFP support. * cpu-nfp.c: New, for NFP support. * elf-bfd.h: Added elf_section_info() * elf64-nfp.c: New, for NFP support. * po/SRC-POTFILES.in: Added NFP source files. * targets.c: Added nfp_elf64_vec * bfd-in2.h: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. binutils* readelf.c: Very basic support for EM_NFP and its section types. * testsuite/binutils-all/nfp: New directory. * testsuite/binutils-all/nfp/objdump.exp: New file. Run new tests. * testsuite/binutils-all/nfp/test2_ctx8.d: New file. * testsuite/binutils-all/nfp/test2_no-pc_ctx4.d: New file. * testsuite/binutils-all/nfp/test1.d: New file. * testsuite/binutils-all/nfp/nfp6000.nffw: New file. * testsuite/binutils-all/nfp/test2_nfp6000.nffw: New file. * NEWS: Mention the new support. include * dis-asm.h: Added print_nfp_disassembler_options prototype. * elf/common.h: Added EM_NFP, officially assigned. See Google Group Generic System V Application Binary Interface. * elf/nfp.h: New, for NFP support. * opcode/nfp.h: New, for NFP support. opcodes Makefile.am: Added nfp-dis.c. configure.ac: Added bfd_nfp_arch. disassemble.h: Added print_insn_nfp prototype. disassemble.c: Added ARCH_nfp and call to print_insn_nfp nfp-dis.c: New, for NFP support. po/POTFILES.in: Added nfp-dis.c to the list. Makefile.in: Regenerate. configure: Regenerate.	8 years ago
Alan Modra	c2bf1eecf9	Remove m88k support include/ * coff/internal.h: Remove m88k support. * coff/m88k.h: Delete. * opcode/m88k.h: Delete. bfd/ * Makefile.am: Remove m88k support. * aoutx.h: Likewise. * archures.c: Likewise. * coffcode.h: Likewise. * coffswap.h: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * cpu-ns32k.c: Likewise. * elf32-nds32.c: Likewise. * mach-o.c: Likewise. * netbsd-core.c: Likewise. * reloc.c: Likewise. * targets.c: Likewise. * coff-m88k.c: Delete. * cpu-m88k.c: Delete. * elf32-m88k.c: Delete. * hosts/m88kmach3.h: Delete. * m88kmach3.c: Delete. * m88kopenbsd.c: Delete. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * Makefile.am: Remove m88k support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * m88k-dis.c: Delete. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * MAINTAINERS (Mark Kettenis): Move to past maintainers. * testsuite/binutils-all/objdump.exp: Remove m88k support. gas/ * configure.ac: Remove m88k support. * config.in: Regenerate. * configure: Regenerate. ld/ * Makefile.am: Remove m88k support. * configure.host: Likewise. * configure.tgt: Likewise. * testsuite/ld-elf/sec-to-seg.exp: Likewise. * emulparams/m88kbcs.sh: Delete. * scripttempl/m88kbcs.sc: Delete. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.	8 years ago
Alan Modra	6793974daa	Remove i370 support include/ * elf/i370.h: Delete. * opcode/i370.h: Delete. bfd/ * Makefile.am: Remove i370 support. * archures.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * targets.c: Likewise. * cpu-i370.c: Delete. * elf32-i370.c: Delete. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * Makefile.am: Remove i370 support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * i370-dis.c: Delete. * i370-opc.c: Delete. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * readelf.c: Remove i370 support. * testsuite/binutils-all/objdump.exp: Likewise. gas/ * Makefile.am: Remove i370 support. * app.c: Likewise. * config/obj-elf.c: Likewise. * configure.tgt: Likewise. * doc/Makefile.am: Likewise. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Likewise. * testsuite/gas/elf/warn-2.s: Likewise. * testsuite/gas/lns/lns.exp: Likewise. * config/tc-i370.c: Delete. * config/tc-i370.h: Delete. * doc/c-i370.texi: Delete. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. ld/ * Makefile.am: Remove i370 support. * configure.tgt: Likewise. * testsuite/ld-elf/compressed1d.d: Likewise. * testsuite/ld-elf/group8a.d: Likewise. * testsuite/ld-elf/group8b.d: Likewise. * testsuite/ld-elf/group9a.d: Likewise. * testsuite/ld-elf/group9b.d: Likewise. * testsuite/ld-elf/merge.d: Likewise. * testsuite/ld-elf/pr12851.d: Likewise. * testsuite/ld-elf/pr12975.d: Likewise. * testsuite/ld-elf/pr13177.d: Likewise. * testsuite/ld-elf/pr13195.d: Likewise. * testsuite/ld-elf/pr17615.d: Likewise. * testsuite/ld-elf/pr21562a.d: Likewise. * testsuite/ld-elf/pr21562b.d: Likewise. * testsuite/ld-elf/pr21562c.d: Likewise. * testsuite/ld-elf/pr21562d.d: Likewise. * testsuite/ld-elf/pr21562i.d: Likewise. * testsuite/ld-elf/pr21562j.d: Likewise. * testsuite/ld-elf/pr21562k.d: Likewise. * testsuite/ld-elf/pr21562l.d: Likewise. * testsuite/ld-elf/pr21562m.d: Likewise. * testsuite/ld-elf/pr21562n.d: Likewise. * testsuite/ld-elf/pr22677.d: Likewise. * testsuite/lib/ld-lib.exp: Likewise. * emulparams/elf32i370.sh: Delete. * scripttempl/elfi370.sc: Delete. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.	8 years ago
Alan Modra	fceadf0951	Remove tahoe support include/ * opcode/tahoe.h: Delete. bfd/ * archures.c: Remove tahoe support. * config.bfd: Likewise. * configure.ac: Likewise. * hosts/tahoe.h: Delete. * bfd-in2.h: Regenerate. * configure: Regenerate. opcodes/ * configure.ac: Remove tahoe support. * configure: Regenerate. binutils/ * testsuite/binutils-all/objdump.exp: Remove tahoe support. gprof/ * Makefile.am: Remove tahoe support. * corefile.c: Likewise. * tahoe.c: Delete. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.	8 years ago
Alan Modra	a8eb42a8b7	Remove i860, i960, bout and aout-adobe targets Plus remove a few leftovers from the 29k support. include/ * aout/adobe.h: Delete. * aout/reloc.h: Delete. * coff/i860.h: Delete. * coff/i960.h: Delete. * elf/i860.h: Delete. * elf/i960.h: Delete. * opcode/i860.h: Delete. * opcode/i960.h: Delete. * aout/aout64.h (enum reloc_type): Trim off 29k and other unused values. * aout/ar.h (ARMAGB): Remove. * coff/internal.h (struct internal_aouthdr, struct internal_scnhdr, union internal_auxent): Remove i960 support. bfd/ * aout-adobe.c: Delete. * bout.c: Delete. * coff-i860.c: Delete. * coff-i960.c: Delete. * cpu-i860.c: Delete. * cpu-i960.c: Delete. * elf32-i860.c: Delete. * elf32-i960.c: Delete. * hosts/i860mach3.h: Delete. * Makefile.am: Remove i860, i960, bout, and adobe support. * archures.c: Remove i860 and i960 support. * coffcode.h: Likewise. * reloc.c: Likewise. * aoutx.h: Comment updates. * archive.c: Remove BOUT and i960 support. * bfd.c: Remove BOUT support. * coffswap.h: Remove i960 support. * config.bfd: Remove i860, i960 and adobe targets. * configure.ac: Remove adode, bout, i860, i960, icoff targets. * targets.c: Likewise. * ieee.c: Remove i960 support. * mach-o.c: Remove i860 support. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * opcodes/i860-dis.c: Delete. * opcodes/i960-dis.c: Delete. * Makefile.am: Remove i860 and i960 support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * ieee.c: Remove i960 support. * od-macho.c: Remove i860 support. * readelf.c: Remove i860 and i960 support. * testsuite/binutils-all/objcopy.exp: Likewise. * testsuite/binutils-all/objdump.exp: Likewise. * testsuite/lib/binutils-common.exp: Likewise. gas/ * config/aout_gnu.h: Delete. * config/tc-i860.c: Delete. * config/tc-i860.h: Delete. * config/tc-i960.c: Delete. * config/tc-i960.h: Delete. * doc/c-i860.texi: Delete. * doc/c-i960.texi: Delete. * testsuite/gas/i860/README.i860: Delete. * testsuite/gas/i860/bitwise.d: Delete. * testsuite/gas/i860/bitwise.s: Delete. * testsuite/gas/i860/branch.d: Delete. * testsuite/gas/i860/branch.s: Delete. * testsuite/gas/i860/bte.d: Delete. * testsuite/gas/i860/bte.s: Delete. * testsuite/gas/i860/dir-align01.d: Delete. * testsuite/gas/i860/dir-align01.s: Delete. * testsuite/gas/i860/dir-intel01.d: Delete. * testsuite/gas/i860/dir-intel01.s: Delete. * testsuite/gas/i860/dir-intel02.d: Delete. * testsuite/gas/i860/dir-intel02.s: Delete. * testsuite/gas/i860/dir-intel03-err.l: Delete. * testsuite/gas/i860/dir-intel03-err.s: Delete. * testsuite/gas/i860/dual01.d: Delete. * testsuite/gas/i860/dual01.s: Delete. * testsuite/gas/i860/dual02-err.l: Delete. * testsuite/gas/i860/dual02-err.s: Delete. * testsuite/gas/i860/dual03.d: Delete. * testsuite/gas/i860/dual03.s: Delete. * testsuite/gas/i860/fldst01.d: Delete. * testsuite/gas/i860/fldst01.s: Delete. * testsuite/gas/i860/fldst02.d: Delete. * testsuite/gas/i860/fldst02.s: Delete. * testsuite/gas/i860/fldst03.d: Delete. * testsuite/gas/i860/fldst03.s: Delete. * testsuite/gas/i860/fldst04.d: Delete. * testsuite/gas/i860/fldst04.s: Delete. * testsuite/gas/i860/fldst05.d: Delete. * testsuite/gas/i860/fldst05.s: Delete. * testsuite/gas/i860/fldst06.d: Delete. * testsuite/gas/i860/fldst06.s: Delete. * testsuite/gas/i860/fldst07.d: Delete. * testsuite/gas/i860/fldst07.s: Delete. * testsuite/gas/i860/fldst08.d: Delete. * testsuite/gas/i860/fldst08.s: Delete. * testsuite/gas/i860/float01.d: Delete. * testsuite/gas/i860/float01.s: Delete. * testsuite/gas/i860/float02.d: Delete. * testsuite/gas/i860/float02.s: Delete. * testsuite/gas/i860/float03.d: Delete. * testsuite/gas/i860/float03.s: Delete. * testsuite/gas/i860/float04.d: Delete. * testsuite/gas/i860/float04.s: Delete. * testsuite/gas/i860/form.d: Delete. * testsuite/gas/i860/form.s: Delete. * testsuite/gas/i860/i860.exp: Delete. * testsuite/gas/i860/iarith.d: Delete. * testsuite/gas/i860/iarith.s: Delete. * testsuite/gas/i860/ldst01.d: Delete. * testsuite/gas/i860/ldst01.s: Delete. * testsuite/gas/i860/ldst02.d: Delete. * testsuite/gas/i860/ldst02.s: Delete. * testsuite/gas/i860/ldst03.d: Delete. * testsuite/gas/i860/ldst03.s: Delete. * testsuite/gas/i860/ldst04.d: Delete. * testsuite/gas/i860/ldst04.s: Delete. * testsuite/gas/i860/ldst05.d: Delete. * testsuite/gas/i860/ldst05.s: Delete. * testsuite/gas/i860/ldst06.d: Delete. * testsuite/gas/i860/ldst06.s: Delete. * testsuite/gas/i860/pfam.d: Delete. * testsuite/gas/i860/pfam.s: Delete. * testsuite/gas/i860/pfmam.d: Delete. * testsuite/gas/i860/pfmam.s: Delete. * testsuite/gas/i860/pfmsm.d: Delete. * testsuite/gas/i860/pfmsm.s: Delete. * testsuite/gas/i860/pfsm.d: Delete. * testsuite/gas/i860/pfsm.s: Delete. * testsuite/gas/i860/pseudo-ops01.d: Delete. * testsuite/gas/i860/pseudo-ops01.s: Delete. * testsuite/gas/i860/regress01.d: Delete. * testsuite/gas/i860/regress01.s: Delete. * testsuite/gas/i860/shift.d: Delete. * testsuite/gas/i860/shift.s: Delete. * testsuite/gas/i860/simd.d: Delete. * testsuite/gas/i860/simd.s: Delete. * testsuite/gas/i860/system.d: Delete. * testsuite/gas/i860/system.s: Delete. * testsuite/gas/i860/xp.d: Delete. * testsuite/gas/i860/xp.s: Delete. * Makefile.am: Remove i860 and i960 support. * configure.tgt: Likewise. * doc/Makefile.am: Likewise. * doc/all.texi: Likewise. * testsuite/gas/all/gas.exp * config/obj-coff.h: Remove i960 support. * doc/internals.texi: Likewise. * expr.c: Likewise. * read.c: Likewise. * write.c: Likewise. * write.h: Likewise. * testsuite/gas/lns/lns.exp: Likewise. * testsuite/gas/symver/symver.exp: Likewise. * config/tc-m68k.c: Remove BOUT support. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sparc.c: Likewise. * symbols.c: Likewise. * doc/h8.texi: Likewise. * configure.ac: Remove BOUT and i860 support. * doc/as.texinfo: Remove BOUT, i860 and i960 support * Makefile.in: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. ld/ * emulparams/coff_i860.sh: Delete. * emulparams/elf32_i860.sh: Delete. * emulparams/elf32_i960.sh: Delete. * emulparams/gld960.sh: Delete. * emulparams/gld960coff.sh: Delete. * emulparams/lnk960.sh: Delete. * emultempl/gld960.em: Delete. * emultempl/gld960c.em: Delete. * emultempl/lnk960.em: Delete. * scripttempl/i860coff.sc: Delete. * scripttempl/i960.sc: Delete. * ld.texinfo: Remove i960 support. * Makefile.am: Remove i860 and i960 support. * configure.tgt: Likewise. * testsuite/ld-discard/extern.d: Likewise. * testsuite/ld-discard/start.d: Likewise. * testsuite/ld-discard/static.d: Likewise. * testsuite/ld-elf/compressed1d.d: Likewise. * testsuite/ld-elf/group1.d: Likewise. * testsuite/ld-elf/group3b.d: Likewise. * testsuite/ld-elf/group8a.d: Likewise. * testsuite/ld-elf/group8b.d: Likewise. * testsuite/ld-elf/group9a.d: Likewise. * testsuite/ld-elf/group9b.d: Likewise. * testsuite/ld-elf/linkonce2.d: Likewise. * testsuite/ld-elf/merge.d: Likewise. * testsuite/ld-elf/merge2.d: Likewise. * testsuite/ld-elf/merge3.d: Likewise. * testsuite/ld-elf/orphan-10.d: Likewise. * testsuite/ld-elf/orphan-11.d: Likewise. * testsuite/ld-elf/orphan-12.d: Likewise. * testsuite/ld-elf/orphan-9.d: Likewise. * testsuite/ld-elf/orphan-region.d: Likewise. * testsuite/ld-elf/orphan.d: Likewise. * testsuite/ld-elf/orphan3.d: Likewise. * testsuite/ld-elf/pr12851.d: Likewise. * testsuite/ld-elf/pr12975.d: Likewise. * testsuite/ld-elf/pr13177.d: Likewise. * testsuite/ld-elf/pr13195.d: Likewise. * testsuite/ld-elf/pr17550a.d: Likewise. * testsuite/ld-elf/pr17550b.d: Likewise. * testsuite/ld-elf/pr17550c.d: Likewise. * testsuite/ld-elf/pr17550d.d: Likewise. * testsuite/ld-elf/pr17615.d: Likewise. * testsuite/ld-elf/pr20528a.d: Likewise. * testsuite/ld-elf/pr20528b.d: Likewise. * testsuite/ld-elf/pr21562a.d: Likewise. * testsuite/ld-elf/pr21562b.d: Likewise. * testsuite/ld-elf/pr21562c.d: Likewise. * testsuite/ld-elf/pr21562d.d: Likewise. * testsuite/ld-elf/pr21562i.d: Likewise. * testsuite/ld-elf/pr21562j.d: Likewise. * testsuite/ld-elf/pr21562k.d: Likewise. * testsuite/ld-elf/pr21562l.d: Likewise. * testsuite/ld-elf/pr21562m.d: Likewise. * testsuite/ld-elf/pr21562n.d: Likewise. * testsuite/ld-elf/pr22677.d: Likewise. * testsuite/ld-elf/pr22836-1a.d: Likewise. * testsuite/ld-elf/pr22836-1b.d: Likewise. * testsuite/ld-elf/pr349.d: Likewise. * testsuite/ld-elf/sec-to-seg.exp: Likewise. * testsuite/ld-elf/sec64k.exp: Likewise. * testsuite/ld-elf/warn1.d: Likewise. * testsuite/ld-elf/warn2.d: Likewise. * testsuite/ld-elf/warn3.d: Likewise. * testsuite/lib/ld-lib.exp: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.	8 years ago
Nick Clifton	c8d59609b1	Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+REG addressing with an assumed offset register. PR 22988 opcode * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_SVE_ADDR_R. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx instructions with only a base address register. * aarch64-opc.c (operand_general_constraint_met_p): Add code to handle AARHC64_OPND_SVE_ADDR_R. (aarch64_print_operand): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64_dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * config/tc-aarch64.c (parse_operands): Add code to handle AARCH64_OPN_SVE_ADDR_R. * testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions with an assumed XZR offset address register. * testsuite/gas/aarch64/sve.d: Update expected disassembly.	9 years ago
Jim Wilson	0e35537d75	RISC-V: Add .insn support. gas/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * config/tc-riscv.c (opcode_name_list): New. (opcode_names_hash): Likewise. (init_opcode_names_hash): Likewise. (opcode_name_lookup): Likewise. (validate_riscv_insn): New argument length, and add new format which used in .insn directive. (md_begin): Refine hash table initialization logic into init_opcode_hash. (init_opcode_hash): New. (my_getOpcodeExpression): Parse opcode name for .insn. (riscv_ip): New argument hash, able to handle .insn directive. (s_riscv_insn): Handler for .insn directive. (riscv_pseudo_table): New entry for .insn. * doc/c-riscv.texi: Add documentation for .insn directive. * testsuite/gas/riscv/insn.d: Add testcase for .insn directive. * testsuite/gas/riscv/insn.s: Likewise. include/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * opcode/riscv.h (OP_MASK_FUNCT3): New. (OP_SH_FUNCT3): Likewise. (OP_MASK_FUNCT7): Likewise. (OP_SH_FUNCT7): Likewise. (OP_MASK_OP2): Likewise. (OP_SH_OP2): Likewise. (OP_MASK_CFUNCT4): Likewise. (OP_SH_CFUNCT4): Likewise. (OP_MASK_CFUNCT3): Likewise. (OP_SH_CFUNCT3): Likewise. (riscv_insn_types): Likewise. opcodes/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_insn_types): New.	9 years ago
H.J. Lu	bd5dea8822	x86: Remove support for old (<= 2.8.1) versions of gcc Old (<= 2.8.1) versions of gcc generate broken fsubp, fsubrp, fdivp and fdivrp instructions. Assembler translates them to correct ones with a warning: [hjl@gnu-cfl-1 gas]$ cat x.s fsubp %st(3),%st [hjl@gnu-cfl-1 gas]$ gcc -c x.s x.s: Assembler messages: x.s:1: Warning: translating to `fsubp %st,%st(3)' [hjl@gnu-cfl-1 gas]$ This patch removes support for old (<= 2.8.1) versions of gcc: [hjl@gnu-cfl-1 gas]$ ./as-new -o x.o x.s x.s: Assembler messages: x.s:1: Error: operand type mismatch for `fsubp' [hjl@gnu-cfl-1 gas]$ gas/ * NEWS: Mention -mold-gcc removal. * config/tc-i386.c (i386_error): Remove old_gcc_only. (old_gcc): Removed. (match_template): Remove old gcc support. (OPTION_MOLD_GCC): Removed. (OPTION_MRELAX_RELOCATIONS): Updated. (md_longopts): Remove OPTION_MOLD_GCC. (md_parse_option): Likewise. (md_show_usage): Remove -mold-gcc. * testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old (<= 2.8.1) versions of gcc. * testsuite/gas/i386/intel.s: Likewise. * testsuite/gas/i386/general.l: Updated. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intel.e: Likewise. * testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general. include/ * opcode/i386 (OLDGCC_COMPAT): Removed. opcodes/ * i386-gen.c (opcode_modifiers): Remove OldGcc. * i386-opc.h (OldGcc): Removed. (i386_opcode_modifier): Remove oldgcc. * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp instructions for old (<= 2.8.1) versions of gcc. * i386-tbl.h: Regenerated.	9 years ago
Thomas Preud'homme	5b616beff4	[ARM] Remove ARM_FEATURE_COPY macro Among the macros to manipulate an arm_feature_set structure is the ARM_FEATURE_COPY which copy the value of a feature set into another. This can be achieved with a simple assignement which most of the existing code does. This patch removes the last 2 uses of that macro and remove the macro altogether. 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com> include/ * opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition. 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com> opcodes/ * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY macro by assignements.	9 years ago
Maciej W. Rozycki	75f3166520	MIPS16/opcodes: Free up `M' operand code The `M' and `m' MIPS16 operand codes are functionally the same, denoting a 7-bit register list that is encoded the same way for both SAVE and RESTORE. Use `m' for both instructions then, making `M' available for a different use. opcodes/ * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case. (mips16_opcodes): Replace `M' with `m' for "restore". include/ * opcode/mips.h: Remove `M' operand code.	9 years ago
Jim Wilson	645a2c5b46	RISC-V: Add 2 missing privileged registers. gas/ * testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval. * testsuite/gas/riscv/priv-reg.d: Likewise. include/ * opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL. (CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry. Add alias to map mbadaddr to CSR_MTVAL.	9 years ago
Alan Modra	219d1afa89	Update year range in copyright notice of binutils files	9 years ago
Jim Wilson	d9be0c189a	RISC-V: Add missing privileged spec registers. gas/ * testsuite/gas/riscv/priv-reg.d, testsuite/gas/riscv/priv-reg.s: New. include/ * opcode/riscv-opc.h (DECLARE_CSR): Add missing privileged registers. Sort to match privileged spec documentation order. (DECLARE_CSR_ALIAS): Add ubadaddr, and comments.	9 years ago
Tamar Christina	00c2093f69	Correct disassembly of dot product instructions. Dot products deviate from the normal disassembly rules for lane indexed instruction. Their canonical representation is in the form of: v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote that these instructions select 4x 1 byte elements instead of a single 1 byte element. Previously we were disassembling them following the normal rules, this patch corrects the disassembly. gas/ PR gas/22559 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B. * gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly. include/ PR gas/22559 * aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B. opcodes/ PR gas/22559 * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant. * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.	9 years ago
Tamar Christina	a3b3345ae6	Add support for V_4B so we can properly reject it. Previously parse_vector_type_for_operand was changed to allow the use of 4b register size for indexed lane instructions. However this had the unintended side effect of also allowing 4b for normal vector registers. Because this support was only partial the rest of the tool silently treated 4b as 8b and continued. This patch adds full support for 4b so it can be properly distinguished from 8b and the correct errors are generated. With this patch you still can't encode any instruction which actually requires v<num>.4b but such instructions don't exist so to prevent needing a workaround in get_vreg_qualifier_from_value this was just omitted. gas/ PR gas/22529 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B. * gas/testsuite/gas/aarch64/pr22529.s: New. * gas/testsuite/gas/aarch64/pr22529.d: New. * gas/testsuite/gas/aarch64/pr22529.l: New. include/ PR gas/22529 * opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B. opcodes/ PR gas/22529 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.	9 years ago
Peter Bergner	0f873fd58b	Use consistent types for holding instructions, instruction masks, etc. include/ * opcode/ppc.h (PPC_INT_FMT): Define. (struct powerpc_opcode) <opcode>: Update type. (struct powerpc_opcode) <mask>: Likewise. (struct powerpc_opcode) <bitm>: Likewise. (struct powerpc_opcode) <insert>: Likewise. (struct powerpc_opcode) <extract>: Likewise. (ppc_optional_operand_value): Likewise. gas/ * config/tc-ppc.c (last_insn): Update type. (insn_validate) <omask, mask>: Likewise. (ppc_setup_opcodes) <mask, right_bit>: Likewise. <PRINT_OPCODE_TABLE>: Update types and printf format specifiers. (ppc_insert_operand): Update return and argument types and remove unneeded type casts. <min, max, right, tmp>: Update type. (md_assemble): Remove unneeded type casts. <insn, val, tmp_insn>: Update type. opcodes/ * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space. (operand_value_powerpc): Update return and argument type. <value, top>: Update type. (skip_optional_operands): Update argument type. (lookup_powerpc): Likewise. (lookup_vle): Likewise. <table_opcd, table_mask, insn2>: Update type. (lookup_spe2): Update argument type. <table_opcd, table_mask, insn2>: Update type. (print_insn_powerpc) <insn, value>: Update type. Use PPC_INT_FMT for printing instructions and operands. * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary, insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat, insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp, extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo, extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm, extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls, insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6, extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi, insert_ral, extract_ral, insert_ram, extract_ram, insert_raq, extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs, insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n, extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w, insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr, extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr, insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6, extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s, insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi, extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui, extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0, extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0, insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0, extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8, insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even, extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2, extract_off_spe2, insert_Ddd, extract_Ddd): Update types. (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15, BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX, DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK, SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST, VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET, VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA, VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK, XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK, XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK, XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB, XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.	9 years ago
Tamar Christina	d0f7791c66	Add new AArch64 FP16 FM{A\|S} instructions. This patch separates the new FP16 instructions backported from Armv8.4-a to Armv8.2-a into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a. The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory on Armv8.4-a. gas/ * config/tc-aarch64.c (fp16fml): New. * doc/c-aarch64.texi (fp16fml): New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d (fp16): Make fp16fml. * testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d (fp16): Make fp16fml. include/ * opcode/aarch64.h: (AARCH64_FEATURE_F16_FML): New. (AARCH64_ARCH_V8_4): Enable AARCH64_FEATURE_F16_FML by default. opcodes/ * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML and AARCH64_FEATURE_F16.	9 years ago
Tamar Christina	01f4802036	Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a. The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory from Armv8.4-a. gas/ * config/tc-arm.c (arm_ext_fp16_fml, fp16fml): New. (do_neon_fmac_maybe_scalar_long): Use arm_ext_fp16_fml. * doc/c-arm.texi (fp16, fp16fml): New. * testsuite/gas/arm/armv8_2-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_3-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d (fp16): Make fp16fml. include/ * opcode/arm.h: (ARM_EXT2_FP16_FML): New. (ARM_AEXT2_V8_4A): Add ARM_EXT2_FP16_FML.	9 years ago
Tamar Christina	981b557a48	Enable the Dot Product extension by default for Armv8.4-a. include/ * opcode/aarch64.h (AARCH64_ARCH_V8_4): Enable DOTPROD. gas/testsuite * gas/aarch64/dotproduct_armv8_4.s: New. * gas/aarch64/dotproduct_armv8_4.d: New.	9 years ago
Tamar Christina	f42f1a1d6c	Adds the new Fields and Operand types for the new instructions in Armv8.4-a. gas/ * config/tc-aarch64.c (process_omitted_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2 and AARCH64_OPND_IMM_2. (parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, AARCH64_OPND_IMM_2, AARCH64_OPND_MASK and AARCH64_OPND_ADDR_OFFSET. include/ * opcode/aarch64.h: (aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK, AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET and AARCH64_OPND_SM3_IMM2. (aarch64_insn_class): Add cryptosm3 and cryptosm4. (arch64_feature_set): Make uint64_t. opcodes/ * aarch64-asm.h (ins_addr_offset): New. * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3. (aarch64_ins_addr_offset): New. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_addr_offset): New. * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3. (aarch64_ext_addr_offset): New. * aarch64-dis-2.c: Regenerate. * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2, FLD_imm4_2 and FLD_SM3_imm2. * aarch64-opc.c (fields): Add FLD_imm6_2, FLD_imm4_2 and FLD_SM3_imm2. (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET. (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET. * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New. * aarch64-tbl.h (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.	9 years ago
Tamar Christina	b6b9ca0c3e	Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options (+aes and +sha2). The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions. gas * config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a. (aarch64_features): Added SM4 and SHA3. include * opcode/aarch64.h: (AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New. (AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New. opcodes * aarch64-tbl.h (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New. (aarch64_feature_sm4, aarch64_feature_sha3): New. (aarch64_feature_fp_16_v8_2): New. (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New. (V8_4_INSN, CRYPTO_V8_2_INSN): New. (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.	9 years ago
Nick Clifton	21b81e67c7	Change the type of the aarch64_feature_set typedef to unsigned long long so that it will work on 32-bit hosts. * opcode/aarch64.h (aarch64_feature_set): Change type to unsigned long long.	9 years ago
Nick Clifton	c0e7cef715	Split the AArch64 Crypto instructions for AES and SHA1+2 into their own options (+aes and +sha2). The new options are: +aes: Enables the AES instructions of Armv8-a, enabled by default with +crypto. +sha2: Enables the SHA1 and SHA2 instructions of Armv8-a, enabled by default with +crypto. These options have been turned on by default when +crypto is used, as such no breakage is expected. The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions. Backporting the split does not break any of the previous requirements and so is safe to do. gas * config/tc-aarch64.c (aarch64_features): Include AES and SHA2 in CRYPTO. Add SHA2 and AES. include * opcode/aarch64.h: (AARCH64_FEATURE_SHA2, AARCH64_FEATURE_AES): New. opcodes * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2. (aarch64_feature_sha2, aarch64_feature_aes): New. (SHA2, AES): New. (AES_INSN, SHA2_INSN): New. (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS. (sha1h, sha1su1, sha256su0, sha1c, sha1p, sha1m, sha1su0, sha256h, sha256h2, sha256su1): Change to SHA2_INS.	9 years ago
Jiong Wang	dec41383ff	Adds command line support for Armv8.4-A, via the new command line option -march=armv8.4-a. Add support for "+dotprod" ARM feature (required for ARMv8.4-A). Add assembler and disassembler support for new FP16 instructions introduced in Armv8.4-A gas * config/tc-arm.c (arm_extensions): (arm_archs): New entry for "armv8.4-a". Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8. (arm_ext_v8_2): New variable. (enum arm_reg_type): New enumeration REG_TYPE_NSD. (reg_expected_msgs): New entry for REG_TYPE_NSD. (parse_typed_reg_or_scalar): Handle REG_TYPE_NSD. (parse_scalar): Support REG_TYPE_VFS. (enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC. (parse_operands): Handle OP_RNSD and OP_RNSD_RNSC. (NEON_SHAPE_DEF): New entries for DHH and DHS. (neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding for new FP16 instructions in ARMv8.2-A. (do_neon_fmac_maybe_scalar_long): New function to encode new FP16 instructions in ARMv8.2-A. (do_neon_vfmal): Wrapper function for vfmal. (do_neon_vfmsl): Wrapper function for vfmsl. (insns): New entries for vfmal and vfmsl. * doc/c-arm.texi (-march): Document "armv8.4-a". * testsuite/gas/arm/dotprod-mandatory.d: New test. * testsuite/gas/arm/armv8_2-a-fp16.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16.d: New test. * testsuite/gas/arm/armv8_3-a-fp16.d: New test. * testsuite/gas/arm/armv8_4-a-fp16.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file. opcodes * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new FP16 instructions, including vfmal.f16 and vfmsl.f16. include * opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature. (ARM_EXT2_V8_4A): New macro. (ARM_AEXT2_V8_4A): Likewise. (ARM_ARCH_V8_4A): Likewise.	9 years ago
Palmer Dabbelt	1270b047fd	RISC-V: Add satp as an alias for sptbr The RISC-V privileged ISA changed the name of sptbr (Supervisor Page Table Base Register) to satp (Supervisor Address Translation and Protection) to reflect the fact it could be used for more than just paging. This patch adds an alias, as they're the same register. include/ChangeLog 2017-11-06 Palmer Dabbelt <palmer@dabbelt.com> * opcode/riscv-opc.h (sptbr): Rename to satp. (CSR_SPTBR): Rename to CSR_SATP. (sptbr): Alias to CSR_SATP. gas/ChangeLog 2017-11-06 Palmer Dabbelt <palmer@dabbelt.com> * testsuite/gas/riscv/satp.d: New test. testsuite/gas/riscv/satp.s: Likewise. testsuite/gas/riscv/riscv.exp: Likewise. config/tc-riscv.c (md_begin): Handle CSR aliases.	9 years ago
Tamar Christina	0198d5e6fc	This patch similarly to the AArch64 one enables Dot Product support by default for the Cortex-A55 and Cortex-A75 which have hardware support for these instructions. gas * config/tc-arm.c (arm_cpus): Change FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 into FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD. include * opcode/arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD): New macro.	9 years ago
Siddhesh Poyarekar	c05e0c5af3	aarch64: Remove AARCH64_FEATURE_F16 from AARCH64_ARCH_V8_2 The FP16 feature is optional in ARMv8.2, so it is wrong to add it to the default AARCH64_ARCH_V8_2 feature flags. This patch makes the behaviour consistent with that of gcc, which also does not assume FP16 for ARMv8.2. include/ * opcode/aarch64.h (AARCH64_ARCH_V8_2): Drop AARCH64_FEATURE_F16.	9 years ago
Alan Modra	e5d70d6b5a	PR22348, conflicting global vars in crx and cr16 include/ PR 22348 * opcode/cr16.h (instruction): Delete. (cr16_words, cr16_allWords, cr16_currInsn): Delete. * opcode/crx.h (crx_cst4_map): Rename from cst4_map. (crx_cst4_maps): Rename from cst4_maps. (crx_no_op_insn): Rename from no_op_insn. (instruction): Delete. opcodes/ PR 22348 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static. (cr16_words, cr16_allWords, processing_argument_number): Likewise. (imm4flag, size_changed): Likewise. * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise. (words, allWords, processing_argument_number): Likewise. (cst4flag, size_changed): Likewise. * crx-opc.c (crx_cst4_map): Rename from cst4_map. (crx_cst4_maps): Rename from cst4_maps. (crx_no_op_insn): Rename from no_op_insn. gas/ PR 22348 * config/tc-crx.c (instruction, output_opcode): Make static. (relocatable, ins_parse, cur_arg_num): Likewise. (parse_insn): Adjust for renamed opcodes globals. (check_range): Likewise	9 years ago
Andrew Waterman	3342be5dab	RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 This matches the ISA specification. This also adds two tests: one to make sure the assembler rejects invalid 'c.lui's, and one to make sure we only relax valid 'c.lui's. bfd/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui when rd is x0. include/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the immediate 0. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-lui-fail.d: New testcase. gas/testsuite/gas/riscv/c-lui-fail.l: Likewise. gas/testsuite/gas/riscv/c-lui-fail.s: Likewise. gas/testsuite/gas/riscv/riscv.exp: Likewise. ld/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase. ld/testsuite/ld-riscv-elf/c-lui.s: Likewise. ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.	9 years ago
James Bowman	3b4b0a629a	FT32: support for FT32B processor - part 1 FT32B is a new FT32 family member. It has a code compression scheme, which requires the use of linker relaxations. The change is quite large, so submission is in several parts. Part 1 adds a 15-bit instruction field, and CPU-specific functions for the code compression that are used in binutils and GDB. bfd/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-ft32.c: Add HOWTO R_FT32_15. * reloc.c: Add BFD_RELOC_FT32_15. gas/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * config/tc-ft32.c (md_assemble): Replace FT32_FLD_K8 with K15. (md_apply_fix, tc_gen_reloc): Add BFD_RELOC_FT32_15. include/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * elf/ft32.h: Add R_FT32_15. * opcode/ft32.h: Replace FT32_FLD_K8 with K15. (ft32_shortcode, sc_compar, ft32_split_shortcode, ft32_merge_shortcode, ft32_merge_shortcode): New functions. opcodes/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * opcodes/ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15. * opcodes/ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with K15. Add jmpix pattern. sim/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * sim/ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15.	9 years ago
Kuan-Lin Chen	4ec521f238	nds32: Rename __BIT() to N32_BIT().	9 years ago
Alexander Fedotov	7408194835	[PowerPC VLE] Add SPE2 and EFS2 instructions support include/ * opcode/ppc.h: (spe2_opcodes, spe2_num_opcodes): New. (PPC_OPCODE_SPE2): New define. (PPC_OPCODE_EFS2): Likewise. (SPE2_XOP): Likewise. (SPE2_XOP_TO_SEG): Likewise. opcodes/ * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "e200z4" entry. New entries efs2 and spe2. Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry. (SPE2_OPCD_SEGS): New macro. (spe2_opcd_indices): New. (disassemble_init_powerpc): Handle SPE2 opcodes. (lookup_spe2): New function. (print_insn_powerpc): call lookup_spe2. * ppc-opc.c (insert_evuimm1_ex0): New function. (extract_evuimm1_ex0): Likewise. (insert_evuimm_lt8): Likewise. (extract_evuimm_lt8): Likewise. (insert_off_spe2): Likewise. (extract_off_spe2): Likewise. (insert_Ddd): Likewise. (extract_Ddd): Likewise. (DD): New operand. (EVUIMM_LT8): Likewise. (EVUIMM_LT16): Adjust. (MMMM): New operand. (EVUIMM_1): Likewise. (EVUIMM_1_EX0): Likewise. (EVUIMM_2): Adjust. (NNN): New operand. (VX_OFF_SPE2): Likewise. (BBB): Likewise. (DDD): Likewise. (VX_MASK_DDD): New mask. (HH): New operand. (VX_RA_CONST): New macro. (VX_RA_CONST_MASK): Likewise. (VX_RB_CONST): Likewise. (VX_RB_CONST_MASK): Likewise. (VX_OFF_SPE2_MASK): Likewise. (VX_SPE_CRFD): Likewise. (VX_SPE_CRFD_MASK VX): Likewise. (VX_SPE2_CLR): Likewise. (VX_SPE2_CLR_MASK): Likewise. (VX_SPE2_SPLATB): Likewise. (VX_SPE2_SPLATB_MASK): Likewise. (VX_SPE2_OCTET): Likewise. (VX_SPE2_OCTET_MASK): Likewise. (VX_SPE2_DDHH): Likewise. (VX_SPE2_DDHH_MASK): Likewise. (VX_SPE2_HH): Likewise. (VX_SPE2_HH_MASK): Likewise. (VX_SPE2_EVMAR): Likewise. (VX_SPE2_EVMAR_MASK): Likewise. (PPCSPE2): Likewise. (PPCEFS2): Likewise. (vle_opcodes): Add EFS2 and some missing SPE opcodes. (powerpc_macros): Map old SPE instructions have new names with the same opcodes. Add SPE2 instructions which just are mapped to SPE2. (spe2_opcodes): Add SPE2 opcodes. gas/ * config/tc-ppc.c: (md_parse_option): Add mspe2 switch. (md_show_usage): Document -mspe2. (ppc_setup_opcodes): Handle spe2_opcodes. * doc/as.texinfo: Document -mspe2. * doc/c-ppc.texi: Likewise. * testsuite/gas/ppc/efs.d: New file. * testsuite/gas/ppc/efs.s: Likewise. * testsuite/gas/ppc/efs2.d: Likewise. * testsuite/gas/ppc/efs2.s: Likewise. * testsuite/gas/ppc/ppc.exp: Run new tests. * testsuite/gas/ppc/spe.d: New file. * testsuite/gas/ppc/spe.s: Likewise. * testsuite/gas/ppc/spe2-checks.d: Likewise. * testsuite/gas/ppc/spe2-checks.l: Likewise. * testsuite/gas/ppc/spe2-checks.s: Likewise. * testsuite/gas/ppc/spe2.d: Likewise. * testsuite/gas/ppc/spe2.s: Likewise. * testsuite/gas/ppc/spe_ambiguous.d: Likewise. * testsuite/gas/ppc/spe_ambiguous.s: Likewise.	9 years ago

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1059 Commits (5890af36e5112bcbb8d7555e63570f68466e6944)