binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Martin Liska	1343fed469	LTO plugin: sync header file with GCC include/ChangeLog: * plugin-api.h (enum ld_plugin_tag): Sync with GCC.	4 years ago
Nick Clifton	ba951afb99	Add a linker warning when creating potentially dangerous executable segments. Add tests, options to disabke and configure switches to choose defaults.	4 years ago
Nick Alcock	44c70fb01f	libctf: add a comment explaining how to use ctf_open Specifically, tell users what to pass to those functions that accept raw section content, since it's fairly involved and easy to get wrong. (.dynsym / .dynstr when CTF_F_DYNSTR is set, otherwise .symtab / .strtab). include/ChangeLog: ctf-api.h (ctf_*open): Improve comment.	4 years ago
Christoph Muellner	77e99ad92f	RISC-V: Add missing DECLARE_INSNs for Zicbo{m,p,z} The recently added support for the Zicbo{m,p,z} extensions did not include DECLARE_INSN() declarations for the instructions. These declarations are needed by GDB's instruction detection code. This patch adds them. Signed-off-by: Christoph Muellner <cmuellner@gcc.gnu.org>	4 years ago
Cl?ment Chigot	1876a54217	Stubs (added in a later patch) will generate new .loader symbols, once the allocations have been done. Thus, the .loader section cannot be layout before that. bfd/ChangeLog: * coff-rs6000.c (_bfd_xcoff_put_ldsymbol_name): Write len in ldinfo->strings instead of directly in the output_bfd. * coff64-rs6000.c (_bfd_xcoff64_put_ldsymbol_name): Likewise. * xcofflink.c (struct xcoff_link_hash_table): Remove ldrel_count field. Add ldinfo field. (xcoff_mark_symbol): Adjust to new ldinfo field. (xcoff_mark): Likewise. (bfd_xcoff_link_count_reloc): Likewise. (xcoff_build_loader_section): Split into two functions: one that build the loader section (this function) and one that only size it... (xcoff_size_loader_section): ... (this function). (bfd_xcoff_size_dynamic_sections): Adapt to new ldinfo field. Move the part where the dynamic sections are build to ... (bfd_xcoff_build_dynamic_sections): ... this function. * xcofflink.h: Add bfd_xcoff_build_dynamic_sections prototype. include/ChangeLog: * coff/xcoff.h (struct xcoff_loader_info): Add ldrel_count and libpath fields. ld/ChangeLog: * emultempl/aix.em (_after_allocation): New function.	4 years ago
Nick Clifton	65daf5bed6	Add linker warning for when it creates an executable stack. PR 29072	4 years ago
Luis Machado	eb33f6973e	Recognize the NT_ARM_SYSTEM_CALL register set Update binutils to recognize the NT_ARM_SYSTEM_CALL set that is dumped by Linux to core files.	4 years ago
Mark Harmstone	145667f8d9	Add support for COFF secidx relocations bfd * coff-i386.c (in_reloc_p): Add R_SECTION. (howto_table): Add R_SECTION. (coff_pe_i386_relocation_section): Add support for R_SECTION. (coff_i386_reloc_type_lookup): Add support for BFD_RELOC_16_SECCIDX. * coff-x86_64.c (in_reloc_p): Add R_SECTION. (howto_table): Add R_SECTION. (coff_pe_amd64_relocation_section): Add support for R_SECTION. (coff_amd64_reloc_type_lookup): Add support for BFD_RELOC_16_SECCIDX. * reloc.c: Add BFD_RELOC_16_SECIDX. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas * config/tc-i386.c (pe_directive_secidx): New function. (md_pseudo_table): Add support for secidx. (x86_cons_fix_new): Likewise. (tc_gen_reloc): Likewise. * expr.c (op_rank): Add O_secidx. * expr.h (operatorT): Likewise. * symbols.c (resolve_symbol_value): Add support for O_secidx. * testsuite/gas/i386/secidx.s: New test source file. * testsuite/gas/i386/secidx.d: New test driver file. * testsuite/gas/i386/i386.exp: Run new test. include * coff/i386.h: Define R_SECTION. * coff/x86_64.h: Likewise. ld * testsuite/ld-pe/secidx1.s: New test source file. * testsuite/ld-pe/secidx2.s: New test source file. * testsuite/ld-pe/secidx.d: New test driver file. * testsuite/ld-pe/secidx_64.d: New test driver file. * testsuite/ld-pe/pe.exp: Add new tests.	4 years ago
Andrew Burgess	60a3da00bd	objdump/opcodes: add syntax highlighting to disassembler output This commit adds the _option_ of having disassembler output syntax highlighted in objdump. This option is _off_ by default. The new command line options are: --disassembler-color=off # The default. --disassembler-color=color --disassembler-color=extended-color I have implemented two colour modes, using the same option names as we use of --visualize-jumps, a basic 8-color mode ("color"), and an extended 8bit color mode ("extended-color"). The syntax highlighting requires that each targets disassembler be updated; each time the disassembler produces some output we now pass through an additional parameter indicating what style should be applied to the text. As updating all target disassemblers is a large task, the old API is maintained. And so, a user of the disassembler (i.e. objdump, gdb) must provide two functions, the current non-styled print function, and a new, styled print function. I don't currently have a plan for converting every single target disassembler, my hope is that interested folk will update the disassemblers they are interested in. But it is possible some might never get updated. In this initial series I intend to convert the RISC-V disassembler completely, and also do a partial conversion of the x86 disassembler. Hopefully having the x86 disassembler at least partial converted will allow more people to try this out easily and provide feedback. In this commit I have focused on objdump. The changes to GDB at this point are the bare minimum required to get things compiling, GDB makes no use of the styling information to provide any colors, that will come later, if this commit is accepted. This first commit in the series doesn't convert any target disassemblers at all (the next two commits will update some targets), so after this commit, the only color you will see in the disassembler output, is that produced from objdump itself, e.g. from objdump_print_addr_with_sym, where we print an address and a symbol name, these are now printed with styling information, and so will have colors applied (if the option is on). Finally, my ability to pick "good" colors is ... well, terrible. I'm in no way committed to the colors I've picked here, so I encourage people to suggest new colors, or wait for this commit to land, and then patch the choice of colors. I do have an idea about using possibly an environment variable to allow the objdump colors to be customised, but I haven't done anything like that in this commit, the color choices are just fixed in the code for now. binutils/ChangeLog: * NEWS: Mention new feature. * doc/binutils.texi (objdump): Describe --disassembler-color option. * objdump.c (disassembler_color): New global. (disassembler_extended_color): Likewise. (disassembler_in_comment): Likewise. (usage): Mention --disassembler-color option. (long_options): Add --disassembler-color option. (objdump_print_value): Use fprintf_styled_func instead of fprintf_func. (objdump_print_symname): Likewise. (objdump_print_addr_with_sym): Likewise. (objdump_color_for_disassembler_style): New function. (objdump_styled_sprintf): New function. (fprintf_styled): New function. (disassemble_jumps): Use disassemble_set_printf, and reset disassembler_in_comment. (null_styled_print): New function. (disassemble_bytes): Use disassemble_set_printf, and reset disassembler_in_comment. (disassemble_data): Update init_disassemble_info call. (main): Handle --disassembler-color option. include/ChangeLog: * dis-asm.h (enum disassembler_style): New enum. (struct disassemble_info): Add fprintf_styled_func field, and created_styled_output field. (disassemble_set_printf): Declare. (init_disassemble_info): Add additional parameter. (INIT_DISASSEMBLE_INFO): Add additional parameter. opcodes/ChangeLog: * dis-init.c (init_disassemble_info): Take extra parameter, initialize the new fprintf_styled_func and created_styled_output fields. * disassembler.c (disassemble_set_printf): New function definition.	5 years ago
Tiezhu Yang	552f1157c6	gdb: rename floatformats_ia64_quad to floatformats_ieee_quad It is better to rename floatformats_ia64_quad to floatformats_ieee_quad to reflect the reality, and then we can clean up the related code. As Tom Tromey said [1]: These files are maintained in gcc and then imported into the binutils-gdb repository, so any changes to them will have to be proposed there first. the related changes have been merged into gcc master now [2], it is time to do it for gdb. [1] https://sourceware.org/pipermail/gdb-patches/2022-March/186569.html [2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b2dff6b2d9d6 Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>	4 years ago
John Baldwin	a171378aa4	Recognize FreeBSD core dump note for x86 segment base registers. This core dump note contains the value of the base address of the %fs and %gs segments for both i386 and amd64 core dumps. It is primarily useful in resolving the address of TLS variables in core dumps. binutils/ChangeLog: * readelf.c (get_freebsd_elfcore_note_type): Handle NT_FREEBSD_X86_SEGBASES. include/ChangeLog: * elf/common.h (NT_FREEBSD_X86_SEGBASES): Define.	4 years ago
Nick Alcock	203bfa2f6b	include, libctf, ld: extend variable section to contain functions too The CTF variable section is an optional (usually-not-present) section in the CTF dict which contains name -> type mappings corresponding to data symbols that are present in the linker input but not in the output symbol table: the idea is that programs that use their own symbol- resolution mechanisms can use this section to look up the types of symbols they have found using their own mechanism. Because these removed symbols (mostly static variables, functions, etc) all have names that are unlikely to appear in the ELF symtab and because very few programs have their own symbol-resolution mechanisms, a special linker flag (--ctf-variables) is needed to emit this section. Historically, we emitted only removed data symbols into the variable section. This seemed to make sense at the time, but in hindsight it really doesn't: functions are symbols too, and a C program can look them up just like any other type. So extend the variable section so that it contains all static function symbols too (if it is emitted at all), with types of kind CTF_K_FUNCTION. This is a little fiddly. We relied on compiler assistance for data symbols: the compiler simply emits all data symbols twice, once into the symtypetab as an indexed symbol and once into the variable section. Rather than wait for a suitably adjusted compiler that does the same for function symbols, we can pluck unreported function symbols out of the symtab and add them to the variable section ourselves. While we're at it, we do the same with data symbols: this is redundant right now because the compiler does it, but it costs very little time and lets the compiler drop this kludge and save a little space in .o files. include/ * ctf.h: Mention the new things we can see in the variable section. ld/ * testsuite/ld-ctf/data-func-conflicted-vars.d: New test. libctf/ * ctf-link.c (ctf_link_deduplicating_variables): Duplicate symbols into the variable section too. * ctf-serialize.c (symtypetab_delete_nonstatic_vars): Rename to... (symtypetab_delete_nonstatics): ... this. Check the funchash when pruning redundant variables. (ctf_symtypetab_sect_sizes): Adjust accordingly. * NEWS: Describe this change.	4 years ago
liuzhensong	3b14682a43	LoongArch: Update ABI eflag in elf header. Update LoongArch ABI eflag in elf header. ilp32s 0x5 ilp32f 0x6 ilp32d 0x7 lp64s 0x1 lp64f 0x2 lp64d 0x3 bfd/ * elfnn-loongarch.c Check object flags while ld. gas/ * tc-loongarch.c Write eflag to elf header. include/elf * loongarch.h Define ABI number.	5 years ago
liuzhensong	5fb13d7ef4	gas:LoongArch: Fix segment error in compilation due to too long symbol name. Change "char buffer[8192];" into "char buffer = (char ) malloc(1000 + 6 * len_str);" in function loongarch_expand_macro_with_format_map. gas/ * config/tc-loongarch.c include/ * opcode/loongarch.h opcodes/ * loongarch-coder.c	4 years ago
Tsukasa OI	41d6ac5da6	RISC-V: Cache management instructions This commit adds 'Zicbom' / 'Zicboz' instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction classes. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN, MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL, MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros. * opcode/riscv.h (enum riscv_insn_class): Add new instruction classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add cache-block management instructions.	5 years ago
Tsukasa OI	3b374308d3	RISC-V: Prefetch hint instructions and operand set This commit adds 'Zicbop' hint instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction class. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for new operand type 'f' (32-byte aligned pseudo S-type immediate for prefetch hints). (validate_riscv_insn): Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I, MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W, MASK_PREFETCH_W): New macros. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZICBOP. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add handling for new operand type. * riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.	5 years ago
Simon Marchi	0c857ef4df	binutils/readelf: handle AMDGPU relocation types Make readelf recognize AMDGPU relocation types, as documented here: https://llvm.org/docs/AMDGPUUsage.html#amdgpu-relocation-records The user-visible change looks like: -000000000004 000400000001 unrecognized: 1 0000000000000000 SCRATCH_RSRC_DWORD0 -00000000000c 000500000001 unrecognized: 1 0000000000000000 SCRATCH_RSRC_DWORD1 -000000000014 000600000007 unrecognized: 7 0000000000000000 global_var0 -00000000001c 000700000008 unrecognized: 8 0000000000000000 global_var1 -000000000024 000800000009 unrecognized: 9 0000000000000000 global_var2 -00000000002c 00090000000a unrecognized: a 0000000000000000 global_var3 -000000000034 000a0000000b unrecognized: b 0000000000000000 global_var4 +000000000004 000400000001 R_AMDGPU_ABS32_LO 0000000000000000 SCRATCH_RSRC_DWORD0 +00000000000c 000500000001 R_AMDGPU_ABS32_LO 0000000000000000 SCRATCH_RSRC_DWORD1 +000000000014 000600000007 R_AMDGPU_GOTPCREL 0000000000000000 global_var0 +00000000001c 000700000008 R_AMDGPU_GOTPCREL 0000000000000000 global_var1 +000000000024 000800000009 R_AMDGPU_GOTPCREL 0000000000000000 global_var2 +00000000002c 00090000000a R_AMDGPU_REL32_LO 0000000000000000 global_var3 +000000000034 000a0000000b R_AMDGPU_REL32_HI 0000000000000000 global_var4 binutils/ChangeLog: * readelf.c (dump_relocations): Handle EM_AMDGPU. include/ChangeLog: * elf/amdgpu.h: Add relocation values. Change-Id: I2ed4589f4cd37ea11ad2e0cb38d4b682271e1334	4 years ago
Simon Marchi	28cdbb183b	binutils/readelf: handle NT_AMDGPU_METADATA note name Handle the NT_AMDGPU_METADATA note, which is described here: https://llvm.org/docs/AMDGPUUsage.html#code-object-v3-note-records As of this patch, just print out the name, not the contents, which is in the msgpack format. binutils/ChangeLog: * readelf.c (get_amdgpu_elf_note_type): New. (process_note): Handle "AMDGPU" notes. include/ChangeLog: * elf/amdgcn.h (NT_AMDGPU_METADATA): New. Change-Id: Id2dba2e2aeaa55ef7464fb35aee9c7d5f96ddb23	4 years ago
Simon Marchi	c077c5802c	binutils/readelf: decode AMDGPU-specific e_flags Decode and print the AMDGPU-specific fields of e_flags, as documented here: https://llvm.org/docs/AMDGPUUsage.html#header That is: - The specific GPU model - Whether the xnack and sramecc features are enabled The result looks like: - Flags: 0x52f + Flags: 0x52f, gfx906, xnack any, sramecc any The flags for the "HSA" OS ABI are properly versioned and documented on that page. But the NONE, PAL and MESA3D OS ABIs are not well documented nor versioned. Taking a peek at the LLVM source code, we see that they encode their flags the same way as HSA v3. For example, for PAL: `c8b614cd74/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp (L601)` So for those other OS ABIs, we read them the same as HSA v3. binutils/ChangeLog: * readelf.c: Include elf/amdgcn.h. (decode_AMDGPU_machine_flags): New. (get_machine_flags): Handle flags for EM_AMDGPU machine type. include/ChangeLog: * elf/amdgcn.h: Add EF_AMDGPU_MACH_AMDGCN_* and EF_AMDGPU_FEATURE_* defines. Change-Id: Ib5b94df7cae0719a22cf4e4fd0629330e9485c12	4 years ago
Simon Marchi	37870be874	binutils/readelf: handle AMDGPU OS ABIs When the machine is EM_AMDGPU, handle the various OS ABIs described here: https://llvm.org/docs/AMDGPUUsage.html#header For a binary with the HSA OS ABI, the change looks like: - OS/ABI: <unknown: 40> + OS/ABI: AMD HSA binutils/ChangeLog: * readelf.c (get_osabi_name): Handle EM_AMDGPU OS ABIs. include/ChangeLog: * elf/common.h (ELFOSABI_AMDGPU_PAL, ELFOSABI_AMDGPU_MESA3D): New. Change-Id: I383590c390f7dc2fe0f902f50038735626d71863	4 years ago
Simon Marchi	978602e83f	bfd: add AMDGCN architecture Add support for the AMDGCN architecture to BFD. This is the bare minimum to get $ ./configure --target=amdgcn-hsa-amdhsa --disable-gas $ make all-binutils working later in this series. The specific AMDGCN models added here are a bit arbitrary, based on what we intend to initially support in GDB. This list will need to be updated in the future anyway. The complete up-to-date list of existing AMDGPU models can be found here: https://llvm.org/docs/AMDGPUUsage.html#processors The ELF format for this architecture is documented here: https://llvm.org/docs/AMDGPUUsage.html#elf-code-object The flags for the "HSA" OS ABI are properly versioned and documented on that page. But the NONE, PAL and MESA3D OS ABIs are not well documented nor versioned. Taking a peek at the LLVM source code, we see that they encode their flags the same way as HSA v3. For example, for PAL: `c8b614cd74/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp (L601)` So at least, we know that all AMDGPU objects (of which AMDGCN objects are a subset of) at the time of writing encode the specific GPU model in the EF_AMDGPU_MACH field of e_flags. bfd/ChangeLog: * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add cpu-amdgcn.c. (BFD64_BACKENDS): Add elf64-amdgcn.lo. (BFD64_BACKENDS_CFILES): Add elf64-amdgcn.c. * Makefile.in: Re-generate. * cpu-amdgcn.c: New. * elf64-amdgcn.c: New. * archures.c (bfd_architecture): Add bfd_arch_amdgcn and related mach defines. (bfd_amdgcn_arch): New. (bfd_archures_list): Add bfd_amdgcn_arch. * bfd-in2.h: Re-generate. * config.bfd: Handle amdgcn* target. * configure.ac: Handle amdgcn_elf64_le_vec. * configure: Re-generate. * elf-bfd.h (elf_target_id): Add AMDGCN_ELF_DATA. * targets.c (amdgcn_elf64_le_vec): New. (_bfd_target_vector): Add amdgcn_elf64_le_vec. include/ChangeLog: * elf/amdgpu.h: New. * elf/common.h (ELFOSABI_AMDGPU_HSA): Add. Change-Id: I969f7b14960797e88891c308749a6e341eece5b2	4 years ago
Alan Modra	dc3ff92676	Delete PowerPC macro insn support Let's hope this stays dead, but it's here as a patch separate from those that removed use of powerpc_macros just in case it needs to be resurrected. include/ * opcode/ppc.h (struct powerpc_macro): Delete declaration. (powerpc_macros, powerpc_num_macros): Likewise.. opcodes/ * ppc-opc.c (powerpc_macros, powerpc_num_macros): Delete. gas/ * config/tc-ppc.c (ppc_macro): Delete function. (ppc_macro_hash): Delete. (ppc_setup_opcodes, md_assemble): Delete macro support.	4 years ago
Alan Modra	42952a9605	PowerPC64 extended instructions in powerpc_macros The extended instructions implemented in powerpc_macros aren't used by the disassembler. That means instructions like "sldi r3,r3,2" appear in disassembly as "rldicr r3,r3,2,61", which is annoying since many other extended instructions are shown. Note that some of the instructions moved out of the macro table to the opcode table won't appear in disassembly, because they are aliases rather than a subset of the underlying raw instruction. If enabled, rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many occurrences in the case of clrlsldi if n <= b was added to the extract functions.) The patch also fixes a small bug in opcode sanity checking. include/ * opcode/ppc.h (PPC_OPSHIFT_SH6): Define. opcodes/ * ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn), (insert_crdn, extract_crdn, insert_rrdn, extract_rrdn), (insert_sldn, extract_sldn, insert_srdn, extract_srdn), (insert_erdb, extract_erdb, insert_csldn, extract_csldb), (insert_irdb, extract_irdn): New functions. (ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb): Define and add associated powerpc_operands entries. (powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi", "sldi", "extldi", "clrlsldi", "insrdi" and corresponding record (ie. dot suffix) forms. (powerpc_macros): Delete same from here. gas/ * config/tc-ppc.c (insn_validate): Don't modify value passed to operand->insert for PPC_OPERAND_PLUS1 when calculating mask. Handle PPC_OPSHIFT_SH6. * testsuite/gas/ppc/prefix-reloc.d: Update. * testsuite/gas/ppc/simpshft.d: Update. ld/ * testsuite/ld-powerpc/elfv2so.d: Update. * testsuite/ld-powerpc/notoc.d: Update. * testsuite/ld-powerpc/notoc3.d: Update. * testsuite/ld-powerpc/tlsdesc2.d: Update. * testsuite/ld-powerpc/tlsget.d: Update. * testsuite/ld-powerpc/tlsget2.d: Update. * testsuite/ld-powerpc/tlsopt5.d: Update. * testsuite/ld-powerpc/tlsopt6.d: Update.	4 years ago
Vladimir Mezentsev	bb368aad29	gprofng: a new GNU profiler top-level * Makefile.def: Add gprofng module. * configure.ac: Add --enable-gprofng option. * src-release.sh: Add gprofng. * Makefile.in: Regenerate. * configure: Regenerate. * gprofng: New directory. binutils * MAINTAINERS: Add gprofng maintainer. * README-how-to-make-a-release: Add gprofng. include. * collectorAPI.h: New file. * libcollector.h: New file. * libfcollector.h: New file.	4 years ago
Nelson Chu	9cbed90ee6	RISC-V: Updated CSRs to privileged spec v1.12 and debug spec v1.0. * Removed N extension CSRs, ustatus, uie, utvec, uscratch, uepc, ucause, utval and uip. * Removed two supervisor CSRs, sedeleg and sideleg. * Changed debug CSR address of scontext from 0x7aa to 0x5a8. We cannot support different versions of debug specs for now, so only supporting the latest one is the only way to move forward. * Added debug CSRs, mscontext (0x7aa), mcontrol6 (0x7a1, tdata1) and tmexttrigger ((0x7a1, tdata1). * Regarded hcontext as a debug CSR. include/ * opcode/riscv-opc.h: Updated CSRs to privileged spec v1.12 and debug spec v1.0. gas/ * testsuite/gas/riscv/csr.s: Updated CSRs to privileged spec v1.12 and debug spec v1.0. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise.	5 years ago
Tsukasa OI	f4ce10b14f	RISC-V: Add Privileged Architecture 1.12 CSRs This commit adds, * Most of CSRs as listed in the Privileged Architecture, version 1.12 (except scontext and mscontext). * Testcases for most CSRs added on the Privileged Architecture, version 1.12 (except moved "scontext" and new "mscontext"). include/ChangeLog: * opcode/riscv-opc.h (CSR_SENVCFG, CSR_MCONFIGPTR, CSR_MENVCFG, CSR_MSTATUSH, CSR_MENVCFGH, CSR_MTINST, CSR_MTVAL2, CSR_MSECCFG, CSR_MSECCFGH, CSR_PMPCFG4, CSR_PMPCFG5, CSR_PMPCFG6, CSR_PMPCFG7, CSR_PMPCFG8, CSR_PMPCFG9, CSR_PMPCFG10, CSR_PMPCFG11, CSR_PMPCFG12, CSR_PMPCFG13, CSR_PMPCFG14, CSR_PMPCFG15, CSR_PMPADDR16, CSR_PMPADDR17, CSR_PMPADDR18, CSR_PMPADDR19, CSR_PMPADDR20, CSR_PMPADDR21, CSR_PMPADDR22, CSR_PMPADDR23, CSR_PMPADDR24, CSR_PMPADDR25, CSR_PMPADDR26, CSR_PMPADDR27, CSR_PMPADDR28, CSR_PMPADDR29, CSR_PMPADDR30, CSR_PMPADDR31, CSR_PMPADDR32, CSR_PMPADDR33, CSR_PMPADDR34, CSR_PMPADDR35, CSR_PMPADDR36, CSR_PMPADDR37, CSR_PMPADDR38, CSR_PMPADDR39, CSR_PMPADDR40, CSR_PMPADDR41, CSR_PMPADDR42, CSR_PMPADDR43, CSR_PMPADDR44, CSR_PMPADDR45, CSR_PMPADDR46, CSR_PMPADDR47, CSR_PMPADDR48, CSR_PMPADDR49, CSR_PMPADDR50, CSR_PMPADDR51, CSR_PMPADDR52, CSR_PMPADDR53, CSR_PMPADDR54, CSR_PMPADDR55, CSR_PMPADDR56, CSR_PMPADDR57, CSR_PMPADDR58, CSR_PMPADDR59, CSR_PMPADDR60, CSR_PMPADDR61, CSR_PMPADDR62, CSR_PMPADDR63): New CSR macros. gas/ChangeLog: * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise.	5 years ago
Alan Modra	ccbaaa3617	PR28882, build failure with gcc-4.2 due to use of 0b literals PR 28882 * elf/loongarch.h: Replace binary literals with hex.	5 years ago
Bhuvanendra Kumar N	e951225303	gdb/fortran: support ptype and print commands for namelist variables Gfortran supports namelists (a Fortran feature); it emits DW_TAG_namelist and DW_TAG_namelist_item dies. But gdb does not process these dies and does not support 'print' or 'ptype' commands on namelist variables. An attempt to print namelist variables results in gdb bailing out with the error message as shown below. (gdb) print nml No symbol "nml" in current context. This commit is to make the print and ptype commands work for namelist variables and its items. Sample output of these commands is shared below, with fixed gdb. (gdb) ptype nml type = Type nml integer(kind=4) :: a integer(kind=4) :: b End Type nml (gdb) print nml $1 = ( a = 10, b = 20 )	5 years ago
Cary Coutant	dfbcbf85ea	Rename EM_56800V4 to EM_56800EF. include/elf: * common.h: Rename EM_56800V4 to EM_56800EF.	5 years ago
Cary Coutant	9d5d41c405	Add new e_machine values. include/elf: * common.h: Add EM_U16_U8CORE, EM_TACHYUM, EM_56800V4.	5 years ago
Klaus Ziegler	b6437be687	Fix a probem building the binutils on SPARC/amd64 PR 28816 * elf/common.h (AT_SUN_HWCAP): Make definition conditional.	5 years ago
Nick Clifton	a74e1cb344	Add markers for 2.38 branch	5 years ago
Alan Modra	ff66e8c5be	PR28751 mbind2a / mbind2b regressions on powerpc-linux include/ bfdlink.h (struct bfd_link_info): Add commonpagesize_is_set. ld/ PR 28751 * emultempl/elf.em (handle_option): Set commonpagesize_is_set. * ldelf.c (ldelf_after_parse): Don't error when only one of -z max-page-size or -z common-page-size is given, correct the other value to make it sane. * testsuite/ld-elf/elf.exp (mbind2a, mbind2b): Do not pass -z max-page-size.	5 years ago
Nick Clifton	ce2d3708bc	Synchronize binutils libiberty sources with gcc version. +2021-12-30 Lancelot SIX <lsix@lancelotsix.com> + + * cp-demangle.c (d_clone_suffix): Support digits in clone tag + names. + * testsuite/demangle-expected: Check demangling of clone symbols + with digits in name. + +2021-12-16 H.J. Lu <hjl.tools@gmail.com> + + Revert: + 2021-12-16 H.J. Lu <hjl.tools@gmail.com> + + * Makefile.in (AR): Add @AR_PLUGIN_OPTION@ + (RANLIB): Add @RANLIB_PLUGIN_OPTION@. + (configure_deps): Depend on ../config/gcc-plugin.m4. + * configure.ac: AC_SUBST AR_PLUGIN_OPTION and + RANLIB_PLUGIN_OPTION. + * aclocal.m4: Regenerated. + * configure: Likewise. + +2021-12-15 H.J. Lu <hjl.tools@gmail.com> + + * Makefile.in (AR): Add @AR_PLUGIN_OPTION@ + (RANLIB): Add @RANLIB_PLUGIN_OPTION@. + (configure_deps): Depend on ../config/gcc-plugin.m4. + * configure.ac: AC_SUBST AR_PLUGIN_OPTION and + RANLIB_PLUGIN_OPTION. + * aclocal.m4: Regenerated. + * configure: Likewise. + +2021-11-29 Eric Gallager <egallager@gcc.gnu.org> + + PR other/103021 + * Makefile.in: Use ETAGS variable in TAGS target. + * configure: Regenerate. + * configure.ac: Allow ETAGS variable to be overridden. + +2021-11-29 Andrew Pinski <apinski@marvell.com> + + * make-temp-file.c (try_dir): Check to see if the dir + is actually a directory. + +2021-10-22 Eric Gallager <egallager@gcc.gnu.org> + + PR other/102663 + * Makefile.in: Allow dvi-formatted documentation + to be installed. + +2021-10-17 Lu?s Ferreira <contact@lsferreira.net> + + PR d/102618 + * d-demangle.c (dlang_parse_qualified): Handle anonymous + symbols correctly. + * testsuite/d-demangle-expected: New tests to cover anonymous + symbols. + +2021-10-14 Lu?s Ferreira <contact@lsferreira.net> + + * testsuite/d-demangle-expected: Add test case for function literals. + +2021-10-14 Lu?s Ferreira <contact@lsferreira.net> + + * testsuite/d-demangle-expected: Add test cases for simple special + mangles. + +2021-10-12 Lu?s Ferreira <contact@lsferreira.net> + + * d-demangle.c (dlang_parse_qualified): Remove redudant parenthesis + around lhs and rhs of assignments. + +2021-10-01 Lu?s Ferreira <contact@lsferreira.net> + + * testsuite/d-demangle-expected: Add missing format for new test + +2021-09-23 Lu?s Ferreira <contact@lsferreira.net> + + * d-demangle.c (dlang_Type): Validate MANGLED is nonnull. + * testsuite/d-demangle-expected: New test. + +2021-09-23 Lu?s Ferreira <contact@lsferreira.net> + + * d-demangle.c (dlang_symbol_backref): Ensure strlen of + string is less than length computed by dlang_number. + +2021-09-01 Iain Sandoe <iain@sandoe.co.uk> * configure: Regenerate. + * configure.ac: Do not search for sbrk on Darwin. + * xmalloc.c: Do not declare sbrk unless it has been found + by configure. + +2021-08-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * d-demangle.c (dlang_identifier): Skip over fake parent manglings. + * testsuite/d-demangle-expected: Add tests. + +2021-08-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * d-demangle.c (dlang_parse_arrayliteral): Add 'info' parameter. + (dlang_parse_assocarray): Likewise. + (dlang_parse_structlit): Likewise. + (dlang_value): Likewise. Handle function literal symbols. + (dlang_template_args): Pass 'info' to dlang_value. + * testsuite/d-demangle-expected: Add new test. + +2021-08-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * d-demangle.c (dlang_attributes): Handle typeof(null). + (dlang_type): Likewise. Demangle 'n' as typeof(null). + testsuite/d-demangle-expected: Update tests. + +2021-08-23 Iain Sandoe <iain@sandoe.co.uk> + + * simple-object-mach-o.c (simple_object_mach_o_write_segment): + Cast the first argument to set_32 as needed. -2021-07-03 Nick Clifton <nickc@redhat.com> +2021-08-18 Iain Sandoe <iain@sandoe.co.uk> + * simple-object-mach-o.c (simple_object_mach_o_write_segment): + Arrange to swap the LTO index tables where needed. # Please enter the commit message for your changes. Lines starting	5 years ago
H.J. Lu	6a91be8666	ld: Initial DT_RELR support Add a -z pack-relative-relocs option to enable DT_RELR and create a relr.dyn section for DT_RELR. DT_RELR is implemented with the linker relaxation infrastructure, but it doesn't require the --relax option enabled. -z pack-relative-relocs implies -z combreloc. -z nocombreloc implies -z nopack-relative-relocs. -z pack-relative-relocs is chosen over the similar option in lld, --pack-dyn-relocs=relr, to implement a glibc binary lockout mechanism with a special glibc version symbol, to avoid random crashes of DT_RELR binaries with the existing glibc binaries. bfd/ * elf-bfd.h (elf_link_hash_table): Add srelrdyn. * elflink.c (_bfd_elf_link_create_dynamic_sections): Create a .relr.dyn section for DT_RELR. include/ * bfdlink.h (bfd_link_info): Add enable_dt_relr. ld/ * News: Mention -z pack-relative-relocs and -z nopack-relative-relocs. * ld.texi: Document -z pack-relative-relocs and -z nopack-relative-relocs. * ldelf.c (ldelf_after_parse): Disable DT_RELR if not building PIE nor shared library. Add 3 spare dynamic tags for DT_RELR, DT_RELRSZ and DT_RELRENT. * ldlang.c (lang_relax_sections): Also enable relaxation if DT_RELR is enabled. * emulparams/elf32_x86_64.sh: Source dt-relr.sh. * emulparams/elf_i386.sh: Likewise. * emulparams/elf_x86_64.sh: Likewise. * emulparams/dt-relr.sh: New file. * scripttempl/elf.sc: Support .relr.dyn.	5 years ago
Clément Chigot	add588a8ef	gas: add visibility support for XCOFF XCOFF assembly defines the visibility using an additional argument on several pseudo-ops: .globl, .weak, .extern and .comm. This implies that .globl and .weak syntax is different than the usual GNU syntax. But we want to provide compatibility with AIX assembler, especially because GCC is generating the visibility using this XCOFF syntax. PR 22085 bfd/ChangeLog: * coffcode.h (coff_write_object_contents): Change XCOFF header vstamp field to 2. * coffgen.c (coff_print_symbol): Increase the size for n_type. gas/ChangeLog: * config/tc-ppc.c (ppc_xcoff_get_visibility): New function. (ppc_globl): New function. (ppc_weak): New function. (ppc_comm): Add visibility field support. (ppc_extern): Likewise. * testsuite/gas/all/cofftag.d: Adjust to new n_type size providing by objdump. * testsuite/gas/ppc/test1xcoff32.d: Likewise. * testsuite/gas/ppc/aix.exp: Add new tests. * testsuite/gas/ppc/xcoff-visibility-1-32.d: New test. * testsuite/gas/ppc/xcoff-visibility-1-64.d: New test. * testsuite/gas/ppc/xcoff-visibility-1.s: New test. include/ChangeLog: * coff/internal.h (SYM_V_INTERNAL, SYM_V_HIDDEN, SYM_V_PROTECTED, SYM_V_EXPORTED, SYM_V_MASK): New defines. * coff/xcoff.h (struct xcoff_link_hash_entry): Add visibility field. ld/ChangeLog: * testsuite/ld-pe/pr19803.d: Adjust to new n_type size providing by objdump.	5 years ago
H.J. Lu	74e315dbfe	elf: Set p_align to the minimum page size if possible Currently, on 32-bit and 64-bit ARM, it seems that ld generates p_align values of 0x10000 even if no section alignment is greater than 0x1000. The issue is more general and probably affects other targets with multiple page sizes. While file layout absolutely must take 64K page size into account, that does not have to be reflected in the p_align value. If running on a 64K kernel, the file will be loaded at a 64K page boundary by necessity. On a 4K kernel, 64K alignment is not needed. The glibc loader has been fixed to honor p_align: https://sourceware.org/bugzilla/show_bug.cgi?id=28676 similar to kernel: commit ce81bb256a224259ab686742a6284930cbe4f1fa Author: Chris Kennelly <ckennelly@google.com> Date: Thu Oct 15 20:12:32 2020 -0700 fs/binfmt_elf: use PT_LOAD p_align values for suitable start address This means that on 4K kernels, we will start to do extra work for 64K p_align, but this pointless for pretty much all binaries (whose section alignment rarely exceeds 16). The minimum page size is used, instead of the maximum section alignment due to this glibc bug: https://sourceware.org/bugzilla/show_bug.cgi?id=28688 It has been fixed in glibc 2.35. But linker output must work on existing glibc binaries. 1. Set p_align to the minimum page size while laying out segments aligning to the maximum page size or section alignment. The run-time loader can align segments to the minimum page size or above, depending on system page size. 2. If -z max-page-size=NNN is used, p_align will be set to the maximum page size or the largest section alignment. 3. If a section requires alignment higher than the minimum page size, don't set p_align to the minimum page size. 4. If a section requires alignment higher than the maximum page size, set p_align to the section alignment. 5. For objcopy, when the minimum page size != the maximum page size, p_align may be set to the minimum page size while segments are aligned to the maximum page size. In this case, the input p_align will be ignored and the maximum page size will be used to align the ouput segments. 6. Update linker to disallow the common page size > the maximum page size. 7. Update linker to avoid the common page size > the maximum page size. 8. Adjust pru_irq_map-1.d to expect p_align == sh_addralign: Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .text PROGBITS 20000000 00007c 000004 00 AX 0 0 4 ... Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000074 0x00000000 0x00000000 0x00008 0x00008 RW 0x1 LOAD 0x00007c 0x20000000 0x20000000 0x00004 0x00004 R E 0x4 vs. Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .text PROGBITS 20000000 00007c 000004 00 AX 0 0 4 ... Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000074 0x00000000 0x00000000 0x00008 0x00008 RW 0x1 LOAD 0x00007c 0x20000000 0x20000000 0x00004 0x00004 R E 0x1 To enable this linker optimization, the backend should define ELF_P_ALIGN to ELF_MINPAGESIZE. bfd/ PR ld/28689 PR ld/28695 * elf-bfd.h (elf_backend_data): Add p_align. * elf.c (assign_file_positions_for_load_sections): Set p_align to the default p_align value while laying out segments aligning to maximum page size or section alignment. (elf_is_p_align_valid): New function. (copy_elf_program_header): Call elf_is_p_align_valid to determine if p_align is valid. * elfxx-target.h (ELF_P_ALIGN): New. Default to 0. (elfNN_bed): Add ELF_P_ALIGN. * elfxx-x86.h (ELF_P_ALIGN): New. Set to ELF_MINPAGESIZE. include/ PR ld/28689 PR ld/28695 * bfdlink.h (bfd_link_info): Add maxpagesize_is_set. ld/ PR ld/28689 PR ld/28695 * emultempl/elf.em (gld${EMULATION_NAME}_handle_option): Set link_info.maxpagesize_is_set for -z max-page-size=NNN. * ldelf.c (ldelf_after_parse): Disallow link_info.commonpagesize > link_info.maxpagesize. * testsuite/ld-elf/elf.exp: Pass -z max-page-size=0x4000 to linker to build mbind2a and mbind2b. * testsuite/ld-elf/header.d: Add -z common-page-size=0x100. * testsuite/ld-elf/linux-x86.exp: Add PR ld/28689 tests. * testsuite/ld-elf/p_align-1.c: New file. * testsuite/ld-elf/page-size-1.d: New test. * testsuite/ld-elf/pr26936.d: Add -z common-page-size=0x1000. * testsuite/ld-elf/seg.d: Likewise. * testsuite/ld-scripts/rgn-at5.d: Likewise. * testsuite/ld-pru/pru_irq_map-1.d: Append 1 to name. Adjust expected PT_LOAD segment alignment. * testsuite/ld-pru/pru_irq_map-2.d: Append 2 to name. * testsuite/ld-scripts/pr23571.d: Add -z max-page-size=0x1000.	5 years ago
Alan Modra	a2c5833233	Update year range in copyright notice of binutils files The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out /po/.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.	5 years ago
Joel Brobecker	4a94e36819	Automatic Copyright Year update after running gdb/copyright.py This commit brings all the changes made by running gdb/copyright.py as per GDB's Start of New Year Procedure. For the avoidance of doubt, all changes in this commits were performed by the script.	5 years ago
Vineet Gupta	a63375ac33	RISC-V: Hypervisor ext: support Privileged Spec 1.12 This is the Hypervisor Extension 1.0 - Hypervisor Memory-Management Instructions HFENCE.VVMA, HFENCE.GVMA, - Hypervisor Virtual Machine Load and Store Instructions HLV.B, HLV.BU, HSV.B, HLV.H, HLV.HU, HLVX.HU, HSB.H, HLV.W, HLV.WU, HLVX.WU, HSV.W, HLV.D, HSV.D - Hypervisor CSRs (some new, some address changed) hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip, htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah, vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp, Note that following were added already as part of svinval extension support: HINVAL.GVMA, HINVAL.VVMA Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Nelson Chu <nelson.chu@sifive.com> bfd/ * cpu-riscv.c (riscv_priv_specs): Added entry for 1.12. * cpu-riscv.h (enum riscv_spec_class): Added PRIV_SPEC_CLASS_1P12. gas/ * config/tc-riscv.c (abort_version): Updated comment. (validate_riscv_insn): Annotate switch-break. * testsuite/gas/riscv/h-ext-32.d: New testcase for hypervisor. * testsuite/gas/riscv/h-ext-32.s: Likewise. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/h-ext-64.s: Likewise. include/ * opcode/riscv-opc.h: Added encodings for hypervisor csrs and instrcutions. opcodes/ * riscv-opc.c (riscv_opcodes): Added hypervisor instrcutions.	5 years ago
Vineet Gupta	5c3ffbc4dd	RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests This makes way for a clean 1.12 based Hypervisor Ext support. There are no known implementors of 1.9.1 H-ext. (Per Jim, kendryte k210 is based on priv spec 1.9.1, but it seems unlikely that they implemented H-ext). Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Nelson Chu <nelson.chu@sifive.com> gas/ * testsuite/gas/riscv/csr-dw-regnums.d: Drop the hypervisor csrs defined in the privileged spec 1.9.1. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg.s: Likewise. include/ * opcode/riscv-opc.h: Drop the hypervisor csrs defined in the privileged spec 1.9.1.	5 years ago
Richard Sandiford	a2b1ea81ba	arm: Add support for Armv9.1-A to Armv9.3-A This patch adds AArch32 support for -march=armv9.[123]-a. The behaviour of the new options can be expressed using a combination of existing feature flags and tables. The cpu_arch_ver entries for ARM_ARCH_V9_2A and ARM_ARCH_V9_3A are technically redundant but it seemed less surprising to include them anyway. include/ * opcode/arm.h (ARM_ARCH_V9_1A, ARM_ARCH_V9_2A): New macros. (ARM_ARCH_V9_3A): Likewise. gas/ * doc/c-arm.texi: Add armv9.1-a, armv9.2-a and armv9.3-a. * config/tc-arm.c (armv91a_ext_table, armv92a_ext_table): New macros. (armv93a_ext_table): Likewise. (arm_archs): Add armv9.1-a, armv9.2-a and armv9.3-a. (cpu_arch_ver): Add ARM_ARCH_V9_1A, ARM_ARCH_V9_2A and ARM_ARCH_V9_3A. * NEWS: Mention the above. * testsuite/gas/arm/attr-march-armv9_1-a.d: New test. * testsuite/gas/arm/attr-march-armv9_2-a.d: Likewise. * testsuite/gas/arm/attr-march-armv9_3-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv9.1-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv9.2-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv9.3-a.d: Likewise. * testsuite/gas/arm/i8mm-armv9.1-a.d: Likewise. * testsuite/gas/arm/i8mm-armv9.2-a.d: Likewise. * testsuite/gas/arm/i8mm-armv9.3-a.d: Likewise.	5 years ago
Richard Sandiford	b3e4d9326f	arm: Add support for Armv8.7-A and Armv8.8-A This patch adds AArch32 support for -march=armv8.[78]-a. The behaviour of the new options can be expressed using a combination of existing feature flags and tables. The cpu_arch_ver entries are technically redundant but it seemed less surprising to include them anyway. include/ * opcode/arm.h (ARM_ARCH_V8_7A, ARM_ARCH_V8_8A): New macros. gas/ * doc/c-arm.texi: Add armv8.7-a and armv8.8-a. * config/tc-arm.c (armv87a_ext_table, armv88a_ext_table): New macros. (arm_archs): Add armv8.7-a and armv8.8-a. (cpu_arch_ver): Add ARM_ARCH_V8_7A and ARM_ARCH_V8_8A. * NEWS: Mention the above. * testsuite/gas/arm/attr-march-armv8_7-a.d: New test. * testsuite/gas/arm/attr-march-armv8_8-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv8.7-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv8.8-a.d: Likewise. * testsuite/gas/arm/i8mm-armv8.7-a.d: Likewise. * testsuite/gas/arm/i8mm-armv8.8-a.d: Likewise.	5 years ago
Richard Sandiford	3518022233	aarch64: Add support for Armv9.1-A to Armv9.3-A This patch adds AArch64 support for -march=armv9.[123]-a. The behaviour of the new options can be expressed using a combination of existing feature flags, so we don't need to eat into the vanishing number of spare AARCH64_FEATURE_* bits. Hoewver, it was more convenient to separate out the \|s of feature flags so that Armv9.1-A could reuse the set for Armv8.6-A, and so on. include/ * opcode/aarch64.h (AARCH64_ARCH_V8_FEATURES): New macro, split out from... (AARCH64_ARCH_V8): ...here. (AARCH64_ARCH_V8_1_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_1): ...here. (AARCH64_ARCH_V8_2_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_2): ...here. (AARCH64_ARCH_V8_3_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_3): ...here. (AARCH64_ARCH_V8_4_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_4): ...here. (AARCH64_ARCH_V8_5_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_5): ...here. (AARCH64_ARCH_V8_6_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_6): ...here. (AARCH64_ARCH_V8_7_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_7): ...here. (AARCH64_ARCH_V8_8_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_8): ...here. (AARCH64_ARCH_V9_FEATURES): New macro, split out from... (AARCH64_ARCH_V9): ...here. (AARCH64_ARCH_V9_1_FEATURES, AARCH64_ARCH_V9_1): New macros. (AARCH64_ARCH_V9_2_FEATURES, AARCH64_ARCH_V9_2): New macros. (AARCH64_ARCH_V9_3_FEATURES, AARCH64_ARCH_V9_3): New macros. gas/ * doc/c-aarch64.texi: Add armv9.1-a, armv9-2-a and armv9.3-a. * config/tc-aarch64.c (aarch64_archs): Likewise. * NEWS: Mention the above. * testsuite/gas/aarch64/armv9_invalid.d, testsuite/gas/aarch64/armv9_invalid.s, testsuite/gas/aarch64/armv9_invalid.l: New test. * testsuite/gas/aarch64/armv9_1.d, testsuite/gas/aarch64/armv9_1.s: Likewise. * testsuite/gas/aarch64/armv9_1_invalid.d, testsuite/gas/aarch64/armv9_1_invalid.s, testsuite/gas/aarch64/armv9_1_invalid.l: Likewise. * testsuite/gas/aarch64/armv9_2.d, testsuite/gas/aarch64/armv9_2.s: Likewise. * testsuite/gas/aarch64/armv9_2_invalid.d, testsuite/gas/aarch64/armv9_2_invalid.s, testsuite/gas/aarch64/armv9_2_invalid.l: Likewise. * testsuite/gas/aarch64/armv9_3.d, testsuite/gas/aarch64/armv9_3.s: Likewise.	5 years ago
Nelson Chu	23ff54c27d	RISC-V: Support svinval extension with frozen version 1.0. According to the privileged spec, there are five new instructions for svinval extension. Two of them (HINVAL.VVMA and HINVAL.GVMA) need to enable the hypervisor extension. But there is no implementation of hypervisor extension in mainline for now, so let's consider the related issues later. 31..25 24..20 19..15 14..12 11...7 6..2 1..0 sinval.vma 0001011 rs2 rs1 000 00000 11100 11 sfence.w.inval 0001100 00000 00000 000 00000 11100 11 sfence.inval.ir 0001100 00001 00000 000 00000 11100 11 hinval.vvma 0010011 rs2 rs1 000 00000 11100 11 hinval.gvma 0110011 rs2 rs1 000 00000 11100 11 This patch is cherry-picked from the riscv integration branch since the svinval extension is frozen for now. Besides, we fix the funct7 encodings of hinval.vvma and hinval.gvma, from 0x0011011 and 0x0111011 to 0x0010011 and 0x0110011. bfd/ * elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval. (riscv_multi_subset_supports): Handle INSN_CLASS_SVINVAL. gas/ * testsuite/gas/riscv/svinval.d: New testcase. * testsuite/gas/riscv/svinval.s: Likewise. include/ * opcode/riscv-opc.h: Added encodings for svinval. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SVINVAL. opcodes/ * riscv-opc.c (riscv_opcodes): Added svinval instructions.	5 years ago
John Baldwin	b4992e9990	Support AT_FXRNG and AT_KPRELOAD on FreeBSD. FreeBSD's kernel has recently added two new ELF auxiliary vector entries. AT_FXRNG points to a root seed version for the kernel's PRNG. Userland can use this to reseed a userland PRNG after the kernel's PRNG has reseeded. AT_KPRELOAD is the base address of a kernel-provided vDSO. This change displays the proper name and description of these entries in 'info auxv'. include/ChangeLog: * elf/common.h (AT_FREEBSD_FXRNG, AT_FREEBSD_KPRELOAD): Define.	5 years ago
Mike Frysinger	20a8e078cc	sim: reorder header includes We're including system headers after local headers in a bunch of places, but this leads to conflicts when our local headers happen to define symbols that show up in the system headers. Use the more standard order of: * config.h (via defs.h) * system headers * local library headers (e.g. bfd & libiberty) * sim specific headers	5 years ago
Richard Sandiford	bcca550b3d	aarch64: Add BC instruction This patch adds support for the Armv8.8-A BC instruction. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/BC-cond--Branch-Consistent-conditionally-?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_HBC): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_HBC. opcodes/ * aarch64-tbl.h (aarch64_feature_hbc): New variable. (HBC, HBC_INSN): New macros. (aarch64_opcode_table): Add BC.C. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document +hbc. * config/tc-aarch64.c (aarch64_features): Add "hbc". * testsuite/gas/aarch64/hbc.s, testsuite/gas/aarch64/hbc.d: New test. * testsuite/gas/aarch64/hbc-invalid.s, testsuite/gas/aarch64/hbc-invalid.l, testsuite/gas/aarch64/hbc-invalid.d: New test.	5 years ago
Richard Sandiford	63eff94751	aarch64: Enforce P/M/E order for MOPS instructions The MOPS instructions should be used as a triple, such as: cpyfp [x0]!, [x1]!, x2! cpyfm [x0]!, [x1]!, x2! cpyfe [x0]!, [x1]!, x2! The registers should also be the same for each writeback operand. This patch adds a warning for code that doesn't follow this rule, along similar lines to the warning that we already emit for invalid uses of MOVPRFX. include/ * opcode/aarch64.h (C_SCAN_MOPS_P, C_SCAN_MOPS_M, C_SCAN_MOPS_E) (C_SCAN_MOPS_PME): New macros. (AARCH64_OPDE_A_SHOULD_FOLLOW_B): New aarch64_operand_error_kind. (AARCH64_OPDE_EXPECTED_A_AFTER_B): Likewise. (aarch64_operand_error): Make each data value a union between an int and a string. opcodes/ * aarch64-tbl.h (MOPS_CPY_OP1_OP2_INSN): Add scan flags. (MOPS_SET_OP1_OP2_INSN): Likewise. * aarch64-opc.c (set_out_of_range_error): Update after change to aarch64_operand_error. (set_unaligned_error, set_reg_list_error): Likewise. (init_insn_sequence): Use a 3-instruction sequence for MOPS P instructions. (verify_mops_pme_sequence): New function. (verify_constraints): Call it. * aarch64-dis.c (print_verifier_notes): Handle AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. gas/ * config/tc-aarch64.c (operand_mismatch_kind_names): Add entries for AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. (operand_error_higher_severity_p): Check that AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B come between AARCH64_OPDE_RECOVERABLE and AARCH64_OPDE_SYNTAX_ERROR; their relative order is not significant. (record_operand_error_with_data): Update after change to aarch64_operand_error. (output_operand_error_record): Likewise. Handle AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. * testsuite/gas/aarch64/mops_invalid_2.s, testsuite/gas/aarch64/mops_invalid_2.d, testsuite/gas/aarch64/mops_invalid_2.l: New test.	5 years ago
Richard Sandiford	6327658ee7	aarch64: Add support for +mops This patch adds support for FEAT_MOPS, an Armv8.8-A extension that provides memcpy and memset acceleration instructions. I took the perhaps controversial decision to generate the individual instruction forms using macros rather than list them out individually. This becomes useful with a follow-on patch to check that code follows the correct P/M/E sequence. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS. (AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd. (AARCH64_OPND_MOPS_ADDR_Rs): Likewise. (AARCH64_OPND_MOPS_WB_Rn): Likewise. opcodes/ * aarch64-asm.h (ins_x0_to_x30): New inserter. * aarch64-asm.c (aarch64_ins_x0_to_x30): New function. * aarch64-dis.h (ext_x0_to_x30): New extractor. * aarch64-dis.c (aarch64_ext_x0_to_x30): New function. * aarch64-tbl.h (aarch64_feature_mops): New feature set. (aarch64_feature_mops_memtag): Likewise. (MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN) (MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN) (MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN) (MOPS_SET_INSN): New macros. (aarch64_opcode_table): Add MOPS instructions. (aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (verify_three_different_regs): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * doc/c-aarch64.texi: Document +mops. * config/tc-aarch64.c (parse_x0_to_x30): New function. (parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (aarch64_features): Add "mops". * testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test. * testsuite/gas/aarch64/mops_invalid.s, * testsuite/gas/aarch64/mops_invalid.d, * testsuite/gas/aarch64/mops_invalid.l: Likewise.	5 years ago

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2809 Commits (5890af36e5112bcbb8d7555e63570f68466e6944)