binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Chao-ying Fu	de9a3e5195	2008-11-06 Chao-ying Fu <fu@mips.com> * mips.h: Doucument '1' for 5-bit sync type.	18 years ago
H.J. Lu	1ca35711f4	gas/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * config/tc-ia64.c (CR_IIB0): New. (CR_IIB1): Likewise. (cr): Add cr.iib0 and cr.iib1. (specify_resource): Handle IA64_RS_CR_IIB and CR_IIB0/CR_IIB1. gas/testsuite/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * gas/ia64/dv-raw-err.s: Add tests for cr.iib0 and cr.iib1. * gas/ia64/dv-waw-err.s: Likewise. * gas/ia64/regs.s: Likewise. * gas/ia64/dv-raw-err.l: Updated. * gas/ia64/dv-waw-err.l: Likewise. * gas/ia64/regs.d: Likewise. include/opcode/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update IA64_RS_CR. opcodes/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1. * ia64-gen.c (lookup_specifier): Likewise. * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1. * ia64-raw.tbl: Likewise. * ia64-waw.tbl: Likewise. * ia64-asmtab.c: Regenerated.	18 years ago
Eric B. Weddington	7b21ac3f45	Add AVR architectures avr25, avr31, avr35, and avr51 to match GCC. bfd/ * archures.c (bfd_mach_avr25, bfd_mach_avr31, bfd_mach_avr35, bfd_mach_avr51): New. * bfd-in2.h: Regenerate. * cpu-avr.c (arch_info_struct): Add avr25, avr31, avr35, and avr51 architectures. Change comments to match architecture comments in GCC. (compatible): Add test for new AVR architectures. * elf32-avr.c (bfd_elf_avr_final_write_processing): Recognize bfd_mach_avr25, bfd_mach_avr31, bfd_mach_avr35 and bfd_mach_avr51. (elf32_avr_object_p): Recognize E_AVR_MACH_AVR25, E_AVR_MACH_AVR31, E_AVR_MACH_AVR35 and E_AVR_MACH_AVR51. gas/ * config/tc-avr.c (mcu_types): Add avr25, avr31, avr35, and avr51 architectures. Reorganize list to put mcu types in correct architectures and to order list same as in GCC. Use new ISA definitions in include/opcode/avr.h. * doc/c-avr.texi: Add avr25, avr31, avr35, and avr51 architecture descriptions. Reorganize descriptions to put mcu types in correct architectures and to order lists same as in GCC. include/ * elf/avr.h (E_AVR_MACH_AVR25, E_AVR_MACH_AVR31, E_AVR_MACH_AVR35, E_AVR_MACH_AVR51): Define. (EF_AVR_MACH): Redefine to 0x7F. * opcode/avr.h (AVR_ISA_TINY3, AVR_ISA_ALL, AVR_ISA_USB162): Remove. (AVR_ISA_AVR3): Redefine. (AVR_ISA_AVR1, AVR_ISA_AVR2, AVR_ISA_AVR31, AVR_ISA_AVR35, AVR_ISA_AVR3_ALL, AVR_ISA_AVR4, AVR_ISA_AVR5, AVR_ISA_AVR51, AVR_ISA_AVR6): Define. ld/ * Makefile.am (ALL_EMULATIONS): Add eavr25.o, eavr31.o, eavr35.o, and eavr51.o. Add rules for eavr25.c, eavr31.c, eavr35.c, eavr51.c. * Makefile.in: Regenerate. * configure.tgt (avr--, targ_extra_emuls): Add avr25, avr31, avr35 and avr51. * emulparams/avr25.sh: New file. * emulparams/avr31.sh: New file. * emulparams/avr35.sh: New file. * emulparams/avr51.sh: New file.	18 years ago
Peter Bergner	9b4e57660d	gas/ * config/tc-ppc.c (parse_cpu): Rename altivec_or_spe to retain_flags. Handle -mvsx and -mpower7. (md_show_usage): Document -mpower7 and -mvsx. * doc/as.texinfo (Target PowerPC): Document -mvsx. * doc/c-ppc.texi (PowerPC-Opts): Document -mvsx and -mpower7. gas/testsuite/ * gas/ppc/power7.d: New. * gas/ppc/power7.s: Likewise. * gas/ppc/ppc.exp: Run power7 test. include/opcode/ * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. opcodes/ * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options. (print_insn_powerpc): Prepend 'vs' when printing VSX registers. (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx. * ppc-opc.c (insert_xt6): New static function. (extract_xt6): Likewise. (insert_xa6): Likewise. (extract_xa6: Likewise. (insert_xb6): Likewise. (extract_xb6): Likewise. (insert_xb6s): Likewise. (extract_xb6s): Likewise. (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK, XX3DM_MASK, PPCVSX): New. (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x", "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".	18 years ago
Alan Modra	081ba1b3c0	include/opcode/ * ppc.h (PPC_OPCODE_405): Define. (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define. gas/ * config/tc-ppc.c (parse_cpu): Separate handling of -m403/405. (md_show_usage): Likewise. opcodes/ * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields. * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands. (insert_sprg, PPC405): Use PPC_OPCODE_405. (powerpc_opcodes): Add Xilinx APU related opcodes.	18 years ago
Peter Bergner	fa452fa683	include/opcode/ * ppc.h (ppc_cpu_t): New typedef. (struct powerpc_opcode <flags>): Use it. (struct powerpc_operand <insert, extract>): Likewise. (struct powerpc_macro <flags>): Likewise. gas/ * config/tc-ppc.c (ppc_cpu): Use ppc_cpu_t typedef. (ppc_insert_operand): Likewise. (ppc_machine): Likewise. * config/tc-ppc.h: #include "opcode/ppc.h" (struct _ppc_fix_extra <ppc_cpu>): Use ppc_cpu_t typedef. (ppc_cpu): Update extern decl. opcodes/ * ppc-dis.c (print_insn_powerpc): Update prototye to use new ppc_cpu_t typedef. (struct dis_private): New. (POWERPC_DIALECT): New define. (powerpc_dialect): Renamed to... (powerpc_init_dialect): This. Update to use ppc_cpu_t and struct dis_private. (print_insn_big_powerpc): Update for using structure in info->private_data. (print_insn_little_powerpc): Likewise. (operand_value_powerpc): Change type of dialect param to ppc_cpu_t. (skip_optional_operands): Likewise. (print_insn_powerpc): Likewise. Remove initialization of dialect. * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp, extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe, extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr, extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm, insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe, insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs, insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect param to be of type ppc_cpu_t. Update prototype.	18 years ago
Nick Clifton	dd3cbb7ef7	* mips.h: Document new field descriptors +Q. (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptor +Q. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq, seqi, sne and snei. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptor +Q. (mips_ip): Likewise. (macro_build): Likewise. (CPU_HAS_SEQ): New macro. (macro2) <M_SEQ_I, M_SNE_I>: Use it. Emit seq/sne and seqi/snei. gas/testsuite/ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for seq* and sne. gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: Add tests for seqi and snei.	18 years ago
Nick Clifton	bb35fb24c1	include/opcode/ * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. Update comment before MIPS16 field descriptors to mention MIPS16. (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for BBIT. (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): New bit masks and shift counts for cins and exts. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptors +x, +X, +p, +P, +s, +S. (mips_ip): Likewise. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptors +x, +p, +s, +S. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions baddu, bbit, cins, dmul, pop, dpop, exts, mtm, mtp, syncs, syncw, syncws, vm3mulu, vm0 and vmulu. gas/testsuite/ gas/mips/octeon.s, gas/mips/octeon.d: Add tests for baddu, bbit, cins, dmul, pop, dpop, exts, mtm, mtp, syncs, syncw, syncws, vm3mulu, vm0 and vmulu. gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: New test. * gas/mips/mips.exp: Run it. Run octeon test with run_dump_test_arches.	18 years ago
Adam Nemet	d079967181	* mips.h (INSN_MACRO): Move it up to the the pinfo macros. (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.	19 years ago
Nick Clifton	e210c36bb1	Move entries for changes in sub-directories into the changelogs in those sub- directories.	19 years ago
Alan Modra	19a6653ce8	ppc e500mc support	19 years ago
H.J. Lu	c0f3af977b	binutils/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (dwarf_regnames_i386): Add AVX registers. (dwarf_regnames_x86_64): Likewise. gas/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx. * doc/c-i386.texi: Add avx, aes, clmul and fma to -march=. Document -msse2avx, .avx, .aes, .clmul and .fma. * config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New. (vex_prefix): Likewise. (sse2avx): Likewise. (CPU_FLAGS_ARCH_MATCH): Likewise. (CPU_FLAGS_64BIT_MATCH): Likewise. (CPU_FLAGS_32BIT_MATCH): Likewise. (CPU_FLAGS_PERFECT_MATCH): Likewise. (regymm): Likewise. (vex_imm4): Likewise. (fits_in_imm4): Likewise. (build_vex_prefix): Likewise. (VEX_check_operands): Likewise. (bad_implicit_operand): Likewise. (OPTION_MSSE2AVX): Likewise. (T_YMMWORD): Likewise. (_i386_insn): Add vex. (cpu_arch): Add .avx, .aes, .clmul and .fma. (cpu_flags_match): Changed to take a pointer to const template. Enable encoding SSE instructions with VEX prefix for -msse2avx. (match_mem_size): Also check ymmword. (operand_type_match): Clear ymmword. (md_begin): Allow '_' in mnemonic. (type_names): Add OPERAND_TYPE_VEX_IMM4. (process_immext): Update assert. (md_assemble): Don't call process_immext if sse2avx and immext are true. Call build_vex_prefix if vex is true. (parse_insn): Updated for cpu_flags_match. (swap_operands): Handle 5 operands. (match_template): Handle 5 operands. Updated for cpu_flags_match. Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX. (process_suffix): Handle YMMWORD_MNEM_SUFFIX. (check_byte_reg): Check regymm. (process_operands): Duplicate the destination register for -msse2avx if needed. (build_modrm_byte): Updated for instructions with VEX encoding. (output_insn): Output VEX prefix if needed. (md_longopts): Add msse2avx. (md_parse_option): Handle OPTION_MSSE2AVX. (md_show_usage): Add avx, aes, clmul, fma and -msse2avx. (intel_e09): Support YMMWORD. (intel_e11): Likewise. (intel_get_token): Likewise. gas/testsuite/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes, x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx, x86-64-avx-intel and x86-64-inval-avx. * gas/cfi/cfi-i386.s: Add tests for AVX register maps. * gas/cfi/cfi-x86_64.s: Likewise. * gas/i386/aes.d: New. * gas/i386/aes.s: Likewise. * gas/i386/aes-intel.d: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx.s: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/i386.exp: Likewise. * gas/i386/inval-avx.l: Likewise. * gas/i386/inval-avx.s: Likewise. * gas/i386/sse2avx.d: Likewise. * gas/i386/sse2avx.s: Likewise. * gas/i386/x86-64-aes.d: Likewise. * gas/i386/x86-64-aes.s: Likewise. * gas/i386/x86-64-aes-intel.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/x86-64-inval-avx.l: Likewise. * gas/i386/x86-64-inval-avx.s: Likewise. * gas/i386/x86-64-sse2avx.d: Likewise. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/rexw.s: Add AVX tests. * gas/i386/x86-64-opcode-inval.s: Remove lds/les test. * gas/cfi/cfi-i386.d: Updated. * gas/cfi/cfi-x86_64.d: Likewise. * gas/i386/arch-10.d: Likewise. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/rexw.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-opcode-inval.d: Likewise. * gas/i386/x86-64-opcode-inval-intel.d: Likewise. include/opcode/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386.h (MAX_OPERANDS): Set to 5. (MAX_MNEM_SIZE): Changed to 20. opcodes/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_register): New. (OP_E_memory): Likewise. (OP_VEX): Likewise. (OP_EX_Vex): Likewise. (OP_EX_VexW): Likewise. (OP_XMM_Vex): Likewise. (OP_XMM_VexW): Likewise. (OP_REG_VexI4): Likewise. (PCLMUL_Fixup): Likewise. (VEXI4_Fixup): Likewise. (VZERO_Fixup): Likewise. (VCMP_Fixup): Likewise. (VPERMIL2_Fixup): Likewise. (rex_original): Likewise. (rex_ignored): Likewise. (Mxmm): Likewise. (XMM): Likewise. (EXxmm): Likewise. (EXxmmq): Likewise. (EXymmq): Likewise. (Vex): Likewise. (Vex128): Likewise. (Vex256): Likewise. (VexI4): Likewise. (EXdVex): Likewise. (EXqVex): Likewise. (EXVexW): Likewise. (EXdVexW): Likewise. (EXqVexW): Likewise. (XMVex): Likewise. (XMVexW): Likewise. (XMVexI4): Likewise. (PCLMUL): Likewise. (VZERO): Likewise. (VCMP): Likewise. (VPERMIL2): Likewise. (xmm_mode): Likewise. (xmmq_mode): Likewise. (ymmq_mode): Likewise. (vex_mode): Likewise. (vex128_mode): Likewise. (vex256_mode): Likewise. (USE_VEX_C4_TABLE): Likewise. (USE_VEX_C5_TABLE): Likewise. (USE_VEX_LEN_TABLE): Likewise. (VEX_C4_TABLE): Likewise. (VEX_C5_TABLE): Likewise. (VEX_LEN_TABLE): Likewise. (REG_VEX_XX): Likewise. (MOD_VEX_XXX): Likewise. (PREFIX_0F38DB..PREFIX_0F38DF): Likewise. (PREFIX_0F3A44): Likewise. (PREFIX_0F3ADF): Likewise. (PREFIX_VEX_XXX): Likewise. (VEX_OF): Likewise. (VEX_OF38): Likewise. (VEX_OF3A): Likewise. (VEX_LEN_XXX): Likewise. (vex): Likewise. (need_vex): Likewise. (need_vex_reg): Likewise. (vex_i4_done): Likewise. (vex_table): Likewise. (vex_len_table): Likewise. (OP_REG_VexI4): Likewise. (vex_cmp_op): Likewise. (pclmul_op): Likewise. (vpermil2_op): Likewise. (m_mode): Updated. (es_reg): Likewise. (PREFIX_0F38F0): Likewise. (PREFIX_0F3A60): Likewise. (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE. (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF and PREFIX_VEX_XXX entries. (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE. (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and PREFIX_0F3ADF. (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE. Add MOD_VEX_XXX entries. (ckprefix): Initialize rex_original and rex_ignored. Store the REX byte in rex_original. (get_valid_dis386): Handle the implicit prefix in VEX prefix bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE. (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before calling get_valid_dis386. Use rex_original and rex_ignored when printing out REX. (putop): Handle "XY". (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and ymmq_mode. (OP_E_extended): Updated to use OP_E_register and OP_E_memory. (OP_XMM): Handle VEX. (OP_EX): Likewise. (XMM_Fixup): Likewise. (CMP_Fixup): Use ARRAY_SIZE. * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS, CPU_FMA_FLAGS and CPU_AVX_FLAGS. (operand_type_init): Add OPERAND_TYPE_REGYMM and OPERAND_TYPE_VEX_IMM4. (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA. (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD, VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources, VexImmExt and SSE2AVX. (operand_types): Add RegYMM, Ymmword and Vex_Imm4. * i386-opc.h (CpuAVX): New. (CpuAES): Likewise. (CpuCLMUL): Likewise. (CpuFMA): Likewise. (Vex): Likewise. (Vex256): Likewise. (VexNDS): Likewise. (VexNDD): Likewise. (VexW0): Likewise. (VexW1): Likewise. (Vex0F): Likewise. (Vex0F38): Likewise. (Vex0F3A): Likewise. (Vex3Sources): Likewise. (VexImmExt): Likewise. (SSE2AVX): Likewise. (RegYMM): Likewise. (Ymmword): Likewise. (Vex_Imm4): Likewise. (Implicit1stXmm0): Likewise. (CpuXsave): Updated. (CpuLM): Likewise. (ByteOkIntel): Likewise. (OldGcc): Likewise. (Control): Likewise. (Unspecified): Likewise. (OTMax): Likewise. (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma. (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256, vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a, vex3sources, veximmext and sse2avx. (i386_operand_type): Add regymm, ymmword and vex_imm4. * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions. * i386-reg.tbl: Add AVX registers, ymm0..ymm15. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	19 years ago
Eric B. Weddington	2460c166ae	/gas: 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (mcu_types): Add attiny167. * doc/c-avr.texi: Likewise. /include: 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> * opcode/avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.	19 years ago
Andreas Krebbel	5746fb46c8	2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added. (s390_cond_extensions): Reduced extensions to the compare related. (main): z10 cpu type option added. (expandConditionalJump): Renamed to ... (insertExpandedMnemonic): ... this. * opcodes/s390-opc.c: Re-group the operand format makros. (INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI, INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU, INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0, INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU, INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU, INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI, INSTR_SIL_RDU): New instruction formats added. (MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI, MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0, MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI, MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR, MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD, MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format masks added. (s390_opformats): New formats added "ris", "rrs", "sil". * opcodes/s390-opc.txt: Add the conditional jumps with the extensions removed from automatic expansion in s390-mkopc.c manually. (asi - trtre): Add new System z10 EC instructions. * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added. 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * config/tc-s390.c (md_parse_option): z10 option added. 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z10.d: New file. * gas/s390/zarch-z10.s: New file. * gas/s390/s390.exp: Run the z10 testcases.	19 years ago
Paul Brook	b1cc4aeb65	2008-03-09 Paul Brook <paul@codesourcery.com> bfd/ * elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new Tag_VFP_arch values. binutils/ * readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16". gas/ * config/tc-arm.c (fpu_vfp_ext_d32): New vairable. (parse_vfp_reg_list, encode_arm_vfp_reg): Use it. (arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3. (aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16. * doc/c-arm.texi: Document new ARM FPU variants. gas/testsuite/ * gas/arm/vfpv3-d16-bad.d: New test. * gas/arm/vfpv3-d16-bad.l: New test. include/opcode/ * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.	19 years ago
Paul Brook	7e8064706d	2008-03-04 Paul Brook <paul@codesourcery.com> gas/ * config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New. (arm_ext_v7m): Rename... (arm_ext_m): ... to this. Include v6-M. (do_t_add_sub): Allow narrow low-reg non flag setting adds. (do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m. (md_assemble): Allow wide msr instructions. (insns): Add classifications for v6-m instructions. (arm_cpu_option_table): Add cortex-m1. (arm_arch_option_table): Add armv6-m. (cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants. gas/testsuite/ * gas/arm/archv6m.d: New test. * gas/arm/archv6m.s: New test. * gas/arm/t16-bad.s: Test low register non flag setting add. * gas/arm/t16-bad.l: Update expected output. include/opcode/ * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.	19 years ago
Nick Clifton	7b2185f945	Change accreditation for patch for PR3134	19 years ago
Nick Clifton	af7329f0ff	PR 3134 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction with a 32-bit displacement but without the top bit of the 4th byte set. * gas/h8300/pr3134.s: New test. * gas/h8300/pr3134.d: Expected disassembly * gas/h8300/h8300.exp: Run the new test. * gas/h8300/h8300-coff.exp: Fix test for COFF based ports to accept h8300-rtemscoff not just h8300-rtems.	19 years ago
Nick Clifton	796d53134a	* cr16.h (cr16_num_optab): Declared. * cr16-opc.c (cr16_num_optab): Defined	19 years ago
Nick Clifton	d669d37f8d	PR gas/2626 * avr.h (AVR_ISA_2xxe): Define. * config/tc-avr.c (mcu_types): Change the ISA tyoe of the attiny26 to AVR_ISA_2xxe. (avr_operand): Disallow post-increment addressing in the lpm instruction for the attiny26.	19 years ago
Adam Nemet	e642969943	* mips.h: Update copyright. (INSN_CHIP_MASK): New macro. (INSN_OCTEON): New macro. (CPU_OCTEON): New macro. (OPCODE_IS_MEMBER): Handle Octeon instructions.	19 years ago
Eric B. Weddington	2b1ed17bea	/gas: 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (mcu_types): Change opcode set for at86rf401. /include: 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com> * opcode/avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.	19 years ago
Eric B. Weddington	982b62a030	/gas: 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (mcu_types): Change opcode set for avr3, at90usb82, at90usb162. * doc/c-avr.texi: Change architecture grouping for at90usb82, at90usb162. These changes support the new avr35 architecture group in gcc. /include: 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com> * opcode/avr.h (AVR_ISA_USB162): Add new opcode set. (AVR_ISA_AVR3): Likewise.	19 years ago
Mark Shinwell	350cc38db2	bfd/ * archures.c (bfd_mach_mips_loongson_2e): New. (bfd_mach_mips_loongson_2f): New. * bfd-in2.h (bfd_mach_mips_loongson_2e): New. (bfd_mach_mips_loongson_2f): New. * cpu-mips.c: Add I_loongson_2e and I_loongson_2f to anonymous enum. (arch_info_struct): Add Loongson-2E and Loongson-2F entries. * elfxx-mips.c (_bfd_elf_mips_mach): Handle Loongson-2E and Loongson-2F flags. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Add Loongson-2E and Loongson-2F entries. binutils/ * readelf.c (get_machine_flags): Handle Loongson-2E and -2F flags. gas/ * config/tc-mips.c (mips_cpu_info_table): Add loongson2e and loongson2f entries. * doc/c-mips.texi: Document -march=loongson{2e,2f} options. gas/testsuite/ * gas/mips/mips.exp: Add loongson-2e and -2f tests. * gas/mips/loongson-2e.d: New. * gas/mips/loongson-2e.s: New. * gas/mips/loongson-2f.d: New. * gas/mips/loongson-2f.s: New. include/elf/ * mips.h (E_MIPS_MACH_LS2E): New. (E_MIPS_MACH_LS2F): New. include/opcode/ * mips.h (INSN_LOONGSON_2E): New. (INSN_LOONGSON_2F): New. (CPU_LOONGSON_2E): New. (CPU_LOONGSON_2F): New. (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags. opcodes/ * mips-dis.c (mips_arch_choices): Add Loongson-2E and -2F entries. * mips-opc.c (IL2E): New. (IL2F): New. (mips_builtin_opcodes): Add Loongson-2E and -2F instructions. Allow movz and movn for Loongson-2E and -2F. Add movnz entry. Move coprocessor encodings to the end of the table. Allow certain MIPS V .ps instructions on the Loongson-2E and -2F.	19 years ago
Mark Shinwell	569502941a	include/opcode/ * mips.h (INSN_ISA): Redefine certain values as an enumeration. Update comments. (mips_isa_table): New. (ISA_MIPS): Redefine to match enumeration. (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA* values. opcodes/ * mips-opc.c (I3_32, I3_33, I4_32, I4_33, I5_33): New. (mips_builtin_opcodes): Use these new I* values.	19 years ago
Ben Elliston	c3d65c1ced	binutils/ * doc/binutils.texi (objdump): Document -Mppcps. gas/ * config/tc-ppc.c (parse_cpu): Handle "750cl". (pre_defined_registers): Add "gqr0" to "gqr7", "gqr.0" to "gqr.7". (md_show_usage): Document -m750cl. (md_assemble): Handle two delimiters in succession (eg. `),'). * doc/c-ppc.texi (PowerPC-Opts): Document -m750cl. * testsuite/gas/ppc/ppc.exp: Run ppc70ps dump tests. * testsuite/gas/ppc/ppc750ps.s: New file. * testsuite/gas/ppc/ppc750ps.d: Likewise. include/opcode/ * ppc.h (PPC_OPCODE_PPCPS): New. opcodes/ * ppc-opc.c (PSW, PSWM, PSQ, PSQM, PSD, MTMSRD_L): New. (XOPS, XOPS_MASK, XW, XW_MASK): Likewise. (PPCPS): Likewise. (powerpc_opcodes): Add all pair singles instructions. * ppc-dis.c (powerpc_dialect): Handle "ppcps". (print_ppc_disassembler_options): Document -Mppcps.	19 years ago
H.J. Lu	0fdaa00544	Correct ChangeLog entries.	19 years ago
Nathan Sidwell	afa2158f09	gas/testsuite/ * gas/m68k/mcf-coproc.d: New. * gas/m68k/mcf-coproc.s: New. * gas/m68k/all.exp: Add it. gas/ * config/tc-m68k.c (m68k_ip): Add j & K operand types. (install_operand): Add E encoding. (md_begin): Check and skip initial '.' arg character. (get_num): Add 0..511 case. include/ * opcode/m68k.h: Document j K & E. opcodes/ * m68k-dis.c (fetch_arg): Add E. Replace length switch with direct masking. (print_ins_arg): Add j & K operand types. (match_insn_m68k): Check and skip initial '.' arg character. (m68k_scan_mask): Likewise. * m68k-opc.c (m68k_opcodes): Add coprocessor instructions.	19 years ago
Nick Clifton	3d3d428f04	New port: National Semiconductor's CR16	19 years ago
Alan Modra	3896c469d2	gas/ PR 4448 * config/tc-ppc.c (ppc_insert_operand): Don't increase min for PPC_OPERAND_PLUS1. include/opcode/ * ppc.h (PPC_OPERAND_PLUS1): Update comment.	20 years ago
Nathan Sidwell	9a2e615a9f	gas/testsuite/ * gas/m68k/br-isaa.s: New. * gas/m68k/br-isaa.d: New. * gas/m68k/br-isab.s: New. * gas/m68k/br-isab.d: New. * gas/m68k/br-isac.s: New. * gas/m68k/br-isac.d: New. * gas/m68k/all.exp: Adjust. gas/ * config/tc-m68k.c (mcf54455_ctrl): New. (HAVE_LONG_DISP, HAVE_LONG_CALL, HAVE_LONG_COND): New. (m68k_archs): Add isac. (m68k_cpus): Add 54455 family. (m68k_ip): Split Bg into Bb, Bs, Bg. (m68k_elf_final_processing): Add ISA_C. * doc/c-m68k.texi (M680x0 Options): Add isac. include/opcode/ * m68k.h (mcfisa_c): New. (mcfusp, mcf_mask): Adjust. bfd/ * archures.c (bfd_mach_mcf_isa_c, bfd_mach_mcf_isa_c_mac, bfd_mach_mcf_isa_c_emac): New. * elf32-m68k.c (ISAC_PLT_ENTRY_SIZE, elf_isac_plt0_entry, elf_isac_plt_entry, elf_isac_plt_info): New. (elf32_m68k_object_p): Add ISA_C. (elf32_m68k_print_private_bfd_data): Print ISA_C. (elf32_m68k_get_plt_info): Detect ISA_C. * cpu-m68k.c (arch_info): Add ISAC. (m68k_arch_features): Likewise, (bfd_m68k_compatible): ISAs B & C are not compatible. opcodes/ * m68k-opc.c: Mark mcfisa_c instructions.	20 years ago
Alan Modra	b84bf58af1	include/opcode/ * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". (num_powerpc_operands): Declare. (PPC_OPERAND_SIGNED et al): Redefine as hex. (PPC_OPERAND_PLUS1): Define. opcodes/ * ppc-dis.c (print_insn_powerpc): Adjust for struct powerpc_operand change. * ppc-opc.c (powerpc_operands): Replace bit count with bit mask in all entries. Add PPC_OPERAND_SIGNED to DE entry. Remove references to following deleted functions. (insert_bd, extract_bd, insert_dq, extract_dq): Delete. (insert_ds, extract_ds, insert_de, extract_de): Delete. (insert_des, extract_des, insert_li, extract_li): Delete. (insert_nb, insert_rsq, insert_rtq, insert_ev2, extract_ev2): Delete. (insert_ev4, extract_ev4, insert_ev8, extract_ev8): Delete. (num_powerpc_operands): New constant. (XSPRG_MASK): Remove entire SPRG field. (powerpc_opcodes <bcctre, bcctrel>): Use XLBB_MASK not XLYBB_MASK. gas/ * messages.c (as_internal_value_out_of_range): Extend to report errors for values with invalid low bits set. * config/tc-ppc.c (ppc_setup_opcodes): Check powerpc_operands bitm fields. Check that operands and opcode fields are disjoint. (ppc_insert_operand): Check operands using mask rather than bit count. Check low bits too. Handle PPC_OPERAND_PLUS1. Adjust insertion code. (md_apply_fix): Adjust for struct powerpc_operand change.	20 years ago
H.J. Lu	831480e942	Fix year.	20 years ago
H.J. Lu	161a04f630	gas/ 2003-03-21 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c: Replace REX_MODE64, REX_EXTX, REX_EXTY and REX_EXTZ with REX_W, REX_R, REX_X and REX_B respectively. include/opcode/ 2003-03-21 H.J. Lu <hongjiu.lu@intel.com> * i386.h (REX_MODE64): Renamed to ... (REX_W): This. (REX_EXTX): Renamed to ... (REX_R): This. (REX_EXTY): Renamed to ... (REX_X): This. (REX_EXTZ): Renamed to ... (REX_B): This. opcodes/ 2003-03-21 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (REX_MODE64): Remove definition. (REX_EXTX): Likewise. (REX_EXTY): Likewise. (REX_EXTZ): Likewise. (USED_REX): Use REX_OPCODE instead of 0x40. Replace REX_MODE64, REX_EXTX, REX_EXTY and REX_EXTZ with REX_W, REX_R, REX_X and REX_B respectively.	20 years ago
H.J. Lu	0b1cf022c8	gas/ 2007-03-15 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am: Run "make dep-am". * Makefile.in: Regenerated. * config/tc-i386.c: Include "opcodes/i386-opc.h" instead of "opcode/i386.h". (md_begin): Check reg_name != NULL for the last entry in i386_regtab. * config/tc-i386.h: Move many entries to opcode/i386.h and opcodes/i386-opc.h. * configure.in (need_opcodes): Set true for i386. * configure: Regenerated. include/opcode/ 2007-03-15 H.J. Lu <hongjiu.lu@intel.com> * i386.h: Add entries from config/tc-i386.h and move tables to opcodes/i386-opc.h. opcodes/ 2007-03-15 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am (CFILES): Add i386-opc.c. (ALL_MACHINES): Add i386-opc.lo. Run "make dep-am". * Makefile.in: Regenerated. * configure.in: Add i386-opc.lo for bfd_i386_arch. * configure: Regenerated. * i386-dis.c: Include "opcode/i386.h". (MAXLEN): Renamed to MAX_MNEM_SIZE. Remove definition. (FWAIT_OPCODE): Remove definition. (UNIXWARE_COMPAT): Renamed to SYSV386_COMPAT. Remove definition. (MAX_OPERANDS): Remove definition. * i386-opc.c: New file. * i386-opc.h: Likewise.	20 years ago
H.J. Lu	d796c0adf2	2007-03-13 H.J. Lu <hongjiu.lu@intel.com> * i386.h (FloatDR): Removed. (i386_optab): Use FloatD and FloatD\|FloatR instead of FloatDR.	20 years ago
Martin Schwidefsky	b5639b37c5	2007-03-06 Andreas Krebbel <krebbel1@de.ibm.com> * opcodes/s390-opc.c (INSTR_RRE_FR, INSTR_RRF_F0FF2, INSTR_RRF_F0FR, INSTR_RRF_UUFF, INSTR_RRF_0UFF, INSTR_RRF_FFFU, INSTR_RRR_F0FF): New instruction formats added. (MASK_RRE_FR, MASK_RRF_F0FF2, MASK_RRF_F0FR, MASK_RRF_UUFF, MASK_RRF_0UFF, MASK_RRF_FFFU, MASK_RRR_F0FF): New instruction format masks added. * opcodes/s390-opc.txt (lpdfr - tgxt): Decimal floating point instructions added. * opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added. (main): z9-ec cpu type option added. * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added. 2007-03-06 Andreas Krebbel <krebbel1@de.ibm.com> * config/tc-s390.c (md_parse_option): z9-ec option added. 2007-03-06 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z9-ec.d: New file. * gas/s390/zarch-z9-ec.s: New file. * gas/s390/s390.exp: Run the z9-ec testcases.	20 years ago
Alan Modra	30ac7323f6	* spu-insns.h: Add soma double-float insns.	20 years ago
Thiemo Seufer	8b082fb134	[ gas/ChangeLog ] * config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2, ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support. (macro_build): Add case '2'. (macro): Expand M_BALIGN to nop, packrl.ph or balign. (validate_mips_insn): Add support for balign instruction. (mips_ip): Handle DSP R2 instructions. Support balign instruction. (OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE, md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2 command line options. (s_mipsset): Add support for .set dspr2 and .set nodspr2 directives. (md_show_usage): Add -mdspr2 and -mno-dspr2 help output. * doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2, .set dspr2, .set nodspr2. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for DSP R2. * gas/mips/mips.exp: Run new test. [ include/opcode/Changelog ] * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. (INSN_DSPR2): Add flag for DSP R2 instructions. (M_BALIGN): New macro. [ opcodes/ChangeLog ] * mips-dis.c (mips_arch_choices): Add DSP R2 support. (print_insn_args): Add support for balign instruction. * mips-opc.c (D33): New shortcut for DSP R2 instructions. (mips_builtin_opcodes): Add DSP R2 instructions. [ sim/mips/ChangeLog ] * Makefile.in (IGEN_INCLUDE): Add dsp2.igen. * configure.ac (mips-sde-elf, mipsisa32r2--, mipsisa64r2--): Add dsp2 to sim_igen_machine. * configure: Regenerate. * dsp.igen (do_ph_op): Add MUL support when op = 2. (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph. (mulq_rs.ph): Use do_ph_mulq. (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen. * mips.igen: Add dsp2 model and include dsp2.igen. (MFHI, MFLO, MTHI, MTLO): Extend these instructions for for mips32r2, mips64r2, dsp. (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions for mips32r2, mips64r2, dsp2. * dsp2.igen: New file for MIPS DSP REV 2 ASE. [ sim/testsuite/sim/mips/ChangeLog ] * basic.exp: Run the dsp2 test. * utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro. * mips32-dsp2.s: New test.	20 years ago
Alan Modra	4eed87de48	gas/ * config/tc-i386.h (Seg2ShortForm, Seg3ShortForm): Delete. * config/tc-i386.c: Wrap overly long lines, whitespace fixes. (process_operands): Move old Seg2ShortForm and Seg3ShortForm code, and test for these insns using a combination of opcode_modifier and operand_types. include/opcode/ * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm and Seg3ShortFrom with Shortform.	20 years ago
H.J. Lu	fda592e836	gas/testsuite/ 2007-02-11 H.J. Lu <hongjiu.lu@intel.com> PR gas/4027 * gas/i386/opcode.s: Add more tests for "test". * i386/opcode-intel.d: Updated. * gas/i386/opcode-suffix.d: Likewise. * gas/i386/opcode.d: Likewise. include/opcode/ 2007-02-11 H.J. Lu <hongjiu.lu@intel.com> PR gas/4027 * i386.h (i386_optab): Put the real "test" before the pseudo one.	20 years ago
Kazu Hirata	3bdcfdf41f	bfd/ * archures.c (bfd_mach_cpu32_fido): Rename to bfd_mach_fido. * bfd-in2.h: Regenerate. * cpu-m68k.c (arch_info_struct): Use bfd_mach_fido instead of bfd_mach_cpu32_fido. (m68k_arch_features): Use fido_a instead of cpu32. (bfd_m68k_compatible): Reject the combination of Fido and ColdFire. Accept the combination of CPU32 and Fido with a warning. * elf32-m68k.c (elf32_m68k_object_p, elf32_m68k_merge_private_bfd_data, elf32_m68k_print_private_bfd_data): Treat Fido as an architecture by itself. binutils/ * readelf.c (get_machine_flags): Treat Fido as an architecture by itself. gas/ * config/tc-m68k.c (m68k_archs, m68k_cpus): Treat Fido as an architecture by itself. (m68k_ip): Don't issue a warning for tbl instructions on fido. (m68k_elf_final_processing): Treat Fido as an architecture by itself. include/elf/ * m68k.h (EF_M68K_FIDO): New. (EF_M68K_ARCH_MASK): OR EF_M68K_FIDO. (EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): Remove. include/opcode/ * m68k.h (m68010up): OR fido_a. opcodes/ * m68k-opc.c (m68k_opcodes): Replace cpu32 with cpu32 \| fido_a except on tbl instructions.	20 years ago
Kazu Hirata	9840d27e81	bfd/ * archures.c (bfd_mach_cpu32_fido): New. (bfd_mach_mcf_isa_a_nodiv, bfd_mach_mcf_isa_a, bfd_mach_mcf_isa_a_mac, bfd_mach_mcf_isa_a_emac, bfd_mach_mcf_isa_aplus, bfd_mach_mcf_isa_aplus_mac, bfd_mach_mcf_isa_aplus_emac, bfd_mach_mcf_isa_b_nousp, bfd_mach_mcf_isa_b_nousp_mac, bfd_mach_mcf_isa_b_nousp_emac, bfd_mach_mcf_isa_b, bfd_mach_mcf_isa_b_mac, bfd_mach_mcf_isa_b_emac, bfd_mach_mcf_isa_b_float, bfd_mach_mcf_isa_b_float_mac, bfd_mach_mcf_isa_b_float_emac): Increment the defined values. * bfd-in2.h: Regenerate. * cpu-m68k.c (arch_info_struct): Add en entry for bfd_mach_cpu32_fido. * elf32-m68k.c (elf32_m68k_object_p): Handle EF_M68K_CPU32_FIDO_A. (elf32_m68k_merge_private_bfd_data): Use EF_M68K_CPU32_MASK. (elf32_m68k_print_private_bfd_data): Handle EF_M68K_CPU32_FIDO_A. binutils/ * readelf.c (get_machine_flags): Handle EF_M68K_CPU32_FIDO_A. gas/ * config/tc-m68k.c (cpu_of_arch): Add fido. (m68k_archs, m68k_cpu): Add entries for fido. (m68k_elf_final_processing): Handle EF_M68K_CPU32_FIDO_A. include/elf/ * m68k.h (EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): New. include/opcode/ * m68k.h (fido_a): New.	20 years ago
Kazu Hirata	c629cdacff	* m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined values.	20 years ago
H.J. Lu	faaf835901	Remove entries checked in by accident.	20 years ago
H.J. Lu	b7d9ef3748	gas/ 2006-11-08 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.h (CpuPNI): Removed. (CpuUnknownFlags): Replace CpuPNI with CpuSSE3. * config/tc-i386.c (md_assemble): Likewise. include/opcode/ 2006-11-08 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.	20 years ago
Nick Clifton	b138abaa40	* tc-score.c (data_op2): Check invalid operands. (my_get_expression): Const operand of some instructions can not be symbol in assembly. (get_insn_class_from_type): Handle instruction type Insn_internal. (do_macro_ldst_label): Modify inst.type. (Insn_PIC): Delete. * score-inst.h (enum score_insn_type): Add Insn_internal. * tc-score.c (data_op2): The immediate value in lw is 15 bit signed. * score-dis.c (print_insn): Correct the error code to print correct PCE instruction disassembly.	20 years ago
Alan Modra	e9f5312993	New Cell SPU port.	20 years ago
Alan Modra	ede602d7c8	Add powerpc cell support.	20 years ago
Michael Meissner	7918206c55	Fix AMDFAM10 POPCNT instruction	20 years ago

1 2 3 4 5 ...

415 Commits (5726889422ca1dd271be75f64a0f152c04bc1476)