binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Alan Modra	f757c5cae9	PR21739, Inconsistent diagnostics PR 21739 cpu/ * mep.opc (parse_lo16, parse_unsigned7): Mark %function message as no-c-format. opcodes/ * mep-asm.c: Regenerate.	2 years ago
Mike Frysinger	8fed036bef	sim: frv: fix -Wincompatible-function-pointer-types warnings [PR sim/29752] Some compilers warn in the frv code: sem.c:24343:41: error: incompatible function pointer types passing 'void (SIM_CPU , UINT, UDI)' (aka 'void (struct _sim_cpu , unsigned int, unsigned long)') to parameter of type 'void ()(SIM_CPU , UINT, DI)' (aka 'void ()(struct _sim_cpu , unsigned int, long)') [-Wincompatible-function-pointer-types] This is due to frvbf_h_acc40U_set using UDI for setting the new value, but using the common sim_queue_fn_di_write API which uses DI. The same size, but different sign. We could change frvbf_h_acc40U_set to take a DI without changing behavior in practice: the UDI is already passed via the queue function which accepts a DI, and frvbf_h_acc40U_set already casts the input to UDI before running any operations on it. However, these files are all generated, so manual changes here would be reverted. Seems like we can only change the register type for all APIs in the cpu definition. This builds cleanly, and passes sim unittests. Not sure if it's 100% the answer, but seems to be the best we have currently. Bug: https://sourceware.org/PR29752	3 years ago
Nick Clifton	299b91cd85	Add markers for 2.42 branch	3 years ago
Mike Frysinger	199b67ca04	sim: cris: change temp var name slightly to avoid shadowing Rename the temp var to avoid shadowing another one: .../sim/cris/semcrisv10f-switch.c:11032:22: error: declaration of ‘tmp_tmpb’ shadows a previous local [-Werror=shadow=compatible-local] 11032 \| tmp_tmpb = ({ SI tmp_tmpb; \| ^~~~~~~~ .../sim/cris/semcrisv10f-switch.c:11031:24: note: shadowed declaration is here 11031 \| tmp_tmpres = ({ SI tmp_tmpb; \| ^~~~~~~~	3 years ago
Mike Frysinger	012c1f072f	sim: cris: add error fallbacks when decoding condition & swap codes The condition & swap code decoder only checks known bits and sets based on that. If the variable is out of range, it ends up returning uninitialized data. Turn that case into a hard error. This fixes build warnings like: sim/cris/semcrisv10f-switch.c:13115:11: error: variable 'tmp_condres' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized]	3 years ago
Mike Frysinger	f793be444c	sim: frv: fix cmpb uninitialized variable usage This code sets up the cc variable based on the comparison of other registers, but it does so incrementally with bit operations, and it never initializes the cc variable. Initialize it to 0 which the cmpba insn is already doing.	3 years ago
Mike Frysinger	fa99355b56	cpu: or1k: drop unused l.swa flag The "flag" argument isn't set/used in this insn, so drop it. This fixes an unused variable warning in the generated sim.	3 years ago
Mike Frysinger	e9026cfbcf	cpu: cris: drop some unused vars These fix unused variable warnings in the generated sim.	3 years ago
Alan Modra	e7ad52cde6	sim --enable-cgen-maint I had reason yesterday to want to regenerate configury files which I do with --enable-maintainer-mode, and added --enable-cgen-maint accidentally. The first problem I hit is that sim looks for cgen in a different directory by default than opcodes, and I had my source layout set up for opcodes rather than sim. Fix that by making both use ../cgen first, then ../../cgen relative to sim/ and opcodes/. The next problem was that various sim local.mk files expected generated sources in the build dir rather than the source dir. Fix that by adding $(srcdir) to paths. Finally, the generated iq2000 files had a compile error, fixed by the cpu/iq2000.cpu patch. cpu/ * iq2000.cpu (syscall): Add pc arg. opcodes/ * configure.ac (cgendir): Default to ../../cgen, but use ../cgen if found there. * configure: Regenerate. sim/m4/ * sim_ac_option_cgen_maint.m4 (cgendir): Look in ../cgen too. sim/ * cris/local.mk: Add $(srcdir) to paths for regenerated source. * frv/local.mk: Likewise. * iq2000/local.mk: Likewise. * lm32/local.mk: Likewise. * m32r/local.mk: Likewise. * or1k/local.mk: Likewise. * Makefile.in: Regenerate. * configure: Regenerate.	3 years ago
Jose E. Marchesi	d218e7fedc	DesCGENization of the BPF binutils port CGEN is cool, but the BPF architecture is simply too bizarre for it. The weird way of BPF to handle endianness in instruction encoding, the weird C-like alternative assembly syntax, the weird abuse of multi-byte (or infra-byte) instruction fields as opcodes, the unusual presence of opcodes beyond the first 32-bits of some instructions, are all examples of what makes it a PITA to continue using CGEN for this port. The bpf.cpu file is becoming so complex and so nested with p-macros that it is very difficult to read, and quite challenging to update. Also, every time we are forced to change something in CGEN to accommodate BPF requirements (which is often) we have to do extensive testing to make sure we do not break any other target using CGEN. This is getting un-maintenable. So I have decided to bite the bullet and revamp/rewrite the port so it no longer uses CGEN. Overall, this involved: * To remove the cpu/bpf.{cpu,opc} descriptions. * To remove the CGEN generated files. * To replace the CGEN generated opcodes table with a new hand-written opcodes table for BPF. * To replace the CGEN generated disassembler wih a new disassembler that uses the new opcodes. * To replace the CGEN generated assembler with a new assembler that uses the new opcodes. * To replace the CGEN generated simulator with a new simulator that uses the new opcodes. [This is pushed in GDB in another patch.] * To adapt the build systems to the new situation. Additionally, this patch introduces some extensions and improvements: * A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These relocations are used for section-relative 16-bit offsets used in load/store instructions. * The disassembler now has support for the "pseudo-c" assembly syntax of BPF. What dialect to use when disassembling is controlled by a command line option. * The disassembler now has support for dumping instruction immediates in either octal, hexadecimal or decimal. The used output base is controlled by a new command-line option. * The GAS BPF test suite has been re-structured and expanded in order to test the disassembler pseudoc syntax support. Minor bugs have been also fixed there. The assembler generic tests that were disabled for bpf-- targets due to the previous implementation of pseudoc syntax are now re-enabled. Additional tests have been added to test the new features of the assembler. .dump files are no longer used. * The linker BPF test suite has been adapted to the command line options used by the new disassembler. The result is very satisfactory. This patchs adds 3448 lines of code and removes 10542 lines of code. Tested in: * Target bpf-unknown-none with 64-bit little-endian host and 32-bit little-endian host. * Target x86-64-linux-gnu with --enable-targets=all Note that I have not tested in a big-endian host yet. I will do so once this lands upstream so I can use the GCC compiler farm. I have not included ChangeLog entries in this patch: these would be massive and not very useful, considering this is pretty much a rewrite of the port. I beg the indulgence of the global maintainers.	3 years ago
Nick Clifton	d501d38488	Add markers for the 2.41 branch	3 years ago
Alan Modra	3e8b13bf77	cpu/mem.opc whitespace tidy cpu/ * mep.opc: Whitespace and formatting. opcodes/ * mep-asm.c: Regenerate. * mep-dis.c: Regenerate.	3 years ago
Nick Clifton	71f646f2b3	Fix an illegal memory access when disassembling a corrupt MeP file. PR 30231 * mep.opc (mep_print_insn): Check for an out of range index.	3 years ago
Guillermo E. Martinez	7f6ebecd56	bpf: fix error conversion from long unsigned int to unsigned int [-Werror=overflow] Regenerating BPF target using the maintainer mode emits: .../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow] 57 \| 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } The use of a narrow size to handle the mask CGEN in instruction format is causing this error. Additionally eBPF `call' instructions constructed by expressions using symbols (BPF_PSEUDO_CALL) emits annotations in `src' field of the instruction, used to identify BPF target endianness. cpu/ * bpf.cpu (define-call-insn): Remove `src' field from instruction mask. include/ opcode/cge.h (CGEN_IFMT): Adjust mask bit width. opcodes/ bpf-opc.c: Regenerate.	4 years ago
Nick Clifton	a72b07181d	Add markers for 2.40 branch	4 years ago
Nick Clifton	0bd0932314	Add markers for 2.39 branch	4 years ago
Jan Beulich	ddd7bf3e28	drop XC16x bits Commit `04f096fb9e` ("Move the xc16x target to the obsolete list") moved the architecture from the "obsolete but still available" to the "obsolete / support removed" list in config.bfd, making the architecture impossible to enable (except maybe via "enable everything" options"). Note that I didn't touch /po/.po{,t} on the assumption that these would be updated by some (half)automatic means.	4 years ago
Alan Modra	0dfdb5234a	opcodes cgen: remove use of PTR Note that opcodes is regenerated with cgen commit d1dd5fcc38e reverted, due to failure of bpf to compile with that patch applied. .../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow] 57 \| 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } plus other similar errors. cpu/ * mep.opc (print_tpreg, print_spreg): Delete unnecessary forward declarations. Replace PTR with void . mt.opc (print_dollarhex, print_pcrel): Delete forward decls. opcodes/ * bpf-desc.c, * bpf-dis.c, * cris-desc.c, * epiphany-desc.c, * epiphany-dis.c, * fr30-desc.c, * fr30-dis.c, * frv-desc.c, * frv-dis.c, * ip2k-desc.c, * ip2k-dis.c, * iq2000-desc.c, * iq2000-dis.c, * lm32-desc.c, * lm32-dis.c, * m32c-desc.c, * m32c-dis.c, * m32r-desc.c, * m32r-dis.c, * mep-desc.c, * mep-dis.c, * mt-desc.c, * mt-dis.c, * or1k-desc.c, * or1k-dis.c, * xc16x-desc.c, * xc16x-dis.c, * xstormy16-desc.c, * xstormy16-dis.c: Regenerate.	4 years ago
Thomas Hebb	16089f320a	opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblers Currently, the get_disassembler() implementations for riscv, csky, and rl78--and mep_print_insn() for mep--access ELF variants of union fields without first checking that the bfd actually represents an ELF. This causes undefined behavior and crashes when disassembling non-ELF files (the "binary" BFD, for example). Fix that.	4 years ago
Nick Clifton	a74e1cb344	Add markers for 2.38 branch	5 years ago
Alan Modra	4dcdbbd1bc	Re: opcodes: constify & local meps macros Commit `f375d32b35` changed a generated file. Edit the source instead. * mep.opc (macros): Make static and const. (lookup_macro): Return and use const pointer. (expand_macro): Make mac param const. (expand_string): Make pmacro const.	5 years ago
Nick Clifton	514192487e	Add markers for 2.37 branch	5 years ago
Stafford Horne	0b3e14c902	or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha() The gotha() relocation mnemonic will be outputted by OpenRISC GCC when using the -mcmodel=large option. This relocation is used along with got() to generate 32-bit GOT offsets. This increases the previous GOT offset limit from the previous 16-bit (64K) limit. This is needed on large binaries where the GOT grows larger than 64k. bfd/ChangeLog: PR 21464 * bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation. * elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise. (or1k_final_link_relocate, or1k_elf_relocate_section, or1k_elf_check_relocs): Likewise. * libbfd.h (bfd_reloc_code_real_names): Likewise. * reloc.c: Likewise. cpu/ChangeLog: PR 21464 * or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic for gotha() relocation. include/ChangeLog: PR 21464 * elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number. opcodes/ChangeLog: PR 21464 * or1k-asm.c: Regenerate. gas/ChangeLog: PR 21464 * testsuite/gas/or1k/reloc-1.s: Add test for new relocation. * testsuite/gas/or1k/reloc-1.d: Add test result for new relocation. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> fixup reloc, add tests	5 years ago
Alan Modra	78933a4ad9	Use bool in opcodes cpu/ * frv.opc: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout. opcodes/ * sysdep.h (POISON_BFD_BOOLEAN): Define. * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h, * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h, * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c, * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c, * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c, * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c, * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c, * microblaze-dis.h, * micromips-opc.c, * mips-dis.c, * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c, * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c, * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c, * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c, * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout.	5 years ago
Alan Modra	3d7d6c1b50	opcodes int vs bfd_boolean fixes cpu/ * frv.opc (frv_is_branch_major, frv_is_float_major), (frv_is_media_major, frv_is_branch_insn, frv_is_float_insn), (frv_is_media_insn, spr_valid): Correct prototypes. include/ * opcode/aarch64.h (aarch64_opcode_encode): Correct prototype. opcodes/ * arc-dis.c (extract_operand_value): Correct NULL cast. * frv-opc.h: Regenerate.	5 years ago
Nick Clifton	055bc77a80	Add Changelog entries and NEWS entries for 2.36 branch	6 years ago
Samanta Navarro	0cc79db2b6	Fix spelling mistakes	6 years ago
David Faust	6e25f88828	bpf: xBPF SDIV, SMOD instructions Add gas and opcodes support for two xBPF-exclusive ALU operations: SDIV (signed division) and SMOD (signed modulo), and add tests for them in gas. cpu/ * bpf.cpu (insn-op-code-alu): Add SDIV and SMOD. (define-alu-insn-bin, daib): Take ISAs as an argument. (define-alu-instructions): Update calls to daib pmacro with ISAs; add sdiv and smod. gas/ * testsuite/gas/bpf/alu-xbpf.d: New file. * testsuite/gas/bpf/alu-xbpf.s: Likewise. * testsuite/gas/bpf/alu32-xbpf.d: Likewise. * testsuite/gas/bpf/alu32-xbpf.d: Likewise. * testuiste/gas/bpf/bpf.exp: Run new tests. opcodes/ * bpf-desc.c: Regenerate. * bpf-desc.h: Likewise. * bpf-opc.c: Likewise. * bpf-opc.h: Likewise.	6 years ago
David Faust	3ad6c19423	bpf: simulator: correct div, mod insn semantics The div and mod eBPF instructions are unsigned, but the semantic specification for the simulator incorrectly used signed operators. Correct them to unsigned versions, and correct the ALU tests in the simulator (which incorrectly assumed signed semantics). Tested in bpf-unknown-none. cpu/ChangeLog: 2020-09-08 David Faust <david.faust@oracle.com> * bpf.cpu (define-alu-instructions): Correct semantic operators for div, mod to unsigned versions. sim/ChangeLog: 2020-09-08 David Faust <david.faust@oracle.com> * bpf/sem-be.c: Regenerate. * bpf/sem-le.c: Likewise. sim/testsuite/ChangeLog: 2020-09-08 David Faust <david.faust@oracle.com> * sim/bpf/alu.s: Correct div and mod tests. * sim/bpf/alu32.s: Likewise.	6 years ago
Alan Modra	8dbe96f070	mep: ubsan: mep-ibld.c:1635,1645,1652 left shift of negative value cpu/ * mep-core.cpu (f-8s8a2, f-12s4a2, f-17s16a2): Multiply signed value by two rather than shifting left. (f-24s5a2n): Similarly multiply signed f-24s5a2n-hi to extract. opcodes/ * mep-ibld.c: Regenerate.	6 years ago
David Faust	4449c81a85	bpf: add xBPF ISA This patch adds support for xBPF, another ISA targetting the BPF virtual architecture. For now, the primary difference between eBPF and xBPF is that xBPF supports indirect calls through the 'call %reg' form of the call instruction. bfd/ * archures.c (bfd_mach_xbpf): Define. * bfd-in2.h: Regenerate. * cpu-bpf.c (bfd_xbpf_arch) New. (bfd_bpf_arch) Update next in list field to point to xbpf arch. cpu/ * bpf.cpu (arch bpf): Add xbpf mach and isas. (define-xbpf-isa) New pmacro. (all-isas) Add xbpfle,xbpfbe. (endian-isas): New pmacro. (mach xbpf): New. (model xbpf-def): Likewise. (h-gpr): Add xbpf mach. (f-dstle, f-srcle, dstle, srcle): Add xbpfle isa. (f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa. (define-alu-insn-un): Use new endian-isas pmacro. (define-alu-insn-bin, define-alu-insn-mov): Likewise. (define-endian-insn, define-lddw): Likewise. (dlind, dxli, dxsi, dsti): Likewise. (define-cond-jump-insn, define-call-insn): Likewise. (define-atomic-insns): Likewise. gas/ * config/tc-bpf.c: Add option -mxbpf to select xbpf isa. * testsuite/gas/bpf/indcall-1.d: New file. * testsuite/gas/bpf/indcall-1.s: Likewise. * testsuite/gas/bpf/indcall-bad-1.l: Likewise. * testsuite/gas/bpf/indcall-bad-1.s: Likewise. * testsuite/gas/bpf/bpf.exp: Run new tests. opcodes/ * bpf-desc.c: Regenerate. * bpf-desc.h: Likewise. * bpf-opc.c: Likewise. * bpf-opc.h: Likewise. * disassemble.c (disassemble_init_for_target): Set bits for xBPF ISA when appropriate.	6 years ago
Nick Clifton	b115b9fd3c	Add markers for binutils 2.35 branch	6 years ago
David Faust	d73be61168	cpu: fix offset16 type, update c-calls in bpf.cpu Correct the type of the offset16 field to HI, and simplify memory accesses which use it. Also update c-calls in semantics for a few instructions. cpu/ChangeLog: 2020-06-25 David Faust <david.faust@oracle.com> * bpf.cpu (f-offset16): Change type from INT to HI. (dxli): Simplify memory access. (dxsi): Likewise. (define-endian-insn): Update c-call in semantics. (dlabs) Likewise. (dlind) Likewise.	6 years ago
Jose E. Marchesi	d8740be159	cpu,gas,opcodes: remove no longer needed workaround from the BPF port cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64. * bpf.opc (bpf_print_insn): Do not set endian_code here. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to bpf_cgen_cpu_open. (md_assemble): Remove no longer needed hack. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * disassemble.c (disassemble_init_for_target): Set endian_code for bpf targets. * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. * bpf-dis.c: Likewise.	6 years ago
Jose E. Marchesi	e9bffec9af	opcodes: discriminate endianness and insn-endianness in CGEN ports The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.	6 years ago
Jose E. Marchesi	78c1c35437	cpu,opcodes: add instruction semantics to bpf.cpu and minor fixes This patch adds semantic RTL descriptions to the eBPF instructions defined in cpu/bpf.cpu. It also contains a couple of minor improvements. Tested in bpf-unknown-none targets. No regressions. cpu/ChangeLog: 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com> David Faust <david.faust@oracle.com> * bpf.cpu (define-alu-insn-un): Add definitions of semantics. (define-alu-insn-mov): Likewise. (daib): Likewise. (define-alu-instructions): Likewise. (define-endian-insn): Likewise. (define-lddw): Likewise. (dlabs): Likewise. (dlind): Likewise. (dxli): Likewise. (dxsi): Likewise. (dsti): Likewise. (define-ldstx-insns): Likewise. (define-st-insns): Likewise. (define-cond-jump-insn): Likewise. (dcji): Likewise. (define-condjump-insns): Likewise. (define-call-insn): Likewise. (ja): Likewise. ("exit"): Likewise. (define-atomic-insns): Likewise. (sem-exchange-and-add): New macro. * bpf.cpu ("brkpt"): New instruction. (bpfbf): Set word-bitsize to 32 and insn-endian big. (h-gpr): Prefer r0 to `a' and r6 to `ctx'. (h-pc): Expand definition. * bpf.opc (bpf_print_insn): Set endian_code to BIG. opcodes/ChangeLog: 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com> David Faust <david.faust@oracle.com> * bpf-desc.c: Regenerate. * bpf-opc.h: Likewise. * bpf-opc.c: Likewise. * bpf-dis.c: Likewise.	6 years ago
Alan Modra	d96bf37ba8	Replace "if (x) free (x)" with "free (x)", opcodes cpu/ * mep.opc (mep_cgen_expand_macros_and_parse_operand): Replace "if (x) free (x)" with "free (x)". opcodes/ * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout. * sparc-dis.c: Likewise. * tic4x-dis.c: Likewise. * xtensa-dis.c: Likewise. * bpf-desc.c: Regenerate. * epiphany-desc.c: Regenerate. * fr30-desc.c: Regenerate. * frv-desc.c: Regenerate. * ip2k-desc.c: Regenerate. * iq2000-desc.c: Regenerate. * lm32-desc.c: Regenerate. * m32c-desc.c: Regenerate. * m32r-desc.c: Regenerate. * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mt-desc.c: Regenerate. * or1k-desc.c: Regenerate. * xc16x-desc.c: Regenerate. * xstormy16-desc.c: Regenerate.	6 years ago
Stafford Horne	ae440402f5	or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts Reported by Rich Felker when building on 32-bit hosts. Backwards jump negative offsets were not calculated correctly due to improper 32-bit to 64-bit zero-extension. The 64-bit fields are present because we are mixing 32-bit and 64-bit architectures in our cpu descriptions. Removing 64-bit fixes the issue. We don't use 64-bit, there is an architecture spec for 64-bit but no implementations or simulators. My thought is if we need them in the future we should do the proper work to support both 32-bit and 64-bit implementations co-existing then. cpu/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> PR 25184 * or1k.cpu (arch or1k): Remove or64 and or64nd machs. (ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros. (cpu or1k64bf, mach or64, mach or64nd): Remove definitions. * or1kcommon.cpu (h-fdr): Remove hardware. * or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions. (float-regreg-insn): Remove lf- mnemonic -d instruction pattern. (float-setflag-insn-base): Remove lf-sf mnemonic -d pattern. (float-cust-insn): Remove "lf-cust" cust-num "-d" pattern. (lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.	6 years ago
David Faust	c54a9b5669	cpu,gas,opcodes: support for eBPF JMP32 instruction class Add support for the JMP32 class of eBPF instructions. cpu/ChangeLog * bpf.cpu (define-cond-jump-insn): Renamed from djci. (dcji) New version with support for JMP32 gas/ChangeLog * testsuite/gas/bpf/bpf.exp: Run jump32 tests. * testsuite/gas/bpf/jump32.s: New file. * testsuite/gas/bpf/jump32.d: Likewise. opcodes/ChangeLog * bpf-desc.c: Regenerate. * bpf-desc.h: Likewise. * bpf-opc.c: Regenerate. * bpf-opc.h: Likewise.	6 years ago
Alan Modra	44e4546fa2	ubsan: m32c: left shift of negative value cpu/ * m32c.cpu (f-dsp-64-s16): Mask before shifting signed value. opcodes/ * m32c-ibld.c: Regenerate.	7 years ago
Alan Modra	b2b1453ad4	ubsan: frv: left shift of negative value More non-bugs flagged by ubsan, unless you happen to be compiling for a 1's complement host. cpu/ * frv.cpu (f-u12): Multiply rather than left shift signed values. (f-label16, f-label24): Likewise. opcodes/ * frv-ibld.c: Regenerate.	7 years ago
Alan Modra	0c115f8483	ubsan: m32c: left shift of negative value More nonsense fixing "bugs" with left shifts of signed values. Yes, the C standard does say this is undefined (and right shifts of signed values are implementation defined BTW) but in practice there is no problem with current machines. 1's complement is a thing of the past. cpu/ * m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting. (f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise. (f-dst32-rn-prefixed-QI): Likewise. (f-dsp-32-s32): Mask before shifting left. (f-dsp-48-u32, f-dsp-48-s32): Likewise. (f-bitbase32-16-s11-unprefixed): Multiply signed field rather than shifting left. (f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise. (h-gr-SI): Mask before shifting. opcodes/ * m32c-ibld.c: Regenerate.	7 years ago
Jose E. Marchesi	bd434cc4d9	cpu,opcodes,gas: fix neg and neg32 instructions in BPF This patch fixes the neg/neg32 BPF instructions, which have K (=0) instead of X (=1) in their header source bit, despite operating on registes. cpu/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (define-alu-insn-un): The unary BPF instructions (neg and neg32) use OP_SRC_K even if they operate only in registers. opcodes/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c: Regenerate. gas/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.d: Update expected opcode for `neg'. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise for `neg32'. * testsuite/gas/bpf/alu32-be.d: Likewise.	7 years ago
Nick Clifton	ae77468624	Add markers for 2.34 branch to the NEWS files and ChangeLogs.	7 years ago
Alan Modra	202e762b32	ubsan: fr30: left shift of negative value cpu/ * fr30.cpu (f-disp9, f-disp10, f-s10, f-rel9, f-rel12): Don't left shift signed values. opcodes/ * fr30-ibld.c: Regenerate.	7 years ago
Alan Modra	cc6aa1a6e0	ubsan: m32c: left shift of negative value There are probably a lot more of these still here. cpu/ * m32c.cpu (f-dsp-8-u16, f-dsp-8-s16): Rearrange to mask any sign bits before shifting rather than masking after shifting. (f-dsp-16-u16, f-dsp-16-s16, f-dsp-32-u16, f-dsp-32-s16): Likewise. (f-dsp-40-u16, f-dsp-40-s16, f-dsp-48-u16, f-dsp-48-s16): Likewise. (f-dsp-64-u16, f-dsp-8-s24): Likewise. (f-bitbase32-16-s19-unprefixed): Avoid signed left shift. opcodes/ * m32c-ibld.c: Regenerate.	7 years ago
Alan Modra	c9ae58fe32	ubsan: m32r: left shift of negative value cpu/ * m32r.cpu (f-disp8): Avoid left shift of negative values. (f-disp16, f-disp24): Likewise. opcodes/ * m32r-ibld.c: Regenerate.	7 years ago
Alan Modra	3e1056a1a6	ubsan: iq2000: left shift of negative value cpu/ * iq2000.cpu (f-offset): Avoid left shift of negative values. opcodes/ * iq2000-ibld.c: Regenerate.	7 years ago
Alan Modra	bcd9f578a9	ubsan: or1k: left shift of negative value cpu/ * or1korbis.cpu (f-disp26, f-disp21): Don't left shift negative values. opcodes/ * or1k-ibld.c: Regenerate.	7 years ago
Alan Modra	62e6599087	ubsan: bpf: left shift cannot be represented in type 'DI' (aka 'long') cpu/ * bpf.cpu (f-imm64): Avoid signed overflow. opcodes/ * bpf-ibld.c: Regenerate.	7 years ago

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