binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Nick Clifton	f432110413	Update the address and phone number of the FSF	22 years ago
Alan Modra	aef6203bd6	update copyright dates	22 years ago
Alexandre Oliva	d164ea7f0f	* m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended when loaded into XR registers.	23 years ago
Alexandre Oliva	40fa02078b	2000-05-25 Alexandre Oliva <aoliva@cygnus.com> * m10300-dis.c (disassemble): Negate negative accumulator's shift. 2000-05-24 Alexandre Oliva <aoliva@cygnus.com> * m10300-dis.c (disassemble, case FSREG, FDREG): Don't assume 32-bit longs when sign-extending operands. 2000-04-20 Alexandre Oliva <aoliva@cygnus.com> * m10300-opc.c: Remove MN10300_OPERAND_RELAX from all FSREGs. * m10300-dis.c (HAVE_AM33_2): Define. (disassemble): Use it. (HAVE_AM33): Redefine. (print_insn_mn10300): Fix mask for 5-byte extended insns. 2000-04-01 Alexandre Oliva <aoliva@cygnus.com> * m10300-opc.c: Renamed AM332 to AM33_2. 2000-03-31 Alexandre Oliva <aoliva@cygnus.com> * m10300-opc.c: Defined AM33 2.0 register operands. Added support for AM33 2.0 `imm8,(abs16)' addressing mode for btst, bset and bclr. Implemented `fbCC', `flCC', `dcpf' and all FP insns. * m10300-dis.c (print_insn_mn10300): Recognize 5byte extended insn code of AM33 2.0. (disassemble): Recognize FMT_D3. Print out FP register names.	23 years ago
Aldy Hernandez	cb87eaaf22	2001-06-15 Aldy Hernandez <aldyh@redhat.com> * m10300-opc.c (mn10300_opcodes): Change opcode for AM33 subc.	26 years ago
Nick Clifton	060d22b0d0	Fix typos in ChangeLogs; fix dates in copyright notices	26 years ago
Alan Modra	0d8dfecfe9	More portability patches. Include sysdep.h everywhere.	27 years ago
Alexandre Oliva	5728a7d74f	* m10300-opc.c: SP-based offsets are always unsigned.	27 years ago
Alexandre Oliva	907f179095	Reverted the comment about inc/inc4, that was already implied by RN02.	27 years ago
Alexandre Oliva	fa5e0d8d33	Fix typos. Add FIXME for 2-reg inc and inc4.	27 years ago
Jeff Law	a9af5e0481	* m10300-opc.c, m10300-dis.c: Add am33 support.	27 years ago
Richard Henderson	252b5132c7	19990502 sourceware import	28 years ago
Stan Shebs	071ea11e85	Initial creation of sourceware repository	28 years ago
Jeff Law	02c1364dd0	* m10300-opc.c: DSP instrutions which only write to one general register have no restrictions on matching operands.	28 years ago
Jeff Law	b657e68db8	* m10300-opc.c (lsr_add): Fix typo for "lsr_add imm,reg,reg,reg" case.	28 years ago
Jeff Law	fefb09e572	* m10300-opc.c (asr, lsr, asl): Fix am33 single bit shift opcode. pr17706	28 years ago
Jeff Law	ffd95d63ec	* m10300-opc.c: First cut at UDF instructions.	28 years ago
Jeff Law	9509185b58	* m10300-opc.c: Add entries for "no_match_operands" field in the opcode table.	28 years ago
Jeff Law	47254a1631	* m10300-opc.c: Add DSP autoincrement memory loads/stores.	28 years ago
Jeff Law	b0b57954c5	* m10300-opc.c: Add autoincrement memory loads/stores.	28 years ago
Jeff Law	f10a9bdead	* m10300-opc.c (mn10300_opcodes): Fix opcode for 4 operand "mul" and "mulu".	29 years ago
Jeff Law	ff7a9bc9b4	* m10300-opc.c: Reorder "movbu" and "movhu" instructions too. Why oh why didn't they take our advice about register prefixing. It would have avoided the ambigious syntax issues. Sigh.	29 years ago
Jeff Law	a841b47c4b	* m10300-opc.c: Reorder more instructions so that we do not accidentally match a mn10300 instruction when we really wanted an am33 instruction.	29 years ago
Jeff Law	0c9b3858c1	* m10300-dis.c: Only recognize instructions from the currently selected machine. * m10300-opc.c: Add field indicating the particular variant of the mn10300 each instruction is available on.	29 years ago
Jeff Law	59557be25d	* mn10300-opc.c (mn10300_opcodes): Fix typo in IMM24 versions of the am33 shift instructions.	29 years ago
Jeff Law	4da06098ff	* mn10300-opc.c (IMM32_HIGH8_MEM): New operand type. (mn10300_opcodes): Reorder so as to try and select opcodes from the core chip when multiple alternatives exist. Change several am33 instructions to use IMM32_HIGH8_MEM. Fix typos in "mac" and "macbu" instructions. Fix typos in a couple DSP instructions too.	29 years ago
Jeff Law	8b727aa4d3	* m10300-opc.c: Support one operand "asr", "lsr" and "asl" instructions. Support (sp) addressing mode by expanding it into (0,sp).	29 years ago
Jeff Law	c5a6e18b2e	* m10300-opc.c: Support 4 byte DSP instructions.	29 years ago
Jeff Law	b17af7f6ef	* m10300-opc.c: Support for 3 byte and 4 byte extended instructions found on the mn10300.	29 years ago
Jeff Law	9eb61c7c61	start-sanitize-am33 * m10300-opc.c (USP, SSP, MSP, PC, IMM4, EPSW, RN0, RM1): New operands for the am33. (mn10300_opcodes): Add new instructions from the am33. end-sanitize-am33 * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall". Snapshot current work.	29 years ago

12 Commits (4fa3602bd53183badf1d259128a5f951f32db8cb)