binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Alan Modra	b240011aba	include/ * dis-asm.h (disassemble_init_powerpc): Declare. opcodes/ * disassemble.c (disassemble_init_for_target): Handle ppc init. * ppc-dis.c (private): New var. (powerpc_init_dialect): Don't return calloc failure, instead use private. (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define. (powerpc_opcd_indices): New array. (disassemble_init_powerpc): New function. (print_insn_big_powerpc): Don't init dialect here. (print_insn_little_powerpc): Likewise. (print_insn_powerpc): Start search using powerpc_opcd_indices.	14 years ago
Alan Modra	aea77599d0	include/opcode/ * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR. opcodes/ * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500". * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New. (PPCVEC2, PPCTMR, E6500): New short names. (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt, mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx, lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl, lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl, lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC optional operands on sync instruction for E6500 target. bfd/ * archures.c: Add bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add entryies for bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500. gas/ * config/tc-ppc.c (md_show_usage): Document -me5500 and -me6500. (ppc_handle_align): Add termination nop opcode for e500mc family. * doc/as.texinfo: Document options -me5500 and -me6500. * doc/c-ppc.texi: Likewise. gas/testsuite/ * gas/ppc/e500mc64_nop.s: New test case for e500mc family termination nops. * gas/ppc/e500mc64_nop.d: Likewise. * gas/ppc/e5500_nop.s: Likewise. * gas/ppc/e5500_nop.d: Likewise. * gas/ppc/e6500_nop.s: Likewise. * gas/ppc/e6500_nop.d: Likewise. * gas/ppc/e6500.s: New. * gas/ppc/e6500.d: Likewise. * gas/ppc/ppc.exp: Run e6500, e500mc64_nop, e5500_nop, and e6500_nop.	14 years ago
Andreas Krebbel	5333187ab1	2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.txt: Set instruction type of pku to SS_L2RDRD. 2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/esa-g5.d: Move length field to the second operand. * gas/s390/esa-g5.s: Likewise.	14 years ago
Alan Modra	a597d2d3d2	cpu/ * mt.opc (print_dollarhex): Trim values to 32 bits. opcodes/ * mt-dis.c: Regenerate.	14 years ago
Alan Modra	3f26eb3af9	* v850-opc.c (extract_v8): Rearrange to make it obvious this is the inverse of corresponding insert function. (extract_d22, extract_u9, extract_r4): Likewise. (extract_d9): Correct sign extension. (extract_d16_15): Don't assume "long" is 32 bits, and don't rely on implementation defined behaviour for shift right of signed types. (extract_d16_16, extract_d17_16, extract_i9): Likewise. (extract_d23): Likewise, and correct mask.	14 years ago
Alan Modra	1f42f8b31d	gas/ * config/tc-crx.c: Include bfd_stdint.h. (getconstant): Remove irrelevant comment. Don't fail due to sign-extension of int mask. (check_range): Rewrite using unsigned arithmetic throughout. opcodes/ * crx-dis.c (print_arg): Mask constant to 32 bits. * crx-opc.c (cst4_map): Use int array. include/opcode/ * crx.h (cst4_map): Update declaration.	14 years ago
Alan Modra	cdb062354e	* arc-dis.c (BITS): Don't use shifts to mask off bits. (FIELDD): Sign extend with xor,sub.	14 years ago
Walter Lee	6f7be9592d	Improve TLS support on TILE-Gx/TILEPro: - Add support for TLS LE references. - Support linker optimization of TLS references. - Delete relocations of GOT/tp relative offsets beyond 32-bits. This brings binutils in line with the support expected in gcc 4.7, for TILE-Gx/TILEPro. bfd/ * reloc.c: Add BFD_RELOC_TILEPRO_TLS_GD_CALL, BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD, BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD, BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD, BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD, BFD_RELOC_TILEPRO_TLS_IE_LOAD, BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE, BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE, BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO, BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO, BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI, BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI, BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA, BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA, BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE, BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE, BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE, BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE, BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE, BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE, BFD_RELOC_TILEGX_TLS_GD_CALL, BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD, BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD, BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD, BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD, BFD_RELOC_TILEGX_TLS_IE_LOAD, BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD, BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD, BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD, BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD. Delete BFD_RELOC_TILEGX_IMM16_X0_HW1_GOT, BFD_RELOC_TILEGX_IMM16_X1_HW1_GOT, BFD_RELOC_TILEGX_IMM16_X0_HW2_GOT, BFD_RELOC_TILEGX_IMM16_X1_HW2_GOT, BFD_RELOC_TILEGX_IMM16_X0_HW3_GOT, BFD_RELOC_TILEGX_IMM16_X1_HW3_GOT, BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_GOT, BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_GOT, BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_GD, BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_GD, BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_GD, BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_GD, BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_GD, BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_GD, BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_GD, BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_GD, BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_IE, BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_IE, BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_IE, BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_IE, BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_IE, BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_IE, BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_IE, BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_IE. * elf32-tilepro.c (tilepro_elf_howto_table): Update tilepro relocations. (tilepro_reloc_map): Ditto. (tilepro_info_to_howto_rela): Ditto. (reloc_to_create_func): Ditto. (tilepro_tls_translate_to_le): New. (tilepro_tls_translate_to_ie): New. (tilepro_elf_tls_transition): New. (tilepro_elf_check_relocs): Handle new tls relocations. (tilepro_elf_gc_sweep_hook): Ditto. (allocate_dynrelocs): Ditto. (tilepro_elf_relocate_section): Ditto. (tilepro_replace_insn): New. (insn_mask_X1): New. (insn_mask_X0_no_dest_no_srca): New (insn_mask_X1_no_dest_no_srca): New (insn_mask_Y0_no_dest_no_srca): New (insn_mask_Y1_no_dest_no_srca): New (srca_mask_X0): New (srca_mask_X1): New (insn_tls_le_move_X1): New (insn_tls_le_move_zero_X0X1): New (insn_tls_ie_lw_X1): New (insn_tls_ie_add_X0X1): New (insn_tls_ie_add_Y0Y1): New (insn_tls_gd_add_X0X1): New (insn_tls_gd_add_Y0Y1): New * elfxx-tilegx.c (tilegx_elf_howto_table): Update tilegx relocations. (tilegx_reloc_map): Ditto. (tilegx_info_to_howto_rela): Ditto. (reloc_to_create_func): Ditto. (tilegx_elf_link_hash_table): New field disable_le_transition. (tilegx_tls_translate_to_le): New. (tilegx_tls_translate_to_ie): New. (tilegx_elf_tls_transition): New. (tilegx_elf_check_relocs): Handle new tls relocations. (tilegx_elf_gc_sweep_hook): Ditto. (allocate_dynrelocs): Ditto. (tilegx_elf_relocate_section): Ditto. (tilegx_copy_bits): New. (tilegx_replace_insn): New. (insn_mask_X1): New. (insn_mask_X0_no_dest_no_srca): New. (insn_mask_X1_no_dest_no_srca): New. (insn_mask_Y0_no_dest_no_srca): New. (insn_mask_Y1_no_dest_no_srca): New. (insn_mask_X0_no_operand): New. (insn_mask_X1_no_operand): New. (insn_mask_Y0_no_operand): New. (insn_mask_Y1_no_operand): New. (insn_tls_ie_ld_X1): New. (insn_tls_ie_ld4s_X1): New. (insn_tls_ie_add_X0X1): New. (insn_tls_ie_add_Y0Y1): New. (insn_tls_ie_addx_X0X1): New. (insn_tls_ie_addx_Y0Y1): New. (insn_tls_gd_add_X0X1): New. (insn_tls_gd_add_Y0Y1): New. (insn_move_X0X1): New. (insn_move_Y0Y1): New. (insn_add_X0X1): New. (insn_add_Y0Y1): New. (insn_addx_X0X1): New. (insn_addx_Y0Y1): New. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * tc-tilepro.c (O_tls_le): Define operator. (O_tls_le_lo16): Ditto. (O_tls_le_hi16): Ditto. (O_tls_le_ha16): Ditto. (O_tls_gd_call): Ditto. (O_tls_gd_add): Ditto. (O_tls_ie_load): Ditto. (md_begin): Delete old operators; handle new operators. (emit_tilepro_instruction): Ditto. (md_apply_fix): Ditto. * tc-tilegx.c (O_hw1_got): Delete operator. (O_hw2_got): Ditto. (O_hw3_got): Ditto. (O_hw2_last_got): Ditto. (O_hw1_tls_gd): Ditto. (O_hw2_tls_gd): Ditto. (O_hw3_tls_gd): Ditto. (O_hw2_last_tls_gd): Ditto. (O_hw1_tls_ie): Ditto. (O_hw2_tls_ie): Ditto. (O_hw3_tls_ie): Ditto. (O_hw2_last_tls_ie): Ditto. (O_hw0_tls_le): Define operator. (O_hw0_last_tls_le): Ditto. (O_hw1_last_tls_le): Ditto. (O_tls_gd_call): Ditto. (O_tls_gd_add): Ditto. (O_tls_ie_load): Ditto. (O_tls_add): Ditto. (md_begin): Delete old operators; handle new operators. (emit_tilegx_instruction): Ditto. (md_apply_fix): Ditto. * doc/c-tilegx.texi: Delete old operators; document new operators. * doc/c-tilepro.texi: Ditto. include/elf/ * tilegx.h (R_TILEGX_IMM16_X0_HW1_GOT): Delete. (R_TILEGX_IMM16_X1_HW1_GOT): Ditto. (R_TILEGX_IMM16_X0_HW2_GOT): Ditto. (R_TILEGX_IMM16_X1_HW2_GOT): Ditto. (R_TILEGX_IMM16_X0_HW3_GOT): Ditto. (R_TILEGX_IMM16_X1_HW3_GOT): Ditto. (R_TILEGX_IMM16_X0_HW2_LAST_GOT): Ditto. (R_TILEGX_IMM16_X1_HW2_LAST_GOT): Ditto. (R_TILEGX_IMM16_X0_HW1_TLS_GD): Ditto. (R_TILEGX_IMM16_X1_HW1_TLS_GD): Ditto. (R_TILEGX_IMM16_X0_HW2_TLS_GD): Ditto. (R_TILEGX_IMM16_X1_HW2_TLS_GD): Ditto. (R_TILEGX_IMM16_X0_HW3_TLS_GD): Ditto. (R_TILEGX_IMM16_X1_HW3_TLS_GD): Ditto. (R_TILEGX_IMM16_X0_HW2_LAST_TLS_GD): Ditto. (R_TILEGX_IMM16_X1_HW2_LAST_TLS_GD): Ditto. (R_TILEGX_IMM16_X0_HW1_TLS_IE): Ditto. (R_TILEGX_IMM16_X1_HW1_TLS_IE): Ditto. (R_TILEGX_IMM16_X0_HW2_TLS_IE): Ditto. (R_TILEGX_IMM16_X1_HW2_TLS_IE): Ditto. (R_TILEGX_IMM16_X0_HW3_TLS_IE): Ditto. (R_TILEGX_IMM16_X1_HW3_TLS_IE): Ditto. (R_TILEGX_IMM16_X0_HW2_LAST_TLS_IE): Ditto. (R_TILEGX_IMM16_X1_HW2_LAST_TLS_IE): Ditto. (R_TILEGX_IMM16_X0_HW0_TLS_LE): New relocation. (R_TILEGX_IMM16_X1_HW0_TLS_LE): Ditto. (R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE): Ditto. (R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE): Ditto. (R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE): Ditto. (R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE): Ditto. (R_TILEGX_TLS_GD_CALL): Ditto. (R_TILEGX_IMM8_X0_TLS_GD_ADD): Ditto. (R_TILEGX_IMM8_X1_TLS_GD_ADD): Ditto. (R_TILEGX_IMM8_Y0_TLS_GD_ADD): Ditto. (R_TILEGX_IMM8_Y1_TLS_GD_ADD): Ditto. (R_TILEGX_TLS_IE_LOAD): Ditto. (R_TILEGX_IMM8_X0_TLS_ADD): Ditto. (R_TILEGX_IMM8_X1_TLS_ADD): Ditto. (R_TILEGX_IMM8_Y0_TLS_ADD): Ditto. (R_TILEGX_IMM8_Y1_TLS_ADD): Ditto. * tilepro.h (R_TILEPRO_TLS_GD_CALL): New relocation. (R_TILEPRO_IMM8_X0_TLS_GD_ADD): Ditto. (R_TILEPRO_IMM8_X1_TLS_GD_ADD): Ditto. (R_TILEPRO_IMM8_Y0_TLS_GD_ADD): Ditto. (R_TILEPRO_IMM8_Y1_TLS_GD_ADD): Ditto. (R_TILEPRO_TLS_IE_LOAD): Ditto. (R_TILEPRO_IMM16_X0_TLS_LE): Ditto. (R_TILEPRO_IMM16_X1_TLS_LE): Ditto. (R_TILEPRO_IMM16_X0_TLS_LE_LO): Ditto. (R_TILEPRO_IMM16_X1_TLS_LE_LO): Ditto. (R_TILEPRO_IMM16_X0_TLS_LE_HI): Ditto. (R_TILEPRO_IMM16_X1_TLS_LE_HI): Ditto. (R_TILEPRO_IMM16_X0_TLS_LE_HA): Ditto. (R_TILEPRO_IMM16_X1_TLS_LE_HA): Ditto. include/opcode/ * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS, TILEGX_OPC_LD_TLS. * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS, TILEPRO_OPC_LW_TLS_SN. opcodes/ * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS. * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and TILEPRO_OPC_LW_TLS_SN.	14 years ago
H.J. Lu	82c2def5ff	Add HLEPrefixNone/HLEPrefixLock/HLEPrefixAny/HLEPrefixRelease gas/ 2012-02-21 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (check_hle): Use HLEPrefixNone, HLEPrefixLock, HLEPrefixAny and HLEPrefixRelease. opcodes/ 2012-02-21 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (HLEPrefixNone): New. (HLEPrefixLock): Likewise. (HLEPrefixAny): Likewise. (HLEPrefixRelease): Likewise.	14 years ago
H.J. Lu	42164a7195	Implement Intel Transactional Synchronization Extensions gas/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (HLE_PREFIX): New. (check_hle): Likewise. (_i386_insn): Add have_hle. (cpu_arch): Add .hle and .rtm. (md_assemble): Call check_hle if i.have_hle isn't zero. (parse_insn): Set i.have_hle to 1 for HLE prefix. (output_jump): Support up to 2 byte opcode. * doc/c-i386.texi: Document hle/.hle and rtm/.rtm. gas/testsuite/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/hle-intel.d: New. * gas/i386/hle.d: Likewise. * gas/i386/hle.s: Likewise. * gas/i386/hlebad.l: Likewise. * gas/i386/hlebad.s: Likewise. * gas/i386/rtm-intel.d: Likewise. * gas/i386/rtm.d: Likewise. * gas/i386/rtm.s: Likewise. * gas/i386/x86-64-hle-intel.d: Likewise. * gas/i386/x86-64-hle.d: Likewise. * gas/i386/x86-64-hle.s: Likewise. * gas/i386/x86-64-hlebad.l: Likewise. * gas/i386/x86-64-hlebad.s: Likewise. * gas/i386/x86-64-rtm-intel.d: Likewise. * gas/i386/x86-64-rtm.d: Likewise. * gas/i386/x86-64-rtm.s: Likewise. * gas/i386/i386.exp: Run hle, hle-intel, hlebad x86-64-hle, rtm, rtm-intel, x86-64-hle-intel, x86-64-hlebad, x86-64-rtm and x86-64-rtm-intel. include/opcode/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * i386.h (XACQUIRE_PREFIX_OPCODE): New. (XRELEASE_PREFIX_OPCODE): Likewise. opcodes/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (HLE_Fixup1): New. (HLE_Fixup2): Likewise. (HLE_Fixup3): Likewise. (Ebh1): Likewise. (Evh1): Likewise. (Ebh2): Likewise. (Evh2): Likewise. (Ebh3): Likewise. (Evh3): Likewise. (MOD_C6_REG_7): Likewise. (MOD_C7_REG_7): Likewise. (RM_C6_REG_7): Likewise. (RM_C7_REG_7): Likewise. (XACQUIRE_PREFIX): Likewise. (XRELEASE_PREFIX): Likewise. (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov. (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg, not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use MOD_C6_REG_7 and MOD_C7_REG_7. (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7. (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and xtest. (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX. (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b. * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and CPU_RTM_FLAGS. (cpu_flags): Add CpuHLE and CpuRTM. (opcode_modifiers): Add HLEPrefixOk. * i386-opc.h (CpuHLE): New. (CpuRTM): Likewise. (HLEPrefixOk): Likewise. (i386_cpu_flags): Add cpuhle and cpurtm. (i386_opcode_modifier): Add hleprefixok. * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory operand. Add xacquire, xrelease, xabort, xbegin, xend and xtest. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	14 years ago
DJ Delorie	21abe33a9b	* rl78-decode.opc (rl78_decode_opcode): Add NOT1. * rl78-decode.c: Regenerate. * config/rl78-parse.y (NOT1): Add.	14 years ago
Alan Modra	e20cc039b4	PR binutils/10173 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.	14 years ago
Andreas Schwab	e143d25c73	* gas/testsuite/gas/m68k/pmove.s, gas/testsuite/gas/m68k/pmove.d: New test. * gas/testsuite/gas/m68k/all.exp: Run it. * opcodes/m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx register and move them after pmove with PSR/PCSR register.	14 years ago
H.J. Lu	8729a6f6a5	Add vmfunc gas/ 2012-01-13 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add ".vmfunc". * doc/c-i386.texi: Document vmfunc. gas/testsuite/ 2012-01-13 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run vmfunc and x86-64-vmfunc. * gas/i386/vmfunc.d: New. * gas/i386/vmfunc.s: Likewise. * gas/i386/x86-64-vmfunc.d: Likewise. opcodes/ 2012-01-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (mod_table): Add vmfunc. * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS. (cpu_flags): CpuVMFUNC. * i386-opc.h (CpuVMFUNC): New. (i386_cpu_flags): Add cpuvmfunc. * i386-opc.tbl: Add vmfunc. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	14 years ago
Nick Clifton	23e1d3291c	Rotate ChangeLogs	14 years ago
Nick Clifton	5011093dd0	* frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bit hosts. * cgen-asm.c (cgen_parse_signed_integer): Add code to handle the sign extension of negative values on a 64-bit host. * frv-asm.c: Regenerate. * gas/frv/immediates.s: New test file - checks assembly of constant values. * gas/frv/immediates.d: Expected disassmbly. * gas/frv/allinsn.exp: Run the new test.	15 years ago
Alan Modra	8ebac3aae9	* ppc-opc.c (ISA_V2): Define and use for relevant BO field tests. (valid_bo_pre_v2, valid_bo_post_v2): New functions, extracted from.. (valid_bo): ..here. When disassembling, accept either 'y' or 'at' type encoding on second pass. (powerpc_opcodes): Use ISA_V2 to enable branch insns rather than POWER4. * ppc-dis.c (print_insn_powerpc): Delete dialect_orig. Instead ignore deprecated on second pass.	15 years ago
Andrew Pinski	bb8e626db9	opcodes: 2011-12-08 Andrew Pinski <apinski@cavium.com> * mips-opc.c (mips_builtin_opcodes): Add "pause". gas/testsuite: 2011-12-08 Andrew Pinski <apinski@cavium.com> * gas/mips/mips32-mt.d: Add pause instruction encoding to the end. * gas/mips/micromips@mips32r2.d: Likewise. * gas/mips/mips32r2.d: Likewise. * gas/mips/mips32-mt.s: Add pause instruction to the end. * gas/mips/mips32r2.s: Likewise.	15 years ago
Andrew Pinski	432233b359	bfd: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * archures.c (bfd_mach_mips_octeon2): New macro * bfd-in2.h: Regenerate. * cpu-mips.c (I_mipsocteon2): New enum value. (arch_info_struct): Add bfd_mach_mips_octeon2. * elfxx-mips.c (_bfd_elf_mips_mach): Support E_MIPS_MACH_OCTEON2. (mips_set_isa_flags): Add bfd_mach_mips_octeon2. (mips_mach_extensions): Add bfd_mach_mips_octeon2. gas: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * tc-mips.c (CPU_IS_OCTEON): Add Octeon2. (mips_cpu_info_table): Add Octeon2. * doc/c-mips.texi: Document octeon2 as an acceptable value for -march=. gas/testsuite: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * gas/mips/mips.exp: Add Octeon2 for an architecture. Run octeon2 test. * gas/mips/octeon2.d: New file. * gas/mips/octeon2.s: New file. include/opcode: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. (INSN_OCTEON2): New macro. (CPU_OCTEON2): New macro. (OPCODE_IS_MEMBER): Add Octeon2. opcodes: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * mips-dis.c (mips_arch_choices): Add Octeon2. For "octeon+", just include OcteonP for the insn. * mips-opc.c (IOCT): Include Octeon2. (IOCTP): Include Octeon2. (IOCT2): New macro. (mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad", "ladd", "lai", "laid", "las", "lasd", "law", "lawd". Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard loads are, and add IOCT2 to them. Add "lbx" and "lhux". Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00", "qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03". Add "zcb" and "zcbt".	15 years ago
Andrew Pinski	dd6a37e700	opcode/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * mips-dis.c (mips_arch_choices): Add Octeon+. * mips-opc.c (IOCT): Include Octeon+. (IOCTP): New macro. (mips_builtin_opcodes): Add "saa" and "saad". bfd/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * archures.c (bfd_mach_mips_octeonp): New macro. * bfd-in2.h: Regenerate. * bfd/cpu-mips.c (I_mipsocteonp): New enum value. (arch_info_struct): Add bfd_mach_mips_octeonp. * elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp. (mips_mach_extensions): Add bfd_mach_mips_octeonp. include/opcodes/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. (INSN_OCTEONP): New macro. (CPU_OCTEONP): New macro. (OPCODE_IS_MEMBER): Add Octeon+. (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values. gas/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * config/tc-mips.c (CPU_IS_OCTEON): New macro function. (CPU_HAS_SEQ): Change to use CPU_IS_OCTEON. (NO_ISA_COP): Likewise. (macro) <ld_st>: Add support when off0 is true. Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB. (mips_cpu_info_table): Add octeon+. * doc/c-mips.texi: Document octeon+ as an acceptable value for -march=. gas/testsuite/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * gas/mips/mips.exp: Add octeon+ for an architecture. Run octeon-saa-saad test. (run_dump_test_arch): For Octeon architectures, also try octeon@. * gas/mips/octeon-pref.d: Remove -march=octeon from command line. * gas/mips/octeon.d: Likewise. * gas/mips/octeon-saa-saad.d: New file. * gas/mips/octeon-saa-saad.s: New file	15 years ago
Pierre Muller	0c7533d365	* mips-dis.c (print_insn_micromips): Rename local variable iprintf to infprintf to avoid shadow warning.	15 years ago
Nick Clifton	eda81062a6	* po/it.po: Updated Italian translation.	15 years ago
Maciej W. Rozycki	514f48bb1d	* micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP for "alnv.ps".	15 years ago
Nick Clifton	207d428dce	* po/it.po: New Italian translation. * configure.in (ALL_LINGUAS): Add it. * configure: Regenerate. * po/opcodes.pot: Regenerate.	15 years ago
DJ Delorie	99c513f6ac	[.] * configure.ac (rl78--) New case. * configure: Regenerate. [bfd] * Makefile.am (ALL_MACHINES): Add cpu-rl78.lo. (ALL_MACHINES_CFILES): Add cpu-rl78.c. (BFD32_BACKENDS): Add elf32-rl78.lo. (BFD32_BACKENDS_CFILES): Add elf32-rl78.c. (Makefile.in): Regenerate. * archures.c (bfd_architecture): Define bfd_arch_rl78. (bfd_archures_list): Add bfd_rl78_arch. * config.bfd: Add rl78--elf. configure.in: Add bfd_elf32_rl78_vec. * reloc.c (bfd_reloc_code_type): Add BFD_RELOC_RL78_* relocations. * targets.c (bfd_target_vector): Add bfd_elf32_rl78_vec. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * cpu-rl78.c: New file. * elf32-rl78.c: New file. [binutils] * readelf.c: Include elf/rl78.h (guess_is_rela): Handle EM_RL78. (dump_relocations): Likewise. (get_machine_name): Likewise. (is_32bit_abs_reloc): Likewise. * NEWS: Mention addition of RL78 support. * MAINTAINERS: Add myself as RL78 port maintainer. [gas] * Makefile.am (TARGET_CPU_CFILES): Add tc-rl78.c. (TARGET_CPU_HFILES): Add rc-rl78.h. (EXTRA_DIST): Add rl78-parse.c and rl78-parse.y. (rl78-parse.c, rl78-parse.h, rl78-parse.o, rl78-defs.h): New rules. * Makefile.in: Regenerate. * configure.in: Add rl78 case. * configure: Regenerate. * configure.tgt: Add rl78 case. * config/rl78-defs.h: New file. * config/rl78-parse.y: New file. * config/tc-rl78.c: New file. * config/tc-rl78.h: New file. * NEWS: Add Renesas RL78. * doc/Makefile.am (c-rl78.texi): New. * doc/Makefile.in: Likewise. * doc/all.texi: Enable it. * doc/as.texi: Add it. [include] * dis-asm.h (print_insn_rl78): Declare. [include/elf] * common.h (EM_RL78, EM_78K0R): New. * rl78.h: New. [include/opcode] * rl78.h: New file. [ld] * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32rl78.c. (+eelf32rl78.c): New rule. * Makefile.in: Regenerate. * configure.tgt: Add rl78-- case. * emulparams/elf32rl78.sh: New file. * NEWS: Mention addition of Renesas RL78 support. [opcodes] * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and rl78-dis.c. (MAINTAINERCLEANFILES): Add rl78-decode.c. (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c. * Makefile.in: Regenerate. * configure.in: Add bfd_rl78_arch case. * configure: Regenerate. * disassemble.c: Define ARCH_rl78. (disassembler): Add ARCH_rl78 case. * rl78-decode.c: New file. * rl78-decode.opc: New file. * rl78-dis.c: New file.	15 years ago
Peter Bergner	a08fc94222	opcodes/ * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq, dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq., diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad instructions.	15 years ago
Nick Clifton	f6dd4781ef	PR binutils/13348 * i386-dis.c (print_insn): Fix testing of array subscript.	15 years ago
Joern Rennecke	fd936b4c69	cpu: * epiphany.opc (parse_branch_addr): Fix type of valuep. Cast value before printing it as a long. (parse_postindex): Fix type of valuep. opcodes: * epiphany-asm.c, epiphany-opc.h: Regenerate.	15 years ago
Joern Rennecke	56b1318518	gas: * doc/as.texinfo [EPIPHANY]: Include c-epiphany.texi to avoid duplication. opcodes: * disassemble.c (ARCH_epiphany): Move into alphasorted spot.	15 years ago
Nick Clifton	cfb8c0921c	bfd: * Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo . (ALL_MACHINES_CFILES): Add cpu-epiphany.c . (BFD32_BACKENDS): Add elf32-epiphany.lo . (BFD32_BACKENDS_CFILES): Add elf32-epiphany.c . * Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate. * archures.c (bfd_arch_epiphany): Add. (bfd_mach_epiphany16, bfd_mach_epiphany32): Define. (bfd_epiphany_arch): Declare. (bfd_archures_list): Add &bfd_epiphany_arch. * config.bfd (epiphany--elf): New target case. configure.in (bfd_elf32_epiphany_vec): New target vector case. * reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation. (BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise. (BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise. (BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise. * targets.c (bfd_elf32_epiphany_vec): Declare. (_bfd_target_vector): Add bfd_elf32_epiphany_vec. * po/SRC-POTFILES.in, po/bfd.pot: Regenerate. * cpu-epiphany.c, elf32-epiphany.c: New files. binutils: * readelf.c (include "elf/epiphany.h") (guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY. (get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise. (is_16bit_abs_reloc, is_none_reloc): Likewise. * po/binutils.pot: Regenerate. cpu: * cpu/epiphany.cpu, cpu/epiphany.opc: New files. gas: * NEWS: Mention addition of Adapteva Epiphany support. * config/tc-epiphany.c, config/tc-epiphany.h: New files. * Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c . (TARGET_CPU_HFILES): Add config/tc-epiphany.h . * Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate. * configure.in: Also set using_cgen for epiphany. * configure.tgt: Handle epiphany. * doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi . * doc/all.texi: Set EPIPHANY. * doc/as.texinfo: Add EPIPHANY-specific text. * doc/c-epiphany.texi: New file. * po/gas.pot: Regenerate. gas/testsuite: * gas/epiphany: New directory. include: * dis-asm.h (print_insn_epiphany): Declare. * elf/epiphany.h: New file. * elf/common.h (EM_ADAPTEVA_EPIPHANY): Define. ld: * NEWS: Mention addition of Adapteva Epiphany support. * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c . (eelf32epiphany.c): New rule. * Makefile.in: Regenerate. * configure.tgt: Handle epiphany--elf. po/ld.pot: Regenerate. * testsuite/ld-srec/srec.exp: xfail epiphany. * emulparams/elf32epiphany.sh: New file. opcodes: * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h . (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c, epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c . (CLEANFILES): Add stamp-epiphany. (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it. (stamp-epiphany): New rule. * Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate. * configure.in: Handle bfd_epiphany_arch. * disassemble.c (ARCH_epiphany): Define. (disassembler): Handle bfd_arch_epiphany. * epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files. * epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise. * epiphany-opc.h: Likewise.	15 years ago
Julian Brown	c373271616	opcodes/ * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml. gas/testsuite/ * gas/m68k/all.exp (movem-offset): Add test. * gas/m68k/movem-offset.s: New test. * gas/m68k/movem-offset.d: New.	15 years ago
Andreas Krebbel	9cae27dcb1	2011-10-21 Jan Glauber <jang@linux.vnet.ibm.com> * s390-opc.txt: Add CPUMF instructions. 2011-10-21 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/zarch-z10.d: Add CPUMF instructions. * gas/s390/zarch-z10.s: Likewise.	15 years ago
Julian Brown	a415b1cd63	Jie Zhang <jie@codesourcery.com> Julian Brown <julian@codesourcery.com> gas/ * config/tc-arm.c (parse_shifter_operand): Fix handling of explicit rotation. (encode_arm_shifter_operand): Likewise. gas/testsuite/ * gas/arm/adrl.d: Adjust. * gas/arm/immed2.d: New test. * gas/arm/immed2.s: New test. ld/testsuite/ * ld-arm/cortex-a8-fix-b-plt.d: Adjust. * ld-arm/cortex-a8-fix-bcc-plt.d: Adjust. * ld-arm/cortex-a8-fix-bl-plt.d: Adjust. * ld-arm/cortex-a8-fix-bl-rel-plt.d: Adjust. * ld-arm/cortex-a8-fix-blx-plt.d: Adjust. * ld-arm/ifunc-1.dd: Adjust. * ld-arm/ifunc-2.dd: Adjust. * ld-arm/ifunc-3.dd: Adjust. * ld-arm/ifunc-4.dd: Adjust. * ld-arm/ifunc-5.dd: Adjust. * ld-arm/ifunc-6.dd: Adjust. * ld-arm/ifunc-7.dd: Adjust. * ld-arm/ifunc-8.dd: Adjust. * ld-arm/ifunc-9.dd: Adjust. * ld-arm/ifunc-10.dd: Adjust. * ld-arm/ifunc-14.dd: Adjust. * ld-arm/ifunc-15.dd: Adjust. * ld-arm/ifunc-16.dd: Adjust. opcodes/ * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.	15 years ago
Nick Clifton	d569865703	Updated Bulgarian, Spanish, Finnish, French, Russian and Ukranian translations.	15 years ago
Jan Beulich	989993d80a	gas/testsuite/ 2011-09-28 Jan Beulich <jbeulich@suse.com> * gas/ppc/476.s: Fix lswi first operand. * gas/ppc/476.d: Adjust expected output. * gas/ppc/a2.s: Fix lswi first operand. * gas/ppc/a2.d: Adjust expected output. * gas/ppc/power6.s: Fix lfdpx first operand. * gas/ppc/power6.d: Adjust expected output. opcodes/ 2011-09-28 Jan Beulich <jbeulich@suse.com> * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX, RBX): New. (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset. (powerpc_opcodes): Use RAX for second and RBXC for third operand of lswx. Use NBI for third operand of lswi. Use FRTp for first operand of lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively on DFP quad instructions.	15 years ago
David S. Miller	92a7795b59	opcodes/ * sparc-opc.c (sparc_opcodes): Fix random instruction to write to a float instead of an integer register. gas/testsuite/ * gas/sparc/hpcvis3.s: Update to use float reg for random insn. * gas/sparc/hpcvis3.d: Likewise.	15 years ago
David S. Miller	e91d10767a	Add sparc integer multiply-add instructions. opcodes/ * sparc-opc.c (sparc_opcodes): Add integer multiply-add instructions. gas/testsuite/ * gas/sparc/ima.d: New test. * gas/sparc/ima.s: New test source. * gas/sparc/sparc.exp: Run new test.	15 years ago
David S. Miller	9e8c70f96b	Annotate sparc objects with cpu hardware capabilities used. bfd/ * elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): New. * elfxx-sparc.h: Declare it. * elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Call it. * elf64-sparc.c (elf64_sparc_merge_private_bfd_data): Likewise. binutils/ * readelf.c (display_sparc_hwcaps): New. (display_sparc_gnu_attribute): New. (process_sparc_specific): New. (process_arch_specific): When EM_SPARC, EM_SPARC32PLUS, or EM_SPARCV9 invoke process_sparc_specific. gas/ * config/tc-sparc.c (hwcap_seen): New bitmask, defined when not TE_SOLARIS. (sparc_ip): When not TE_SOLARIS, accumulate hwcap bits from sparc_opcode->flags of instruction into hwcap_seen. (sparc_md_end): Create Tag_GNU_Sparc_HWCAPS attribute if hwcap_seen is non-zero and not TE_SOLARIS. gas/testsuite/ * gas/sparc/hpcvis3.s: Update for fixed fchksum16 mnemonic. * gas/sparc/hpcvis3.d: Likewise. include/elf/ * sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute. (ELF_SPARC_HWCAP_): New HWCAPS bitmask values. include/opcode/ sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int. (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. opcodes/ * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag bits. Fix "fchksm16" mnemonic.	15 years ago
Andreas Schwab	b2ea18299b	Add PR markers	15 years ago
David S. Miller	8dbb9eb3c6	opcodes/ * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd' This has been reported as being accepted by the Sun assmebler. gas/testsuite/ * gas/sparc/save-args.[sd]: New test. * gas/sparc/sparc.exp: Run new test.	15 years ago
David S. Miller	9bf29d72d4	opcodes/ The changes below bring 'mov' and 'ticc' instructions into line with the V8 SPARC Architecture Manual. * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'. * sparc-opc.c (sparc_opcodes): Add alias entries for 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs'; 'mov regrs2,%wim' and 'mov regrs2,%tbr'. * sparc-opc.c (sparc_opcodes): Move/Change entries for 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim' and 'mov imm,%tbr'. * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above mov aliases. gas/testsuite/ * gas/sparc/ticc-imm-reg.[sd]: New test. * gas/sparc/v8-movwr-imm.[sd]: New test. * gas/sparc/sparc.exp: Run new tests.	15 years ago
David S. Miller	cdf492019f	opcodes/ * sparc-opc.c (pdistn): Destination is integer not float register. gas/testsuite/ * gas/sparc/hpcvis3.s: Correct pdistn test. * gas/sparc/hpcvis3.d: Likewise.	15 years ago
Andreas Schwab	96e67898bc	* gas/testsuite/gas/m68k/all.exp: Run "mode5" test also with -mcpu=5200. * gas/testsuite/gas/m68k/mode5.s: Add moveml testcases. * gas/testsuite/gas/m68k/mode5.d: Update. * opcodes/m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.	15 years ago
Nick Clifton	7cf8042268	Updated Spanish translations.	15 years ago
Nick Clifton	dc15e575ad	Move cpu files from cgen/cpu to top level cpu directory.	15 years ago
Maciej W. Rozycki	dec0624dcd	gas/ * config/tc-mips.c (mips_set_options): Add ase_mcu. (mips_opts): Initialise ase_mcu to -1. (ISA_SUPPORTS_MCU_ASE): New macro. (MIPS_CPU_ASE_MCU): Likewise. (is_opcode_valid): Handle MCU. (macro_build, macro): Likewise. (validate_mips_insn, validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_MCU and OPTION_NO_MCU. (md_longopts): Add mmcu and mno-mcu. (md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU. (mips_after_parse_args): Handle MCU. (s_mipsset): Likewise. (md_show_usage): Handle MCU options. * doc/as.texinfo: Document -mmcu and -mno-mcu options. * doc/c-mips.texi: Likewise, and document ".set mcu" and ".set nomcu" directives. gas/testsuite/ * gas/mips/micromips@mcu.d: New test. * gas/mips/mcu.d: Likewise. * gas/mips/mcu.s: New test source. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. (INSN_ASE_MASK): Add the MCU bit. (INSN_MCU): New macro. (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. opcodes/ * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2" and "mips64r2". (print_insn_args, print_insn_micromips): Handle MCU. * micromips-opc.c (MC): New macro. (micromips_opcodes): Add "aclr", "aset" and "iret". * mips-opc.c (MC): New macro. (mips_builtin_opcodes): Add "aclr", "aset" and "iret".	15 years ago
Maciej W. Rozycki	2b0c8b40ed	include/opcode/ * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros. (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise. (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise. (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise. (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise. (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise. (INSN2_READ_GPR_MMN): Likewise. (INSN2_READ_FPR_D): Change the bit used. (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise. (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise. (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise. (INSN2_COND_BRANCH): Likewise. (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros. (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise. (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise. (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise. (INSN2_MOD_GPR_MN): Likewise. gas/ * config/tc-mips.c (gpr_mod_mask): Remove INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG, INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN, INSN2_MOD_GPR_MP and INSN2_MOD_GPR_MQ opcode register use checks. (gpr_read_mask): Add INSN2_READ_GPR_MC, INSN2_READ_GPR_ME INSN2_READ_GPR_MG, INSN2_READ_GPR_MJ, INSN2_READ_GPR_MMN, INSN2_READ_GPR_MP and INSN2_READ_GPR_MQ opcode register use checks. (gpr_write_mask): Replace INSN2_WRITE_GPR_S opcode register use flag with INSN_WRITE_GPR_S. Add INSN2_WRITE_GPR_MB, INSN2_WRITE_GPR_MHI, INSN2_WRITE_GPR_MJ and INSN2_WRITE_GPR_MP opcode register use checks. (can_swap_branch_p): Enable microMIPS branch swapping. (append_insn): Likewise. gas/testsuite/ * gas/mips/micromips.d: Update according to changes to enable microMIPS branch swapping. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips@jal-svr4pic.d: Likewise. * gas/mips/micromips@loc-swap.d: Likewise. * gas/mips/micromips@loc-swap-dis.d: Likewise. opcodes/ * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros. (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise. (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise. (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros. (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise. (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise. (WR_s): Update macro. (micromips_opcodes): Update register use flags of: "addiu", "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu", "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j", "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li", "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not", "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw", "swm" and "xor" instructions.	15 years ago
David S. Miller	ea783ef3a0	include/opcode/ * sparc.h: Document new format codes '4', '5', and '('. (OPF_LOW4, RS3): New macros. opcodes/ * sparc-dis.c (v9a_ast_reg_names): Add "cps". (X_RS3): New macro. (print_insn_sparc): Handle '4', '5', and '(' format codes. Accept %asr numbers below 28. * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3 instructions. gas/ * config/tc-sparc.c (v9a_asr_table): Add "cps". (sparc_ip): Handle '4', '5' and '(' format codes. gas/testsuite * gas/sparc/hpcvis3.d: New test. * gas/sparc/hpcvis3.s: New test source. * gas/sparc/sparc.exp: Run new test.	15 years ago
Quentin Neill	3929df0978	opcodes/ 2011-08-02 Quentin Neill <quentin.neill@amd.com> * i386-dis.c (xop_table): Remove spurious bextr insn.	15 years ago
H.J. Lu	d7921315ba	Check R_X86_64_32 overflow and allow R_X86_64_64 for x32. bfd/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * archures.c (bfd_mach_i386_intel_syntax): New. (bfd_mach_i386_i8086): Updated. (bfd_mach_i386_i386): Likewise. (bfd_mach_x86_64): Likewise. (bfd_mach_x64_32): Likewise. (bfd_mach_i386_i386_intel_syntax): Likewise. (bfd_mach_x86_64_intel_syntax): Likewise. (bfd_mach_x64_32_intel_syntax): Likewise. (bfd_mach_l1om): Likewise. (bfd_mach_l1om_intel_syntax): Likewise. (bfd_mach_k1om): Likewise. (bfd_mach_k1om_intel_syntax): Likewise. * bfd-in2.h: Regenerated. * cpu-i386.c (bfd_i386_compatible): Check mach instead of bits_per_address. (bfd_x64_32_arch_intel_syntax): Set bits_per_address to 64. (bfd_x64_32_arch): Likewise. * elf64-x86-64.c: Include "libiberty.h". (x86_64_elf_howto_table): Append x32 R_X86_64_32. (elf_x86_64_rtype_to_howto): Support x32 R_X86_64_32. (elf_x86_64_reloc_type_lookup): Likewise. (elf_x86_64_reloc_name_lookup): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_check_relocs): Allow R_X86_64_64 relocations for x32. gas/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * config/tc-i386.c (handle_quad): Removed. (md_pseudo_table): Remove "quad". (tc_gen_reloc): Don't check BFD_RELOC_64 for disallow_64bit_reloc. (x86_dwarf2_addr_size): New. * config/tc-i386.h (x86_dwarf2_addr_size): New. (DWARF2_ADDR_SIZE): Likewise. gas/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * gas/i386/ilp32/ilp32.exp: Don't run inval. * gas/i386/ilp32/inval.l: Removed. * gas/i386/ilp32/inval.s: Likewise. * gas/i386/ilp32/quad.d: Expect R_X86_64_64 instead of R_X86_64_32. * gas/i386/ilp32/x86-64-pcrel.s: Add tests for movabs. * gas/i386/ilp32/x86-64-pcrel.d: Updated. ld/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * ld-x86-64/ilp32-6.d: New. * ld-x86-64/ilp32-6.s: Likewise. * ld-x86-64/ilp32-7.d: Likewise. * ld-x86-64/ilp32-7.s: Likewise. * ld-x86-64/ilp32-8.d: Likewise. * ld-x86-64/ilp32-8.s: Likewise. * ld-x86-64/ilp32-9.d: Likewise. * ld-x86-64/ilp32-9.s: Likewise. * ld-x86-64/x86-64.exp: Run ilp32-6, ilp32-7, ilp32-8 and ilp32-9. opcodes/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * i386-dis.c (print_insn): Optimize info->mach check.	15 years ago

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