binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Jan Beulich	1424ad8677	x86: also optimize KXOR{D,Q} and KANDN{D,Q} These can be converted to 2-byte VEX encoding when both source registers are the same, by using KXORW / KANDNW as replacement.	8 years ago
Jan Beulich	ae2387feae	x86: fold various AVX512 templates with so far differing Masking attributes There's no insn allowing ZEROING_MASKING alone. Re-purpose its value for handling the not uncommon case of insns allowing either form of masking with register operands, but only merging masking with a memory operand.	8 years ago
Jan Beulich	fa77b93ab7	x86: add more exhaustive tests for invalid AVX512 zeroing-masking Before changing how things get handled, install a full set of tests, such that it can be demonstrated that the subsequent change doesn't break things.	8 years ago
Jan Beulich	6ff00b5e12	x86/Intel: correct permitted operand sizes for AVX512 scatter/gather AVX gather insns correctly allow the element size to be specified rather than the full vector size. Make AVX512 ones match.	8 years ago
Jan Beulich	7a8655d2bb	x86: don't abort() upon DATA16 prefix on (E)VEX encoded insn Instead of hitting the abort() in output_insn() (commented by "There should be no other prefixes for instructions with VEX prefix"), report a proper diagnostic instead, just like we do e.g. for invalid REP prefixes.	8 years ago
Jan Beulich	e951d5ca3d	x86: drop CpuVREX It is fully redundant with CpuAVX512F.	8 years ago
Jan Beulich	629cfaf1b0	x86: don't mistakenly scale non-8-bit displacements In commit `b5014f7af2` I've removed (instead of replaced) a conditional, resulting in addressing forms not allowing 8-bit displacements to now get their displacements scaled under certain circumstances. Re-add the missing conditional.	8 years ago
Andrew Jenner	b8891f8d62	Add support for the C_SKY series of processors. This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc. This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about. bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY. (BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise. * Makefile.in: Regenerated. * archures.c (enum bfd_architecture): Add bfd_arch_csky and related bfd_mach defines. (bfd_csky_arch): Declare. (bfd_archures_list): Add C-SKY. * bfd-in.h (elf32_csky_build_stubs): Declare. (elf32_csky_size_stubs): Declare. (elf32_csky_next_input_section: Declare. (elf32_csky_setup_section_lists): Declare. * bfd-in2.h: Regenerated. * config.bfd: Add C-SKY. * configure.ac: Likewise. * configure: Regenerated. * cpu-csky.c: New file. * elf-bfd.h (enum elf_target_id): Add C-SKY. * elf32-csky.c: New file. * libbfd.h: Regenerated. * reloc.c: Add C-SKY relocations. * targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare. (_bfd_target_vector): Add C-SKY target vector entries. binutils* readelf.c: Include elf/csky.h. (guess_is_rela): Handle EM_CSKY. (dump_relocations): Likewise. (get_machine_name): Likewise. (is_32bit_abs_reloc): Likewise. include * dis-asm.h (csky_symbol_is_valid): Declare. * opcode/csky.h: New file. opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c. * Makefile.in: Regenerated. * configure.ac: Add C-SKY. * configure: Regenerated. * csky-dis.c: New file. * csky-opc.h: New file. * disassemble.c (ARCH_csky): Define. (disassembler, disassemble_init_for_target): Add case for ARCH_csky. * disassemble.h (print_insn_csky, csky_get_disassembler): Declare. gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY. (TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise. * Makefile.in: Regenerated. * config/tc-csky.c: New file. * config/tc-csky.h: New file. * config/te-csky_abiv1.h: New file. * config/te-csky_abiv1_linux.h: New file. * config/te-csky_abiv2.h: New file. * config/te-csky_abiv2_linux.h: New file. * configure.tgt: Add C-SKY. * doc/Makefile.am (CPU_DOCS): Add entry for C-SKY. * doc/Makefile.in: Regenerated. * doc/all.texi: Set CSKY feature. * doc/as.texi (Overview): Add C-SKY options. (Machine Dependencies): Likewise. * doc/c-csky.texi: New file. * testsuite/gas/csky/: New test cases. ld Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations. (ecskyelf.c, ecskyelf_linux.c): New rules. * Makefile.in: Regenerated. * configure.tgt: Add C-SKY. * emulparams/cskyelf.sh: New file. * emulparams/cskyelf_linux.sh: New file. * emultempl/cskyelf.em: New file. * gen-doc.texi: Add C-SKY. * ld.texi: Likewise. (Options specific to C-SKY targets): New section. * testsuite/ld-csky/*: New tests.	8 years ago
John David Anglin	29e6f4745e	Fix unwind offset for start_symbol. * config/tc-hppa.c: Include "struc-symbol.h". (pa_build_unwind_subspace): Use call_info->start_symbol->sy_frag instead of frag_now for local symbol replacement.	8 years ago
Jim Wilson	d19969ffbf	RISC-V: Fix gas configure support for riscv--. gas/ configure.tgt (riscv): Accept as alias for riscv32.	8 years ago
H.J. Lu	1286ab7881	x86: Check for more than 2 memory references For movsd (%esi), %ss:(%edi), %ss:(%eax) we got [hjl@gnu-tools-1 tmp]$ as -o x.o x.s x.s: Assembler messages: x.s:1: Error: too many memory references for `movsd' munmap_chunk(): invalid pointer x.s:1: Internal error (Aborted). Please report this bug. [hjl@gnu-tools-1 tmp]$ struct _i386_insn has const seg_entry seg[2]; 3 memory references will overflow the seg array. We should issue an error if there are more than 2 memory references. PR gas/23453 config/tc-i386.c (parse_operands): Check for more than 2 memory references. * testsuite/gas/i386/inval.s: Add a movsd test with 3 memory references. * testsuite/gas/i386/x86-64-inval.s: Likewise. * testsuite/gas/i386/inval.l: Updated. * testsuite/gas/i386/x86-64-inval.l: Likewise.	8 years ago
H.J. Lu	1f75763aa1	x86: Initialize broadcast_op.bytes to 0 * config/tc-i386.c (check_VecOperations): Initialize broadcast_op.bytes to 0.	8 years ago
Alex Chadwick	fa758a7046	PowerPC Improve support for Gekko & Broadway This is a relatively straightforward patch to improve support for the IBM Gekko and IBM Broadway processors. Broadway is functionally equivalent to the IBM 750CL, while Gekko's functionality is a subset of theirs. The patch simplifies this reality and adds -mgekko and -mbroadway as aliases for -m750cl. I didn't feel it was worth wasting a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of simplified mnemonics for special purpose register access. Notably, Broadway adds 4 additional IBAT and DBAT registers but these are not assigned sequential SPR numbers. gas/ * config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway. * doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * testsuite/gas/ppc/broadway.d, * testsuite/gas/ppc/broadway.s: New test for broadway. * testsuite/gas/ppc/ppc.exp: Run new test. include/ * opcode/ppc.h (PPC_OPCODE_750): Adjust comment. opcodes/ * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. (powerpc_init_dialect): Handle bfd_mach_ppc_750. * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to support disjointed BAT. (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. (XSPRGQR_MASK, GEKKO, BROADWAY): Define. (powerpc_opcodes): Add 750cl extended mnemonics for spr access.	8 years ago
Alan Modra	33cb30a1f9	Implement PowerPC64 .localentry for value 1 This adds support for ".localentry 1", a new st_other STO_PPC64_LOCAL_MASK encoding that signifies a function with a single entry point like ".localentry 0", but unlike a ".localentry 0" function does not preserve r2. include/ * elf/ppc64.h: Specify byte offset to local entry for values of two to six in STO_PPC64_LOCAL_MASK. Clarify r2 return value for such functions when entering via global entry point. Specify meaning of a value of one in STO_PPC64_LOCAL_MASK. bfd/ * elf64-ppc.c (ppc64_elf_size_stubs): Use a ppc_stub_long_branch_r2off for calls to symbols with STO_PPC64_LOCAL_MASK bits set to 1. gas/ * config/tc-ppc.c (ppc_elf_localentry): Allow .localentry values of 1 and 7 to directly set value into STO_PPC64_LOCAL_MASK bits. ld/testsuite/ * ld-powerpc/elfv2.s: Add .localentry f5,1 testcase. * ld-powerpc/elfv2exe.d: Update. * ld-powerpc/elfv2so.d: Update.	8 years ago
H.J. Lu	4a1b91eabb	x86: Expand Broadcast to 3 bits Expand Broadcast to 3 bits so that the number of bytes to broadcast can be computed as 1 << (Broadcast - 1). Use it to simplify x86 assembler. gas/ * config/tc-i386.c (Broadcast_Operation): Add bytes. (build_evex_prefix): Use i.broadcast->bytes. (match_broadcast_size): New function. (check_VecOperands): Use the broadcast field to compute the number of bytes to broadcast directly. Set i.broadcast->bytes. Use match_broadcast_size. opcodes/ * i386-gen.c (adjust_broadcast_modifier): New function. (process_i386_opcode_modifier): Add an argument for operands. Adjust the Broadcast value based on operands. (output_i386_opcode): Pass operand_types to process_i386_opcode_modifier. (process_i386_opcodes): Pass NULL as operands to process_i386_opcode_modifier. * i386-opc.h (BYTE_BROADCAST): New. (WORD_BROADCAST): Likewise. (DWORD_BROADCAST): Likewise. (QWORD_BROADCAST): Likewise. (i386_opcode_modifier): Expand broadcast to 3 bits. * i386-tbl.h: Regenerated.	8 years ago
Thomas Preud'homme	5469110733	Clarify doc for .arch/.cpu Documentation for .arch and .cpu directives currently says that it accepts the same name as -march/-mcpu command-line options respectively. However it only accept the architecture/CPU part of those options: it does not accept specifying an extension which is done via .arch_extension. This patch clarifies that the extension is not accepted. 2018-07-25 Thomas Preud'homme <thomas.preudhomme@linaro.org> gas/ * doc/c-arm.texi (.arch directive): Clarify that name must not include an extension. (.cpu directive): Likewise.	8 years ago
H.J. Lu	56522fc5af	x86: Use unsigned int to iterate through vector operands Use unsigned int to iterate through multi-length vector operands to avoid sign-extension. * config/tc-i386.c (build_vex_prefix): Use unsigned int to iterate through multi-length vector operands. (build_evex_prefix): Likewise.	8 years ago
Jan Beulich	4174bfff8a	x86-64: correct AVX512F vcvtsi2s{d,s} handling Just like for their AVX counterparts and CVTSI2S{D,S}, a memory source here is ambiguous and hence - in source files should be qualified with a suitable suffix or operand size specifier (not doing so is an error in Intel mode, and will gain a diagnostic in AT&T mode in the future), - in disassembly should be properly suffixed (the Intel operand size specifiers were emitted correctly already).	8 years ago
H.J. Lu	e2b7fbc46d	x86: Add a test for missing broadcast For .intel_syntax noprefix vcvtps2qq xmm0, DWORD PTR [rax] we should get Error: broadcast is needed for operand of such type for `vcvtps2qq' * testsuite/gas/i386/inval-avx512f.s: Add a test for missing broadcast. * testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise. * testsuite/gas/i386/inval-avx512f.l: Updated. * testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.	8 years ago
H.J. Lu	c265869848	x86: Remove broadcast_not_on_src_operand Remove broadcast_not_on_src_operand since it is unused. * config/tc-i386.c (i386_error): Remove broadcast_not_on_src_operand. (match_template): Likewse.	8 years ago
Claudiu Zissulescu	04e65276fa	[ARC] Fix decoding of w6 signed short immediate. gas/ Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/st.d: Fix test. opcodes/ Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (extract_w6): Fix extending the sign.	8 years ago
claziss	f02806be1f	[ARC] Fix case-sensitivity for extension instructions. In ARC assembler, we accept case insensitive mnemonics, but this was not the case for extension instruction, fix it and add a test. gas/ Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (tokenize_extinsn): Convert to lower case the name of extension instructions. * testsuite/gas/arc/textinsn_case.d: New file. * testsuite/gas/arc/textinsn_case.s: Likewise.	8 years ago
H.J. Lu	c7213af9b3	x86: Determine vector length from the last vector operand Determine VEX/EVEXE vector length from the last multi-length vector operand. * config/tc-i386.c (build_vex_prefix): Determine vector length from the last multi-length vector operand. (build_evex_prefix): Likewise.	8 years ago
H.J. Lu	dd40ce22d0	gas/config/tc-i386.c: Break long line * config/tc-i386.c (match_simd_size): Break long line. (match_mem_size): Likewise.	8 years ago
H.J. Lu	7a54636a02	x86: Rename match_reg_size to match_operand_size match_reg_size checks size for both memory and register operands. This patch renamed match_reg_size to match_operand_size and updated comments for commit `3ac21baa84` Author: Jan Beulich <jbeulich@novell.com> Date: Mon Jul 16 08:19:21 2018 +0200 x86: fix operand size checking which added one argument to match_reg_size, match_simd_size and match_mem_size. * config/tc-i386.c (match_reg_size): Renamed to ... (match_operand_size): This. Update comments. (match_simd_size): Update comments. Replace match_reg_size with match_operand_size. (match_mem_size): Likewise. (operand_size_match): Replace match_reg_size with match_operand_size.	8 years ago
Chenghua Xu	8095d2f70e	MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a The MMI instruction set has been implemented in many Loongson processors. There is a lot of software optimized for MMI. This patch splits MMI from loongson2f/3a, and adds GAS and disassembler options for MMI instructions. 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com> Maciej W. Rozycki <macro@mips.com> bfd/ * elfxx-mips.c (print_mips_ases): Add MMI extension. binutils/ * readelf.c (print_mips_ases): Add MMI extension. gas/ * NEWS: Mention MultiMedia extensions Instructions (MMI) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and OPTION_NO_LOONGSON_MMI. (md_longopts): Likewise. (mips_ases): Define availability for MMI. (mips_convert_ase_flags): Map ASE_LOONGSON_MMI to AFL_ASE_LOONGSON_MMI. (mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a. (md_show_usage): Add help for -mloongson-mmi and -mno-loongson-mmi. * doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi. * doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi, .set loongson-mmi and .set noloongson-mmi. * testsuite/gas/mips/loongson-2f.d: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-2f.s: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.s: Here. * testsuite/gas/mips/loongson-3a.d: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-3a.s: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.s: Here. * testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and loongson-3a-mmi tests. include/ * elf/mips.h (AFL_ASE_MMI): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI. * opcode/mips.h (ASE_LOONGSON_MMI): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-mmi option. (print_mips_disassembler_options): Document -M loongson-mmi. * mips-opc.c (LMMI): New macro. (mips_opcodes): Replace IL2F\|IL3A marking with LMMI for MMI instructions.	8 years ago
Rainer Orth	0458ca4440	Specify architecture for SPARC gas tests A couple of SPARC gas tests FAIL on Solaris/SPARC (both sparc-sun-solaris2.11 and sparcv9-sun-solaris2.11): FAIL: sparc PAUSE FAIL: sparc CBCOND FAIL: sparc CFR FAIL: sparc CRYPTO FAIL: sparc HPC+VIS3 FAIL: sparc IMA FAIL: sparc OSA2015 %mwait asr and MWAIT instruction FAIL: sparc OSA2015 %mcdper asr FAIL: sparc SPARC5 and VIS4.0 FAIL: OSA2015 crypto instructions FAIL: SPARC6 FAIL: FPCMPSHL OSA2017 instructions FAIL: OSA2017 ONADD/ONSUB/ONMUL/ONDIV instructions. FAIL: OSA2017 RLE instructions FAIL: sparc64 rdasr FAIL: sparc64 rdpr FAIL: sparc64 rdhpr FAIL: sparc64 wrasr FAIL: sparc64 wrpr It turns out there's a common pattern here: failures happen for all tests that use SPARC ISA extensions beyond sparcv9, e.g. for the sparc PAUSE test: regexp_diff match failure regexp "^ 0: b7 80 40 02 wr %g1, %g2, %pause$" line " 0: b7 80 40 02 wr %g1, %g2, %asr27" [...] regexp_diff match failure regexp "^ 8: b7 80 20 08 pause 8$" line " 8: b7 80 20 08 wr 8, %asr27" [...] The fix is easy, actually: just as the tests specify the ISA extension to use as a gas flag, the same needs to be done for objdump. For the test above, which has -Av9v, this means passing -msparc:v9v to objdump. Doing so makes all but two (unrelated; to be reported separately) failures go away. This doesn't happen on Linux/SPARC, where gas emits GNU object attributes matching the hardcare capabilities used. Since gas doesn't yet implement Solaris-style object capabilites, the explicit -march is needed, but only passed on Solaris. Tested on both sparc-sun-solaris2.11 and sparcv9-sun-solaris2.11. * testsuite/gas/sparc/sparc.exp (set_tests_arch): New proc. Prefix v9c, v9d, v9v, v9m, v9m8 tests with corresponding set_tests_arch.	8 years ago
Jan Beulich	625cbd7ac1	x86: fold VFPCLASSP{D,S} templates These are special because they may not have a register operand to derive the vector length from, which requires to also deal with the braodcast case when determining vector length in build_evex_prefix(). Also drop IgnoreSize (and the now redundant size specifiers) from their suffixed counterparts.	8 years ago
Jan Beulich	8282b7ad0d	x86: fold various AVX512BW templates	8 years ago
Jan Beulich	7091c61201	x86: fold various AVX512VL templates into their AVX512F counterparts	8 years ago
Maciej W. Rozycki	972450a72c	MIPS/GAS/testsuite: Correct whitespace issues with Loongson tests Remove CR characters, trailing whitespace and space characters appearing immediately before a tab character, and replace spaces with tabs, all across Loongson GAS tests. gas/ * testsuite/gas/mips/loongson-2e.d: Correct whitespace issues. * testsuite/gas/mips/loongson-2f.d: Likewise. * testsuite/gas/mips/loongson-2f-2.d: Likewise. * testsuite/gas/mips/loongson-2f-3.d: Likewise. * testsuite/gas/mips/loongson-3a.d: Likewise. * testsuite/gas/mips/loongson-3a-2.d: Likewise. * testsuite/gas/mips/loongson-2e.s: Likewise. * testsuite/gas/mips/loongson-2f.s: Likewise. * testsuite/gas/mips/loongson-2f-3.s: Likewise. * testsuite/gas/mips/loongson-3a.s: Likewise. * testsuite/gas/mips/loongson-3a-2.s: Likewise.	8 years ago
H.J. Lu	11a322db5c	x86: Split vcvtps2{,u}qq and vcvttps2{,u}qq After commit `1b54b8d7e4` Author: Jan Beulich <jbeulich@novell.com> Date: Mon Dec 18 09:36:14 2017 +0100 x86: fold RegXMM/RegYMM/RegZMM into RegSIMD ... qualified by their respective sizes, allowing to drop FirstXmm0 at the same time. folded RegXMM, RegYMM and RegZMM into RegSIMD, it's no longer impossible to distinguish if Xmmword can represent a memory reference when operand specification contains SIMD register. For example, template operands specification like these RegXMM\|...\|Xmmword\|... and RegXMM\|... The Xmmword bitfield is always set by RegXMM which is represented by "RegSIMD\|Xmmword". This patch splits each of vcvtps2qq, vcvtps2uqq, vcvttps2qq and vcvttps2uqq into 2 templates: one template only has RegXMM source operand and the other only has mempry source operand. gas/ PR gas/23418 * testsuite/gas/i386/xmmword.s: Add tests for vcvtps2qq, vcvtps2uqq, vcvttps2qq and vcvttps2uqq. * testsuite/gas/i386/xmmword.l: Updated. opcodes/ PR gas/23418 * i386-opc.h (Byte): Update comments. (Word): Likewise. (Dword): Likewise. (Fword): Likewise. (Qword): Likewise. (Tbyte): Likewise. (Xmmword): Likewise. (Ymmword): Likewise. (Zmmword): Likewise. * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and vcvttps2uqq. * i386-tbl.h: Regenerated.	8 years ago
Jan Beulich	3ac21baa84	x86: fix operand size checking Currently mov to/from control, debug, and test register insns accept any size GPR operand (general pattern: templates with D set and both operands being registers in distinct register files). This is due to improper checking of the reverse case, including not informing the caller whether a straight and/or reverse match was successful. The helper functions need to be told two indexes: One to index the given operand types array, and the other to index the template one. The caller must attempt a further straight match only if the function reported a straight match (and respectively for reverse matches).	8 years ago
Nick Clifton	b84f59efc6	Add a test that relocs are correctly generated for missing build notes. * testsuite/gas/elf/missing-build-notes.s: New test. Checks that relocs are correctly generated for missing build notes. * testsuite/gas/elf/missing-build-notes.d: New file. Expected output from objdump. * testsuite/gas/elf/elf.exp: Run the new test.	8 years ago
Nick Clifton	4ef4710f5c	Allow bit-patterns in the immediate field of ARM neon mov instructions. * config/tc-arm.c (do_neon_mov): When converting an integer immediate into a floating point value, check that the conversion is valid. Also warn if the immediate is valid as both a floating point value and a bit pattern. * testsuite/gas/arm/vfp-mov-enc.s: Add instructions that use floating point bit patterns. * testsuite/gas/arm/vfp-mov-enc.d: Add regexps for the disassembly of the new insns.	8 years ago
Nick Clifton	cde3679eb5	This patch adds support for the SSBB and PSSBB speculation barrier instructions to the AArch64 assembler and disassembler. For more details see: https://static.docs.arm.com/ddi0596/a/DDI_0596_ARM_a64_instruction_set_architecture.pdf opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entry for ssbb and pssbb and update dsb flags to F_HAS_ALIAS. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.s: Add test for ssbb and pssbb. * testsuite/gas/aarch64/system.d: Update accordingly and remove explicit addresses.	8 years ago
Tamar Christina	45a28947f3	Add remainder of Em16 restrictions for AArch64 gas. This adds the missing Em16 constraints the rest of the instructions requiring them and also adds a testcase to test all the instructions so these are checked from now on. The Em16 operand constrains the valid registers to the lower 16 registers when used with a half precision qualifier. The list has been cross checked (by hand) through the Arm ARM version Ca. opcodes/ PR binutils/23192 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2, mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal, umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull, sqdmulh, sqrdmulh): Use Em16. gas/ PR binutils/23192 * testsuite/gas/aarch64/illegal-by-element.s: New. * testsuite/gas/aarch64/illegal-by-element.d: New. * testsuite/gas/aarch64/illegal-by-element.l: New.	8 years ago
Sudakshina Das	c597cc3d6e	Adds the speculation barrier instructions to the ARM assembler and disassembler. See: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/download-the-whitepaper opcodes * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move csdb together with them. (thumb32_opcodes): Likewise. gas * config/tc-arm.c (insns): Add new ssbb and pssbb instructions. * testsuite/gas/arm/csdb.s: Add new tests for ssbb and pssbb. * testsuite/gas/arm/csdb.d: Likewise * testsuite/gas/arm/thumb2_it_bad.s: Likewise. * testsuite/gas/arm/thumb2_it_bad.l: Likewise. * testsuite/gas/arm/barrier.d: Update with ssbb. * testsuite/gas/arm/barrier-thumb.d: Likewise.	8 years ago
Jan Beulich	2fb5be8dac	x86: drop {,reg16_}inoutportreg variables The checking against reg16_inoutportreg can be had with a simple test of a bit, and the value setting from inoutportreg can be replaced by using the actual register's reg_type field. Note that the so far redundant 2nd instance of OPERAND_TYPE_INOUTPORTREG is left in place, for its use in type_names[].	8 years ago
Jan Beulich	bd59a6313d	x86: simplify legacy prefix emission The check_prefix label was bogus from the beginning: The special checking is supposed to happen for PadLock insns only; no 3-opcode-byte insn should go this path.	8 years ago
Jan Beulich	7f5cad3047	x86/Intel: accept memory operand size specifiers for CET insns	8 years ago
Jan Beulich	76d3a78a49	x86: fix "REP RET" with -madd-bnd-prefix Just like any other branches, RET should gain a BND prefix also when already prefixed in source by REP.	8 years ago
Jeff Law	2af4d0d938	* testsuite/nds32/ji-jr.d: Fix name tag.	8 years ago
Tamar Christina	cba05feb51	Fix the read/write flag for these registers on AArch64 The previous constraints were based on information already in opcodes and it seems that a few of them were wrong. I have now hand verified the ones changed by the previous patch and corrected where needed. This prevents a warning to be issued when one shouldn't be. opcodes/ PR binutils/23369 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. gas/testsuite/ PR binutils/23369 * gas/aarch64/msr.d (csselr_el1, vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1): New. * gas/aarch64/msr.s: Likewise.	8 years ago
Nick Clifton	2e48456f02	Fix the relocs created to adjust notes created by the assembler. * write.c (maybe_generate_build_notes): Bias reloc offsets by the number of notes already generated.	8 years ago
Nick Clifton	d8dab05495	Updated Russian, Bulgarian, and Brazilian Portuguese translations for various components of the binutuls. ld * po/bg.po: Updated Bulgarian translation. * po/pt_BR.po: Updated Brazilian Portuguese translation. binutils* po/bg.po: Updated Bulgarian translation. bfd,gas * po/ru.po: Updated Russian translation.	8 years ago
Maciej W. Rozycki	14c80123c0	microMIPS/GAS: Handle several percent-ops with macros In the microMIPS mode also accept %half, %got, %call, %got_hi, %got_lo, %call_hi, %call_lo, %neg, %got_page, %highest, %got_disp, %tlsgd, %tlsldm, %dtprel_hi, %dtprel_lo, %gottprel, %tprel_hi and %tprel_lo percent-ops with macros, so that they can be used with instructions that expand into sequences if relocation is required due to their limited offset span, such as LL, LWL, etc., fixing GAS assertions: .../gas/testsuite/gas/mips/elf-rel28.s: Assembler messages: .../gas/testsuite/gas/mips/elf-rel28.s:17: Internal error in macro_build at .../gas/config/tc-mips.c:8854. Please report this bug. observed if an attempt is made to assemble the `elf-rel28.s' test case modified to use one of the affected instructions to microMIPS code. gas/ * config/tc-mips.c (macro_build) <'i', 'j'>: Also accept BFD_RELOC_16, BFD_RELOC_MIPS_GOT16, BFD_RELOC_MIPS_CALL16, BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MIPS_SUB, BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MIPS_TLS_TPREL_HI16 and BFD_RELOC_MIPS_TLS_TPREL_LO16 relocations if in the microMIPS mode. * testsuite/gas/mips/elf-rel28-lldscd-n32.d: New test. * testsuite/gas/mips/elf-rel28-lldscd-micromips-n32.d: New test. * testsuite/gas/mips/elf-rel28-lldscd-n64.d: New test. * testsuite/gas/mips/elf-rel28-lldscd-micromips-n64.d: New test. * testsuite/gas/mips/elf-rel28.s: Add instruction selection. * testsuite/gas/mips/mips.exp: Run the new tests.	8 years ago
Maciej W. Rozycki	156f2c001e	microMIPS/BFD: Add missing NewABI TLS and miscellaneous relocations Complement commit `df58fc944d` ("MIPS: microMIPS ASE support"), <https://sourceware.org/ml/binutils/2011-07/msg00198.html>, and add TLS and a few miscellaneous relocations to NewABI microMIPS support, fixing GAS assertion failures: .../gas/testsuite/gas/mips/elf-rel28.s: Assembler messages: .../gas/testsuite/gas/mips/elf-rel28.s:19: Internal error in append_insn at .../gas/config/tc-mips.c:7660. Please report this bug. observed if an attempt is made to assemble the `elf-rel28.s' test case to microMIPS code. The relocations are the same as with o32 support, except for `partial_inplace' and `src_mask' updates for the respective RELA variants. bfd/ * elf64-mips.c (micromips_elf64_howto_table_rel): Add R_MICROMIPS_HI0_LO16, R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM, R_MICROMIPS_TLS_DTPREL_HI16, R_MICROMIPS_TLS_DTPREL_LO16, R_MICROMIPS_TLS_GOTTPREL, R_MICROMIPS_TLS_TPREL_HI16, R_MICROMIPS_TLS_TPREL_LO16, R_MICROMIPS_GPREL7_S2 and R_MICROMIPS_PC23_S2 relocation entries. (micromips_elf64_howto_table_rela): Likewise. (micromips_reloc_map): Likewise. * elfn32-mips.c (elf_micromips_howto_table_rel): Likewise. (elf_micromips_howto_table_rela): Likewise. (micromips_reloc_map): Likewise. gas/ * testsuite/gas/mips/elf-rel28-micromips-n32.d: New test. * testsuite/gas/mips/elf-rel28-micromips-n64.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests.	8 years ago
Thomas Preud'homme	c0c468d562	[ARM] Update bfd's Tag_CPU_arch knowledge BFD's bfd_get_mach () function returns a bfd specific value representing the architecture of the target which is populated from the Tag_CPU_arch build attribute value of that target. Among other users of that interfacem, objdump which uses it to print the architecture version of the binary being examinated and to decide what instruction is available if run with "-m arm" via its own mapping from bfd_mach_arm_X values to feature bits available. However, both BFD and objdump's most recent known architecture is Armv5TE. When encountering a newer architecture bfd_get_mach will return bfd_mach_arm_unknown. This is unfortunate since objdump uses that value to allow all instructions on all architectures which is already what it does by default, making the "-m arm" trick useless. This patch updates BFD and objdump's knowledge of Arm architecture versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A) share the same Tag_CPU_arch build attribute value and bfd_mach_arm values, the mapping from bfd machine value to feature bits need to return the most featureful feature bits that would yield the given bfd machine value otherwise some instruction would not disassemble under "-m arm" mode. The patch rework that mapping to make this clearer and simplify writing the mapping rules. In particular, for simplicity all FPU instructions are allowed in all cases. Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the TAG_CPU_ARCH_X macros rather than hardcode their value. 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ, bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M, bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R, bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entries for above new bfd_mach_arm values. * elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later architectures. Force assert failure for any new Tag_CPU_arch value. gas/ * config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros rather than hardcode their values. ld/ * arm-dis.c (select_arm_features): Fix typo in heading comment. Allow all FPU features and add mapping from new bfd_mach_arm values to allowed CPU feature bits. opcodes/ * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in expected result. * testsuite/ld-arm/tls-descrelax-v7.d: Likewise. * testsuite/ld-arm/tls-longplt-lib.d: Likewise. * testsuite/ld-arm/tls-longplt.d: Likewise.	8 years ago
Thomas Preud'homme	a05a5b64cf	Fix use of "command line X" in binutils doc Binutils documentation uses a mix of spelling for the compound word "command-line X". According to [1]: "Sometimes compound words are written separately (nail polish), sometimes with a hyphen (short-sighted) and sometimes as one word (eyelashes). Often new compounds are written as two separate words and, as they become more familiar, they are either connected with a hyphen (-) or made into one word." I think command-line X is common enough in our industry that the two workds command and line should be connected. Since command-line is more common than commandline, I propose to update binutils documentation to consistently use "command-line" when this is used as an adjective to a noun (eg. command-line argument, command-line switch, command-line option and command-line flag). I've left occurences of "the command line" as is. I've also left gdb, sim and readline alone and have only touched public documentation (texi and NEWS files). [1] http://dictionary.cambridge.org/grammar/british-grammar/word-formation/compounds 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * doc/bfdint.texi: Use command-line consistently when used in a compount word. * doc/bfdsumm.texi: Likewise. binutils/ * NEWS: Use command-line consistently when used in a compount word. * doc/binutils.texi: Likewise and fix trailing whitespace on same line. gas/ * NEWS: Use command-line consistently when used in a compount word. * doc/as.texi: Likewise. * doc/c-aarch64.texi: Likewise. * doc/c-alpha.texi: Likewise. * doc/c-arc.texi: Likewise. * doc/c-arm.texi: Likewise. * doc/c-avr.texi: Likewise. * doc/c-bfin.texi: Likewise. * doc/c-cris.texi: Likewise. * doc/c-epiphany.texi: Likewise. * doc/c-i386.texi: Likewise. * doc/c-ia64.texi: Likewise. * doc/c-lm32.texi: Likewise. * doc/c-m32r.texi: Likewise. * doc/c-m68k.texi: Likewise. * doc/c-mips.texi: Likewise. * doc/c-mmix.texi: Likewise. * doc/c-msp430.texi: Likewise. * doc/c-mt.texi: Likewise. * doc/c-nios2.texi: Likewise. * doc/c-ppc.texi: Likewise. * doc/c-pru.texi: Likewise. * doc/c-rl78.texi: Likewise. * doc/c-rx.texi: Likewise. * doc/c-tic6x.texi: Likewise. * doc/c-v850.texi: Likewise. * doc/c-vax.texi: Likewise. * doc/c-visium.texi: Likewise. * doc/c-xstormy16.texi: Likewise. * doc/c-xtensa.texi: Likewise. * doc/c-z80.texi: Likewise. * doc/c-z8k.texi: Likewise. * doc/internals.texi: Likewise. gprof/ * gprof.texi: Use command-line consistently when used in a compount word. ld/ * NEWS: Use command-line consistently when used in a compount word. * ld.texinfo: Likewise. * ldint.texinfo: Likewise.	8 years ago

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8538 Commits (472fa5eec2cc521ad5ea37091ea2424ea46552ae)