binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Jim Wilson	e925c834ec	RISC-V: Fix bug in prior addi/c.nop patch. gas/ * config/tc-riscv.c (validate_riscv_insn) <'z'>: New. (riscv_ip) <'z'>: New. opcodes/ * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.	9 years ago
Jim Wilson	2721d702a0	RISC-V: Add support for addi that compresses to c.nop. gas/ * testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop. * testsuite/gas/riscv/c-zero-imm.d: Likewise. opcodes/ * riscv-opc.c (match_c_nop): New. (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.	9 years ago
Alan Modra	219d1afa89	Update year range in copyright notice of binutils files	9 years ago
Jim Wilson	21a186f280	RISC-V: Add compressed instruction hints, and a few misc cleanups. gas/ * config/tc-riscv.c (risc_ip) <o>: Add comment. * testsuite/gas/riscv/c-nonzero-imm.d, * testsuite/gas/riscv/c-nonzero-imm.l, * testsuite/gas/riscv/c-nonzero-imm.s, * testsuite/gas/riscv/c-nonzero-reg.d, * testsuite/gas/riscv/c-nonzero-reg.l, * testsuite/gas/riscv/c-nonzero-reg.s, * testsuite/gas/riscv/c-zero-imm-64.d, * testsuite/gas/riscv/c-zero-imm-64.s, * testsuite/gas/riscv/c-zero-imm.d, testsuite/gas/riscv/c-zero-imm.s, * testsuite/gas/riscv/c-zero-reg.d, * testsuite/gas/riscv/c-zero-reg.s: New. opcodes/ * riscv-opc.c (match_c_add_with_hint, match_c_lui_with_hint): New. (riscv_opcodes) <li>: Delete "d,0" line. Change Cj to Co. <andi, and, add, addiw, addw, c.addi>: Change Cj to Co. <add>: Add explanatory comment for 4-operand add instruction. <c.nop>: Add support for immediate operand. <c.mv, c.add>: Use match_c_add_with_hint instead of match_c_add. <c.lui>: Use match_c_lui_with_hint instead of match_c_lui. <c.li, c.slli>: Use match_opcode instead of match_rd_nonzero.	9 years ago
Jim Wilson	25982ee022	Add missing RISC-V fsrmi and fsflagsi instructions. PR 22599 gas/ * testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New. opcodes/ * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.	9 years ago
Andrew Waterman	63a25ea0de	RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 These are all invalid instructions, so they should not disassemble. opcodes/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (match_c_addi16sp) : New function. (match_c_addi4spn): New function. (match_c_lui): Don't allow 0-immediate encodings. (riscv_opcodes) <addi>: Use the above functions. <add>: Likewise. <c.addi4spn>: Likewise. <c.addi16sp>: Likewise. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-addi16sp-fail.d: New test. testsuite/gas/riscv/c-addi16sp-fail.l: Likewise. testsuite/gas/riscv/c-addi16sp-fail.s: Likewise. testsuite/gas/riscv/c-addi4spn-fail.d: Likewise. testsuite/gas/riscv/c-addi4spn-fail.l: Likewise. testsuite/gas/riscv/c-addi4spn-fail.s: Likewise. testsuite/gas/riscv/riscv.exp: Add new tests.	9 years ago
Nick Clifton	8e43602e34	Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions, vis: fmv.x.w and fmv.w.x. PR 22179 opcodes * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new names for the fmv.x.s and fmv.s.x instructions respectively. gas * testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the renamed fmv.x.s and fmv.s.x instructions. * testsuite/gas/riscv/fmv.x.d: New file: Test driver.	9 years ago
Palmer Dabbelt	67d888f5c8	RISC-V: Mark "c.nop" as an alias This fixes "-M noaliases" disassembly for "c.nop", which is an alias for "c.addi x0, 0". opcodes/ChangeLog 2017-08-01 Palmer Dabbelt <palmer@dabbelt.com> * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.	9 years ago
Andrew Waterman	9bdfdbf929	RISC-V: Fix SLTI disassembly 2017-06-23 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an alias; do not mark SLTI instruction as an alias.	9 years ago
Michael Clark	43e379d74c	RISC-V: Change CALL macro to use ra as the temporary address register e.g. 1: auipc ra, %pcrel_hi(symbol) jalr ra, %pcrel_lo(1b)(ra) The use of ra instead of t1 for address construction provides an opportunity for a microarchitecture to elide the write of the destination address, and instead read the target address as an immediate spread across the fused auipc+jalr pair. The link register ra in the jalr overwrites the target address temporary. 2017-05-01 Michael Clark <michaeljclark@mac.com> * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary register.	9 years ago
Kito Cheng	b416fe873e	RISC-V: Fix assembler for c.li, c.andi and c.addiw - They can accept 0 in imm field 2017-03-14 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. <c.andi>: Likewise. <c.addiw> Likewise.	10 years ago
Kito Cheng	03b039a518	RISC-V: Fix assembler for c.addi, rd can be x0 opcodes/ChangeLog: 2017-03-14 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.	10 years ago
Andrew Waterman	2c232b8361	RISC-V: Fix [dis]assembly of srai/srli These were simple copy/paste errors from the compressed left shift pattern, which can't have a 0-register.	10 years ago
Andrew Waterman	f98d33be3a	Add SFENCE.VMA instruction include/ChangeLog: 2017-02-14 Andrew Waterman <andrew@sifive.com> * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define. (MASK_SFENCE_VMA): Likewise. (sfence_vma): Declare instruction. opcodes/ChangeLog: 2017-02-14 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and pseudoinstructions.	10 years ago
Kito Cheng	cc917fd93d	Add support for the Q extension to the RISCV ISA. gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA extension. (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is enabled and no other ABI is specified. include * opcode/riscv-opc.h: Add support for the "q" ISA extension. opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA extension. * riscv-opcodes/all-opcodes: Likewise.	10 years ago
Alan Modra	2571583aed	Update year range in copyright notice of all files.	10 years ago
Andrew Waterman	58a6d3c9d8	Avoid creating symbol table entries for registers Instructions like "jal t0, foo" were erroneously creating symbol table entries for t0 as well as foo, which causes linking problems. Fix by reordering instruction alternatives so that t0 is first attempted to be parsed as a register, rather than as a symbol. * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.	10 years ago
Andrew Waterman	3e67a37820	Correct assembler mnemonic for RISC-V aqrl AMOs sc is a misnomer, because they aren't inherently sc. * riscv-opc.c (riscv_opcodes): Rename the ".sc" instructions to ".aqrl".	10 years ago
Andrew Waterman	04386d9ed5	Fix disassembly of RISC-V CSR instructions under -Mno-aliases This fixes https://github.com/riscv/riscv-binutils-gdb/issues/36. * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as INSN_ALIAS.	10 years ago
Andrew Waterman	755c5297bd	Add canonical JALR for RISC-V jalr rd,offset(rs1) rather than jalr rd,rs1,offset This matches the format of other instructions. * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)" format.	10 years ago
Andrew Waterman	1d65abb5e2	Formatting changes for RISC-V This is a mixed bag of format changes: * Replacing constants with macros (0xffffffff with MINUS_ONE, for example). There's one technically functional change in here (some MINUS_ONEs are changed to 0), but it only changes the behavior of an otherwise-unused field. * Using 0 instead of 0x0 in the relocation table. * There were some missing spaces before parens, the spaces have been added. * A handful of comments are now more descriptive. * A bunch of whitespace-only changes, mostly alignment and brace newlines. bfd/ * elfnn-riscv.c: Formatting and comment fixes throughout. * elfxx-riscv.c: Likewise. (howto_table): Change the src_mask field from MINUS_ONE to 0 for R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32, R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64. opcodes/ * riscv-opc.c: Formatting fixes. gas/ * config/tc-riscv.c: Formatting and comment fixes throughout.	10 years ago
Nick Clifton	e23eba971d	Add support for RISC-V architecture. bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.	10 years ago

1 2

72 Commits (41d6ac5da655a2e78109848f2db47e53552fd61a)